Multiplex communication circuit and electronic device

Abstract

The utility model discloses a multiplexing communication circuit. The multiplexing communication circuit adopts a multiplexing communication terminal to provide communication connection for master equipment and slave equipment. A first communication circuit is arranged to cooperate with a multiplexing communication terminal, so that a master device performs data interaction with a slave device through a first communication protocol; and a second communication circuit is arranged to be matched with the multiplexing communication terminal, so that the master equipment can perform data interaction with the slave equipment through a second communication protocol. Therefore, the master device can control the first communication circuit and the second communication circuit to alternately work in a time-sharing manner, so that one communication terminal can multiplex two communication protocols in a time-sharing manner to carry out data interaction with the slave device, redundant wiring and slave device connection are reduced, and the structure of the whole circuit hardware is simplified. In addition, the utility model also discloses an electronic device.

Description

Technical Field

[0001] The utility model relates to the technical field of communication, in particular to a multiplexing communication circuit and electronic equipment. Background Art

[0002] UART and IIC are two different communication protocols. In some applications, the communication between the master device and the slave device may adopt the UART communication protocol or the IIC communication protocol. For this application scenario, the solution adopted by the relevant technology is: the master device is connected to the slave device through two independent communication circuits, that is, UART and IIC use two completely independent circuits for communication.

[0003] The above-mentioned related technical solutions have the following shortcomings in specific applications: in the scenario where both UART and IIC communication protocols need to be supported, the communication circuits of each communication protocol are designed separately and independently, which leads to the problems of complex structure, large size and high cost of the overall circuit hardware. Utility Model Content

[0004] The main purpose of the utility model is to provide a multiplexed communication circuit, aiming to solve the problem in the prior art that two communication protocols require two independent communication circuits, resulting in complex circuit hardware structure and high cost.

[0005] To achieve the above object, the utility model provides a multiplexing communication circuit, which includes:

[0006] Multiplexed communication terminals are used to provide communication connections between master and slave devices;

[0007] a first communication circuit, wherein the first communication circuit is communicatively connected to the master device and the multiplexed communication terminal respectively, and the first communication circuit is used to cooperate with the multiplexed communication terminal to allow the master device to perform data exchange with the slave device using a first communication protocol;

[0008] a second communication circuit, the second communication circuit being communicatively connected to the master device and the multiplexed communication terminal respectively, and the second communication circuit being used to cooperate with the multiplexed communication terminal so that the master device can perform data exchange with the slave device using a second communication protocol;

[0009] The first communication circuit and the second communication circuit are used to perform time-sharing switching under the control of the master device.

[0010] In some embodiments, the multiplexed communication terminal includes a first data transmitting terminal and a first data receiving terminal;

[0011] The first communication circuit comprises a first communication terminal, a second communication terminal, a third communication terminal, a fourth communication terminal and a first control terminal, wherein the first communication terminal and the second communication terminal are electrically connected to two first communication pins of the master device respectively, the first control terminal is electrically connected to a control pin of the master device, the third communication terminal is electrically connected to the first data sending terminal, and the fourth communication terminal is electrically connected to the first data receiving terminal;

[0012] The second communication circuit has a fifth communication terminal, a sixth communication terminal, a seventh communication terminal, an eighth communication terminal and a second control terminal. The fifth communication terminal and the sixth communication terminal are electrically connected to the two second communication pins of the main device respectively, the seventh communication terminal is electrically connected to the first data sending terminal, and the eighth communication terminal is electrically connected to the first data receiving terminal.

[0013] In some embodiments, the third communication terminal is electrically connected to the seventh communication terminal, and the fourth communication terminal is electrically connected to the eighth communication terminal;

[0014] The first communication terminal, the second communication terminal, the third communication terminal, and the fourth communication terminal are all UART communication terminals, and the fifth communication terminal, the sixth communication terminal, the seventh communication terminal, and the eighth communication terminal are all IIC communication terminals.

[0015] In some embodiments, the first communication circuit includes a signal direction control module, and the signal direction control module includes:

[0016] A first conducting end, the first conducting end being electrically connected to the first communication end;

[0017] a second conducting end, the second conducting end being electrically connected to the second communication end;

[0018] A third conducting end, the third conducting end being electrically connected to the third communication end;

[0019] a fourth conducting end, the fourth conducting end being electrically connected to the fourth communication end;

[0020] an enabling terminal, the enabling terminal being electrically connected to the first control terminal;

[0021] The second communication circuit includes a data isolation module, a clock isolation module and an on-off control terminal, the input terminal of the clock isolation module is electrically connected to the fifth communication terminal, and the output terminal of the clock isolation module is electrically connected to the seventh communication terminal;

[0022] The input end of the data isolation module is electrically connected to the sixth communication end, and the output end of the data isolation module is electrically connected to the eighth communication end;

[0023] The on-off control terminal is communicatively connected with the first control terminal.

[0024] In some embodiments, the signal direction control module further includes a first direction control terminal and a second direction control terminal;

[0025] The first communication circuit further includes:

[0026] A pull-down resistor, one end of which is connected to the cathode, and the other end of which is electrically connected to the first direction control end;

[0027] A pull-up resistor has one end connected to the positive electrode and the other end electrically connected to the second direction control end.

[0028] In some embodiments, the signal direction control module is a three-state buffer chip of model SN74AXC2T245.

[0029] In some embodiments, the data isolation module includes:

[0030] a first switch tube, wherein a source of the switch tube is electrically connected to an input end of the data isolation module, and a gate of the first switch tube is electrically connected to a control pin of the master device;

[0031] a second switch tube, wherein a drain of the second switch tube is electrically connected to a drain of the first switch tube, a source of the second switch tube is electrically connected to an output end of the data isolation module, and a gate of the second switch tube is electrically connected to a control pin of the master device;

[0032] The clock isolation module comprises:

[0033] a third switch tube, wherein a source of the third switch tube is electrically connected to an input end of the clock isolation module, and a gate of the third switch tube is communicatively connected to a control pin of the master device;

[0034] A fourth switch tube, wherein the drain of the fourth switch tube is electrically connected to the drain of the third switch tube, the source of the fourth switch tube is electrically connected to the output end of the clock isolation module, and the gate of the fourth switch tube is electrically connected to the control pin of the master device.

[0035] In some embodiments, the data isolation module further includes:

[0036] Two first resistors, one end of each of the two first resistors is connected to the positive electrode of the power supply, and the other end of each of the two first resistors is connected to the gate of the first switch tube and the gate of the second switch tube respectively;

[0037] The clock isolation module comprises:

[0038] Two second resistors, one end of the two second resistors are connected to the positive electrode of the power supply, and the other ends of the two second resistors are respectively connected to the gate of the third switch tube and the gate of the fourth switch tube.

[0039] In some embodiments, the data isolation module further includes:

[0040] Two third resistors, one end of each of the two third resistors is connected to the positive electrode of the power supply, and the other end of each of the two third resistors is connected to the source electrode of the first switch tube and the source electrode of the second switch tube respectively;

[0041] The clock isolation module comprises:

[0042] Two fourth resistors, one end of each of the two fourth resistors is connected to the positive electrode of the power supply, and the other end of each of the two fourth resistors is connected to the source of the third switch tube and the source of the fourth switch tube respectively.

[0043] The utility model further provides an electronic device, comprising a master device and a slave device, and the multiplexing communication circuit of the aforementioned embodiment, wherein the multiplexing communication circuit is arranged between the master device and the slave device.

[0044] In the technical solution of this embodiment, a multiplexed communication terminal is used to provide communication connection for the master device and the slave device. By setting a first communication circuit to cooperate with the multiplexed communication terminal, the master device can interact with the slave device through the first communication protocol; and then by setting a second communication circuit to cooperate with the multiplexed communication terminal, the master device can interact with the slave device through the second communication protocol. In this way, the master device can control the first communication circuit and the second communication circuit to work alternately in time-sharing, so as to interact with the slave device through two communication protocols in time-sharing multiplexing through one communication terminal. In this way, redundant wiring and slave device connections are reduced, and the overall circuit hardware structure is simplified. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 This is a schematic diagram of the electrical connection of modules of a multiplexed communication circuit in one embodiment of the utility model;

[0046] Figure 2 A circuit diagram of a multiplexed communication circuit in one embodiment of the utility model;

[0047] Figure 3 It is a circuit diagram of a multiplexed communication circuit in one embodiment of the utility model.

[0048] Description of Figure Numbers:

[0049] 100, master device; 102, first communication pin; 104, second communication pin; 106, control pin; 200, slave device; 300, multiplexed communication terminal; 302, first data sending terminal; 304, first data receiving terminal; 400, first communication circuit; 401, first communication terminal; 402, second communication terminal; 403, third communication terminal; 404, fourth communication terminal; 406, first control terminal; 410, signal direction control module; 411, first conduction terminal; 412, second conduction terminal; 413, third conduction terminal; 414, fourth conduction terminal; 416, enable terminal ; 417, first direction control terminal; 418, second direction control terminal; R1, pull-down resistor; R2, pull-up resistor; 500, second communication circuit; 502, fifth communication terminal; 504, sixth communication terminal; 506, seventh communication terminal; 508, eighth communication terminal; 509, second control terminal; 510, data isolation module; Q1, first switch tube; Q2, second switch tube; R3, two first resistors; R4, two third resistors; 520, clock isolation module; Q3, third switch tube; Q4, fourth switch tube; R5, two second resistors; R6, two fourth resistors; G1, on-off control terminal.

[0050] The realization of the purpose, functional features and advantages of the utility model will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0051] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the scheme in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0052] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back...) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0053] It should also be noted that when an element is referred to as being "fixed on" or "disposed on" another element, it may be directly on the other element or there may be an intermediate element at the same time. When an element is referred to as being "connected to" another element, it may be directly connected to the other element or there may be an intermediate element at the same time.

[0054] In addition, the descriptions of "first", "second", etc. in the present utility model are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in this field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present utility model.

[0055] Reference Figure 1 , Figure 1 The figure is a schematic diagram of the electrical connection of modules of the multiplexing communication circuit in one embodiment of the utility model.

[0056] The multiplexing communication circuit proposed in the embodiment of the utility model includes:

[0057] The multiplexed communication terminal 300 is used to provide a communication connection between the master device 100 and the slave device 200;

[0058] A first communication circuit 400, the first communication circuit 400 is respectively connected to the master device 100 and the multiplexed communication terminal 300 for communication, and the first communication circuit 400 is used to cooperate with the multiplexed communication terminal 300 to allow the master device 100 to exchange data with the slave device 200 using a first communication protocol;

[0059] The second communication circuit 500 is respectively connected to the master device 100 and the multiplexed communication terminal 300 for communication. The second communication circuit 500 is used to cooperate with the multiplexed communication terminal 300 to allow the master device 100 to perform data exchange with the slave device 200 using the second communication protocol;

[0060] The first communication circuit 400 and the second communication circuit 500 are used to perform time-sharing switching under the control of the master device 100 .

[0061] In this embodiment, the first communication circuit 400 and the second communication circuit 500 can be adapted to different communication protocols respectively. Specifically, the first communication circuit 400 is applicable to the UART (Universal Asynchronous Receiver / Transmitter) protocol, and the second communication circuit 500 is applicable to the IIC (Inter-Integrated Circuit) protocol. The UART protocol is a one-way communication protocol, which is usually used for point-to-point serial communication, and has the advantages of simplicity and low cost; while the IIC protocol is a two-way communication protocol, which is usually used for short-distance communication between multiple devices, supports multi-master and multi-slave devices 200, and has the advantages of high flexibility and saving pin resources. In addition to UART and IIC, the first communication circuit 400 and the second communication circuit 500 can also be applied to other common communication protocols, such as SPI (Serial Peripheral Interface), CAN (Controller Area Network), etc., to meet the needs of different application scenarios.

[0062] In the present embodiment, the master device 100 to which the first communication circuit 400 and the second communication circuit 500 can be connected can be a microcontroller (MCU) or an embedded processor. These master devices 100 are generally responsible for controlling the operation of the entire system, performing data processing and instruction sending. The first communication circuit 400 and the second communication circuit 500 can also be connected to different slave devices 200, such as sensors, displays, memory modules, external control units, etc., respectively. These slave devices 200 interact with the master device 100 through the multiplexed communication terminal 300 to realize the collection, processing and feedback of information.

[0063] In the present embodiment, the multiplexed communication is powered on by default using the UART protocol for communication. If the default UART protocol can successfully communicate with the slave device 200, the system will continue to use the first communication circuit 400 (UART protocol) for data interaction. However, if after trying to communicate with the UART protocol for a period of time, the slave device 200 does not respond, at this time the master device 100 will execute the program for switching the communication protocol, switch the communication protocol to IIC, and communicate through the second communication circuit 500.

[0064] The whole switching process is roughly as follows: after the system is powered on and initialized, the first communication circuit 400 (UART protocol) is enabled by default. The master device 100 sends an initialization command or data packet to the slave device 200 through the UART protocol to try to establish a communication link. Within the set time window, the master device 100 waits for a response from the slave device 200.

[0065] If the slave device 200 responds through the UART protocol within the specified time, the master device 100 confirms that the UART communication link is successfully established, and the master device 100 continues to use the UART protocol for data exchange to complete the communication task.

[0066] If the slave device 200 fails to respond through the UART protocol within the specified time, the master device 100 determines that the UART communication has failed. At this time, the master device 100 will start the communication protocol switching program and prepare to switch to the IIC protocol. During this process, the master device 100 sends a control signal to control the first communication circuit 400 to be closed while switching the communication path to the second communication circuit 500 (IIC protocol). The master device 100 will reinitialize the communication parameters and prepare to communicate with the slave device 200 through the IIC protocol. After the initialization is completed, the master device 100 sends an initialization command or data packet through the IIC protocol to try to establish a new communication link.

[0067] At this time, the master device 100 waits for the slave device 200 to respond through the IIC protocol. If the slave device 200 responds through the IIC protocol, the communication link is successfully established, and the master device 100 uses the IIC protocol for data exchange.

[0068] If the slave device 200 still does not respond, the master device 100 may take further error handling measures, such as retrying communication (re-switching to the UART protocol to try to establish a communication link), issuing an alarm, or entering a fault handling mode.

[0069] During the entire communication process, the master device 100 first attempts to communicate via the default UART protocol; if the UART protocol communication fails, the system automatically switches to the IIC protocol and attempts to establish communication using the second communication circuit 500. Through this time-division multiplexing communication mechanism, the system can switch between multiple communication protocols when the physical channel is limited, ensuring a stable communication link with the slave device 200.

[0070] In some scenarios, time-sharing multiplexing of UART and IIC may be required. For example, in some embedded systems, physical pin resources are limited and it is impossible to configure independent physical channels for each communication protocol. In this case, multiple communication protocols can be implemented on the same pin by time-sharing multiplexing of physical channels, thus saving hardware resources.

[0071] During the time-division multiplexing communication process, the multiplexing communication circuit of this embodiment uses the UART protocol for communication by default upon power-on. At this time, the first communication circuit 400 establishes a communication link with the master device 100 and the slave device 200, and the master device 100 can send or receive data through the UART protocol.

[0072] When data interaction with the slave device 200 is required through the second communication circuit 500 (IIC protocol), the master device 100 executes the communication protocol switching program, and the master device 100 sends a control signal to control the first communication circuit 400 to be closed while switching the communication path to the second communication circuit 500 (IIC protocol). At this time, the master device 100 sequentially establishes a communication link with the slave device 200 through the second communication circuit 500 and the multiplexed communication terminal 300, so that the master device 100 can perform two-way data communication through the IIC protocol. Through the control of the master device 100, time-sharing switching between the first communication circuit 400 and the second communication circuit 500 can be achieved, thereby achieving switching of multiple communication protocols on the same physical channel.

[0073] It should be noted that the time-division multiplexing communication circuit in this embodiment is applicable not only to the above-mentioned situation where physical pin resources are limited, but also to other situations, such as multi-protocol compatible devices, system upgrade or compatibility requirements, development and debugging requirements, etc.

[0074] In the technical solution of this embodiment, a multiplexed communication terminal 300 is used to provide a communication connection for the master device 100 and the slave device 200. By setting a first communication circuit 400, it is matched with the multiplexed communication terminal 300, so that the master device 100 can interact with the slave device 200 through the first communication protocol; secondly, by setting a second communication circuit 500, it is matched with the multiplexed communication terminal 300, so that the master device 100 can interact with the slave device 200 through the second communication protocol. In this way, the master device 100 can control the first communication circuit 400 and the second communication circuit 500 to work alternately in time division, so as to interact with the slave device 200 through two communication protocols in time division through one communication terminal, thereby reducing redundant wiring and connection with the slave device 200, and simplifying the structure of the overall circuit hardware. In addition, through this time-division multiplexing communication mechanism, the system can realize the switching of multiple communication protocols when the physical channel is limited, and ensure the establishment of a stable communication link with the slave device 200.

[0075] See also Figure 1 In this embodiment, the multiplexed communication terminal 300 includes a first data transmitting terminal 302 and a first data receiving terminal 304;

[0076] The first communication circuit 400 has a first communication terminal 401, a second communication terminal 402, a third communication terminal 403, a fourth communication terminal 404 and a first control terminal 406. The first communication terminal 401 and the second communication terminal 402 are respectively electrically connected to the two first communication pins 102 of the main device 100, the first control terminal 406 is communicatively connected to the control pin 106 of the main device 100, the third communication terminal 403 is electrically connected to the first data sending terminal 302, and the fourth communication terminal 404 is communicatively connected to the first data receiving terminal 304;

[0077] The second communication circuit 500 has a fifth communication terminal 502, a sixth communication terminal 504, a seventh communication terminal 506, an eighth communication terminal 508 and a second control terminal 509. The fifth communication terminal 502 and the sixth communication terminal 504 are electrically connected to the two second communication pins 104 of the main device 100 respectively, the seventh communication terminal 506 is electrically connected to the first data sending terminal 302, and the eighth communication terminal 508 is electrically connected to the first data receiving terminal 304.

[0078] In this embodiment, the master device 100 is a microcontroller (MCU) as an example, which has UART and IIC pins to support multiple communication protocols. The two first communication pins mentioned in this embodiment can be UART pins, and the two second communication pins 104 can be IIC pins. In this embodiment, the first communication terminal 401 and the second communication terminal 402 are respectively electrically connected to the two first communication pins of the master device 100 (MCU), and these two pins are usually used for the UART protocol. The third communication terminal 403 and the fourth communication terminal 404 are respectively electrically connected to the first data sending terminal 302 and the first data receiving terminal 304 of the multiplexed communication terminal 300. The first control terminal 406 is connected to the control pin 106 of the master device 100 for receiving the control signal of the master device 100 to enable and disable the UART protocol.

[0079] In the second communication circuit 500, the fifth communication terminal 502 and the sixth communication terminal 504 are electrically connected to two second communication pins 104 of the host device 100 (MCU) respectively, and these two pins are usually used for the IIC protocol.

[0080] The seventh communication terminal 506 and the eighth communication terminal 508 are respectively electrically connected to the first data transmitting terminal 302 and the first data receiving terminal 304 of the multiplexed communication terminal 300. The second control terminal 509 can be connected to the control pin 106 of the host device 100 or can be electrically connected to the first control terminal 406.

[0081] After the system is powered on and initialized, the first communication circuit 400 is enabled by default and the UART protocol is used for communication.

[0082] The master device 100 sends signals through the first communication terminal 401 and receives signals through the second communication terminal 402. At this time, the third communication terminal 403 and the fourth communication terminal 404 are electrically connected to the first data sending terminal 302 and the first data receiving terminal 304 of the multiplexed communication terminal 300, respectively, to achieve data sending and receiving.

[0083] When switching to the IIC protocol, the master device 100 sends a control signal to turn off the first communication circuit 400 and enable the second communication circuit 500. The fifth communication terminal 502 serves as the clock line (SCL) of the IIC protocol, and the sixth communication terminal 504 serves as the data line (SDA), which are electrically connected to the first data transmitting terminal 302 and the first data receiving terminal 304 of the multiplexed communication terminal 300, respectively.

[0084] In this protocol communication process, the SC signal controls the data transmission rate. The master device 100 can control the data transmission speed on the IIC bus by adjusting the frequency of the SCL signal. The SDA line is a bidirectional data line in the IIC protocol, which can be used for both data transmission (master device 100 to slave device 200) and data reception (slave device 200 to master device 100). When the IIC bus transmits data, both the master device 100 and the slave device 200 can drive the SDA line. During the data transmission process, the SDA line transmits data bits under the control of the SCL signal.

[0085] Continue reading Figure 1 In this embodiment, the third communication terminal 403 is electrically connected to the seventh communication terminal 506, and the fourth communication terminal 404 is electrically connected to the eighth communication terminal 508;

[0086] The first communication terminal 401 , the second communication terminal 402 , the third communication terminal 403 , and the fourth communication terminal 404 are all UART communication terminals, and the fifth communication terminal 502 , the sixth communication terminal 504 , the seventh communication terminal 506 , and the eighth communication terminal 508 are all IIC communication terminals.

[0087] In this embodiment, by electrically connecting the third communication terminal 403 to the seventh communication terminal 506, and the fourth communication terminal 404 to the eighth communication terminal 508, the multiplexed communication terminal 300 is effectively utilized, significantly reducing the need for additional wiring. Specifically, after the third communication terminal 403 is connected to the seventh communication terminal 506, only one additional line is needed to connect to the first data sending terminal 302; similarly, after the fourth communication terminal 404 is connected to the eighth communication terminal 508, only one additional line is needed to connect to the first data receiving terminal 304. In this way, by connecting the third communication terminal 403 to the seventh communication terminal 506, and the fourth communication terminal 404 to the eighth communication terminal 508, only one line needs to be added to each communication path, which greatly simplifies the wiring design of the circuit board and reduces the wiring complexity on the PCB. In addition, this simplified wiring design can reduce potential interference and signal crosstalk in the circuit, thereby improving the reliability and stability of communication.

[0088] See also Figure 2 , Figure 2 It is a circuit diagram of a multiplexed communication circuit in one embodiment of the utility model.

[0089] In this embodiment, the first communication circuit 400 includes a signal direction control module 410, and the signal direction control module 410 includes:

[0090] A first conducting end 411, the first conducting end 411 is electrically connected to the first communication end 401;

[0091] The second conducting end 412 is electrically connected to the second communication end 402;

[0092] The third conducting terminal 413 is electrically connected to the third communication terminal 403;

[0093] A fourth conducting terminal 414, the fourth conducting terminal 414 is electrically connected to the fourth communication terminal 404;

[0094] An enable terminal 416, the enable terminal 416 is electrically connected to the first control terminal 406;

[0095] The second communication circuit 500 includes a data isolation module 510, a clock isolation module 520 and an on-off control terminal G1, the input terminal of the clock isolation module 520 is electrically connected to the fifth communication terminal 502, and the output terminal of the clock isolation module 520 is electrically connected to the seventh communication terminal 506;

[0096] The input end of the data isolation module 510 is electrically connected to the sixth communication end 504, and the output end of the data isolation module 510 is electrically connected to the eighth communication end 508;

[0097] The on-off control terminal G1 is communicatively connected to the first control terminal 406 .

[0098] In this embodiment, the first communication circuit 400 includes a signal direction control module 410, which can control the transmission direction of the signal of the third conductive end 413 and the fourth conductive end 414. In this embodiment, the first communication end 401 (TX) is connected to the third communication end 403 for sending signals, and the second communication end 402 (RX) is connected to the fourth communication end 404 for receiving signals.

[0099] When the single-chip microcomputer (MCU) uses the UART protocol to communicate, the single-chip microcomputer (MCU) uses the UART protocol to communicate with the slave device 200. Data enters from the first communication terminal 401, and then is transmitted to the first data transmitting terminal 302 of the multiplexed communication terminal 300 through the third conductive terminal 413. At the same time, the data sent from the slave device 200 enters the fourth conductive terminal 414 through the first data receiving terminal 304 of the multiplexed communication terminal 300, and then passes through the second communication terminal 402, and is transmitted back to the single-chip microcomputer (MCU) to complete the signal reception.

[0100] When the single chip microcomputer (MCU) uses the IIC protocol to communicate, the single chip microcomputer (MCU) sends a control signal to the first control terminal 406, so that the first communication terminal 401 and the third conduction terminal 413 of the signal direction control module 410 are turned off, and the second communication terminal 402 and the fourth conduction terminal 414 are turned off. In this state, the signal direction control module 410 of the first communication circuit 400 is turned off, isolating the first communication terminal 401 and the third communication terminal 403, and the second communication terminal 402 and the fourth communication terminal 404.

[0101] At the same time, the single-chip microcomputer (MCU) also sends a control signal to the second control terminal 509, and the second communication circuit 500 is enabled. The input end of the clock isolation module 520 is electrically connected to the fifth communication terminal 502, the input end of the data isolation module 510 is electrically connected to the sixth communication terminal 504, the output end of the clock isolation module 520 is electrically connected to the seventh communication terminal 506, and the output end of the data isolation module 510 is electrically connected to the eighth communication terminal 508. At this time, the clock signal is transmitted from the fifth communication terminal 502 to the IIC bus through the clock isolation module 520. The data is transmitted to the eighth communication terminal 508 (the first data receiving terminal 304) through the sixth communication terminal 504 and the data isolation module 510, so as to provide the single-chip microcomputer (MCU) with the slave device 200 for two-way communication. In this way, by isolating the unused communication path, the reliability and anti-interference ability of the system can be improved, and the stability of data transmission can be ensured.

[0102] See also Figure 3 , Figure 3 It is a circuit diagram of a multiplexed communication circuit in one embodiment of the utility model.

[0103] Furthermore, the signal direction control module 410 further includes a first direction control terminal 417 and a second direction control terminal 418;

[0104] The first communication circuit 400 further includes:

[0105] A pull-down resistor R1, one end of which is connected to the cathode, and the other end of which is electrically connected to the first direction control terminal 417;

[0106] The pull-up resistor R2 has one end connected to the positive electrode, and the other end electrically connected to the second direction control terminal 418 .

[0107] In this embodiment, the first direction control terminal 417 is set to be effective at a high level, that is, when the first direction control terminal 417 is at a high level, the first conducting terminal 411 and the third conducting terminal 413 are conducting.

[0108] The second direction control terminal 418 is set to be effective at a low level, that is, when the second direction control terminal 418 is at a low level, the second conducting terminal 412 and the fourth conducting terminal 414 are conducting.

[0109] In the default state, the pull-up resistor R2 clamps the level signal of the first direction control terminal 417 at a high level, and the pull-down resistor R1 clamps the level signal of the second direction control terminal 418 at a low level. At this time, the first conductive terminal 411 and the third conductive terminal 413 are turned on, and the microcontroller communicates with the slave device 200 in the default state UART communication protocol.

[0110] When the first control terminal 406 inputs a high level, the enable terminal 416 of the signal direction control module 410 is triggered, and the state of the signal direction control module 410 changes. At this time, the level signal of the first direction control terminal 417 becomes a low level, and the level signal of the second direction control terminal 418 becomes a high level. As a result, the first conductive terminal 411 and the third conductive terminal 413 are disconnected, and the second conductive terminal 412 and the fourth conductive terminal 414 are also disconnected, and the second communication circuit 500 is switched to work.

[0111] At this time, the second control terminal 509 of the second communication circuit 500 is high level valid, the data isolation module 510 and the clock isolation module 520 start working under the control of the on-off control terminal G1, and the single chip microcomputer switches to the IIC communication protocol to communicate with the slave device 200.

[0112] Continue reading Figure 3 In order to further reduce signal interference and crosstalk, the signal direction control module 410 can use a three-state buffer chip. Specifically, the signal direction control module 410 is a three-state buffer chip of the SN74AXC2T245 model.

[0113] In this embodiment, in order to further reduce signal interference and crosstalk, the signal direction control module 410 of this embodiment adopts a three-state buffer chip of the SN74AXC2T245 model. The three-state buffer chip can switch between high level, low level and high impedance state (disconnected). The high impedance state can effectively isolate the signal line and reduce interference and crosstalk. The enable terminal 416 of the three-state buffer chip is connected to the first control terminal 406 and the second control terminal 509, which is used to control the conduction and disconnection of the signal.

[0114] When the system is powered on and uses UART communication by default, the first control terminal 406 is at a low level, so that the first direction control terminal 417 is at a low level and the second direction control terminal 418 is at a high level. In this state, the tri-state buffer chip connects the first communication terminal 401 with the third communication terminal 403 (the second communication terminal 402 is connected with the fourth communication terminal 404). In this way, the sending and receiving signals of the UART communication protocol can be transmitted without interference.

[0115] When the first control terminal 406 inputs a high level and the enable terminal 416 is triggered, the tri-state buffer chip enters a high impedance state, disconnecting the first communication terminal 401, the third communication terminal 403, the second communication terminal 402, and the fourth communication terminal 404. At this time, the on-off control terminal G1 of the second communication circuit 500 is activated, the data isolation module 510 and the clock isolation module 520 start to work, and the clock line (SCL) and the data line (SDA) of the IIC communication are used for data transmission through the seventh communication terminal 506 and the eighth communication terminal 508. In this way, the IIC communication can be carried out without the interference of the UART signal.

[0116] In this embodiment, the tri-state buffer chip can effectively isolate the signal line in the high impedance state, preventing the unused communication circuit from interfering with and crosstalking the communication circuit in use. When switching between UART and IIC communications, the tri-state buffer chip can ensure that the unused signal line is in a high impedance state, thereby improving the stability and reliability of signal transmission. In addition, by using a tri-state buffer chip, additional isolation circuits can be reduced, achieving a more compact and efficient design.

[0117] Continue reading Figure 3 , further, the data isolation module 510 includes:

[0118] A first switch tube Q1, wherein a source of the switch tube is electrically connected to an input end of the data isolation module 510, and a gate of the first switch tube Q1 is electrically connected to a control pin 106 of the master device 100;

[0119] A second switch tube Q2, wherein a drain of the second switch tube Q2 is electrically connected to a drain of the first switch tube Q1, a source of the second switch tube Q2 is electrically connected to an output end of the data isolation module 510, and a gate of the second switch tube Q2 is electrically connected to a control pin 106 of the master device 100;

[0120] The clock isolation module 520 includes:

[0121] A third switch tube Q3, wherein a source of the third switch tube Q3 is electrically connected to an input end of the clock isolation module 520, and a gate of the third switch tube Q3 is communicatively connected to a control pin 106 of the master device 100;

[0122] A fourth switch tube Q4, wherein the drain of the fourth switch tube Q4 is electrically connected to the drain of the third switch tube Q3, the source of the fourth switch tube Q4 is electrically connected to the output end of the clock isolation module 520, and the gate of the fourth switch tube Q4 is electrically connected to the control pin 106 of the master device 100.

[0123] In this embodiment, the first switch tube Q1 and the second switch tube Q2 are used as the on-off control of the clock isolation module 520, and the third switch tube Q3 and the fourth switch tube Q4 are used as the on-off control of the data isolation module 510, wherein the first switch tube Q1, the second switch tube Q2, the third switch tube Q3, and the fourth switch tube Q4 can all be N-channel MOS tubes.

[0124] The four N-channel MOS transistors are turned off at a low level and turned on when the second control terminal 509 is a high level signal; that is, when the second control terminal 509 is a high level, the four switch tubes are turned on, and the data and clock signals can be transmitted through the isolation module. When the second control terminal 509 is a low level, the four switch tubes are turned off, and the data and clock signals are isolated to avoid interference and crosstalk.

[0125] In this embodiment, the first switch tube Q1 and the second switch tube Q2 of the clock isolation module 520 adopt a similar cascade structure to ensure that the clock signal is completely isolated in a low level state.

[0126] When the second control terminal 509 is at a high level, the first switch tube Q1 and the second switch tube Q2 are turned on, and the clock signal enters the third switch tube Q3 from the input terminal through the source, and then enters the fourth switch tube Q4 through the drain, and finally outputs from the source to the output terminal of the clock isolation module 520. This process ensures the stable transmission of the clock signal.

[0127] The drain of the third switch tube Q3 is connected to the drain of the fourth switch tube Q4, also forming a cascade structure. This design can enhance the signal isolation effect and ensure that the signal is completely disconnected in the low-level state. When the second control terminal 509 is at a high level, the third switch tube Q3 and the fourth switch tube Q4 are turned on at the same time, and the data enters the third switch tube Q3 from the input end through the source, and then enters the fourth switch tube Q4 through the drain, and finally outputs from the source to the output end of the data isolation module 510.

[0128] In some embodiments, in addition to using the above-mentioned switch tube (MOS tube) to realize the on-off control of the clock isolation module 520 and the data isolation module 510, an IIC BUFFER with enable can also be used. Common IIC BUFFER models include PCA9515, PCA9617A, TCA4311A, etc. These BUFFER devices are specially designed for the IIC bus and provide enhanced signal driving capability and isolation function.

[0129] Exemplarily, the clock isolation module 520 and the data isolation module 510 can be implemented using IIC BUFFERs such as PCA9515, PCA9617A or TCA4311A, respectively.

[0130] The clock isolation module 520 uses one channel of the IIC BUFFER to connect to the fifth communication terminal 502 (SCL), and another channel is connected to the output terminal of the clock isolation module 520. The data isolation module 510 uses one channel of the IIC BUFFER to connect to the sixth communication terminal 504 (SDA), and another channel is connected to the output terminal of the data isolation module 510.

[0131] After the system is powered on, the first communication circuit 400 is enabled by default. The pull-up resistor R2 and the pull-down resistor R1 control the signal direction to ensure the sending and receiving of UART communication. When switching to IIC communication, the first control terminal 406 inputs a low level, the enable terminal 416 is triggered, and the tri-state buffer chip enters a high impedance state to isolate the UART communication path. At the same time, the IIC BUFFER is enabled to connect it to the second control terminal 509, and the clock isolation module 520 and the data isolation module 510 are activated. The clock signal is transmitted from the fifth communication terminal 502 to the IIC bus through the IIC BUFFER. Data is sent through the sixth communication terminal 504 and transmitted to the eighth communication terminal 508 (the first data sending terminal 302) through the IIC BUFFER to complete the IIC communication.

[0132] Continue reading Figure 3 , the data isolation module 510 further includes:

[0133] Two first resistors R3, one end of the two first resistors R3 are connected to the positive electrode of the power supply, and the other end of the two first resistors R3 are connected to the gate of the first switch tube Q1 and the gate of the second switch tube Q2 respectively;

[0134] The clock isolation module 520 includes:

[0135] Two second resistors R5, one end of the two second resistors R5 are connected to the positive electrode of the power supply, and the other end of the two second resistors R5 are respectively connected to the gate of the third switch tube Q3 and the gate of the fourth switch tube Q4.

[0136] In this embodiment, the gate resistor connected in series with the gate of the MOS tube can limit the gate current, avoid the oscillation phenomenon caused by excessive gate current, and improve the stability of the switching operation. At the same time, the gate resistor can effectively suppress the peak voltage caused by power supply noise or switching process, and prevent the MOS tube from being damaged due to excessive transient voltage. The existence of the resistor can slow down the rise and fall speed of the gate voltage, thereby reducing the electromagnetic interference (EMI) caused by the switching operation in the circuit.

[0137] Continue reading Figure 3 In this embodiment, the data isolation module 510 further includes:

[0138] Two third resistors R4, one end of the two third resistors R4 are connected to the positive electrode of the power supply, and the other end of the two third resistors R4 are connected to the source of the first switch tube Q1 and the source of the second switch tube Q2 respectively;

[0139] The clock isolation module 520 includes:

[0140] Two fourth resistors R6, one ends of the two fourth resistors R6 are connected to the positive electrode of the power supply, and the other ends of the two fourth resistors R6 are respectively connected to the source of the third switch tube Q3 and the source of the fourth switch tube Q4.

[0141] In this embodiment, the SCL line and the SDA line are connected to the positive pole of the power supply through the pull-up resistor R2, which is generally required, to ensure that the bus is in a known high level state when not driven, and the two third resistors R4 and the two third fourth resistors in this embodiment are used to pull the SDA line and the SCL line to a high level when not driven. At the same time, the combination with the MOS tube can effectively suppress the peak voltage and electromagnetic interference, and improve the anti-interference ability of the system. This design can ensure that the system can still work stably and reliably in a complex electromagnetic environment.

[0142] The utility model further proposes an electronic device, including a master device 100 and a slave device 200, and a multiplexed communication circuit of the aforementioned embodiment. The specific structure of the multiplexed communication circuit refers to the aforementioned embodiment. Since the electronic device adopts all the technical solutions of all the aforementioned embodiments, it at least has all the technical effects brought by the technical solutions of the aforementioned embodiments, which will not be described one by one here. The multiplexed communication circuit is arranged between the master device 100 and the slave device 200.

[0143] In this embodiment, the master device 100 can be a common microcontroller, such as STM32, PIC, Arduino, ESP32, etc., which is a core processor for controlling various electronic devices; and the slave device 200 can be a sensor, a storage device, etc., and the electronic device mentioned in the embodiment can be a computer, a mobile phone, a PLC, etc. that uses the master device 100 and the slave device 200, without any special limitation here.

[0144] For example, by multiplexing the communication circuit, the controller (master device 100) in the smart home system can communicate efficiently with various sensors, display modules and actuators (slave devices 200) to achieve functions such as temperature control, security monitoring, and lighting control.

[0145] The above description is only a partial or preferred embodiment of the present invention. Neither the text nor the drawings can limit the scope of protection of the present invention. All equivalent structural changes made by using the contents of the present invention specification and drawings under the overall concept of the present invention, or direct / indirect application in other related technical fields are included in the scope of protection of the present invention.

Claims

1. A multiplexing communication circuit, characterized in that: include: Multiplexed communication terminals are used to provide communication connections between master and slave devices; a first communication circuit, wherein the first communication circuit is communicatively connected to the master device and the multiplexed communication terminal respectively, and the first communication circuit is used to cooperate with the multiplexed communication terminal to allow the master device to perform data exchange with the slave device using a first communication protocol; a second communication circuit, the second communication circuit being communicatively connected to the master device and the multiplexed communication terminal respectively, and the second communication circuit being used to cooperate with the multiplexed communication terminal so that the master device can perform data exchange with the slave device using a second communication protocol; The first communication circuit and the second communication circuit are used to perform time-sharing switching under the control of the master device.

2. The multiplexing communication circuit according to claim 1, characterized in that: The multiplexed communication terminal includes a first data transmitting terminal and a first data receiving terminal; The first communication circuit comprises a first communication terminal, a second communication terminal, a third communication terminal, a fourth communication terminal and a first control terminal, wherein the first communication terminal and the second communication terminal are electrically connected to two first communication pins of the master device respectively, the first control terminal is electrically connected to a control pin of the master device, the third communication terminal is electrically connected to the first data sending terminal, and the fourth communication terminal is electrically connected to the first data receiving terminal; The second communication circuit has a fifth communication terminal, a sixth communication terminal, a seventh communication terminal, an eighth communication terminal and a second control terminal. The fifth communication terminal and the sixth communication terminal are electrically connected to the two second communication pins of the main device respectively, the seventh communication terminal is electrically connected to the first data sending terminal, and the eighth communication terminal is electrically connected to the first data receiving terminal.

3. The multiplexing communication circuit according to claim 2, characterized in that: The third communication terminal is electrically connected to the seventh communication terminal, and the fourth communication terminal is electrically connected to the eighth communication terminal; The first communication terminal, the second communication terminal, the third communication terminal, and the fourth communication terminal are all UART communication terminals, and the fifth communication terminal, the sixth communication terminal, the seventh communication terminal, and the eighth communication terminal are all IIC communication terminals.

4. The multiplexing communication circuit according to claim 2, characterized in that: The first communication circuit includes a signal direction control module, and the signal direction control module includes: A first conducting end, the first conducting end being electrically connected to the first communication end; a second conducting end, the second conducting end being electrically connected to the second communication end; A third conducting end, the third conducting end being electrically connected to the third communication end; a fourth conducting end, the fourth conducting end being electrically connected to the fourth communication end; an enabling terminal, the enabling terminal being electrically connected to the first control terminal; The second communication circuit includes a data isolation module, a clock isolation module and an on-off control terminal, the input terminal of the clock isolation module is electrically connected to the fifth communication terminal, and the output terminal of the clock isolation module is electrically connected to the seventh communication terminal; The input end of the data isolation module is electrically connected to the sixth communication end, and the output end of the data isolation module is electrically connected to the eighth communication end; The on-off control terminal is communicatively connected with the first control terminal.

5. The multiplexing communication circuit according to claim 4, characterized in that: The signal direction control module also includes a first direction control terminal and a second direction control terminal; The first communication circuit further includes: A pull-down resistor, one end of which is connected to the cathode, and the other end of which is electrically connected to the first direction control end; A pull-up resistor has one end connected to the positive electrode and the other end electrically connected to the second direction control end.

6. The multiplexing communication circuit according to claim 5, characterized in that: The signal direction control module is a three-state buffer chip of the SN74AXC2T245 model.

7. The multiplexing communication circuit according to claim 4, characterized in that: The data isolation module comprises: a first switch tube, wherein a source of the first switch tube is electrically connected to an input end of the data isolation module, and a gate of the first switch tube is electrically connected to a control pin of the master device; a second switch tube, wherein a drain of the second switch tube is electrically connected to a drain of the first switch tube, a source of the second switch tube is electrically connected to an output end of the data isolation module, and a gate of the second switch tube is electrically connected to a control pin of the master device; The clock isolation module comprises: a third switch tube, wherein a source of the third switch tube is electrically connected to an input end of the clock isolation module, and a gate of the third switch tube is communicatively connected to a control pin of the master device; A fourth switch tube, wherein the drain of the fourth switch tube is electrically connected to the drain of the third switch tube, the source of the fourth switch tube is electrically connected to the output end of the clock isolation module, and the gate of the fourth switch tube is electrically connected to the control pin of the master device.

8. The multiplexing communication circuit according to claim 7, characterized in that: The data isolation module also includes: Two first resistors, one end of each of the two first resistors is connected to the positive electrode of the power supply, and the other end of each of the two first resistors is connected to the gate of the first switch tube and the gate of the second switch tube respectively; The clock isolation module comprises: Two second resistors, one end of the two second resistors are connected to the positive electrode of the power supply, and the other ends of the two second resistors are respectively connected to the gate of the third switch tube and the gate of the fourth switch tube.

9. The multiplexing communication circuit according to claim 7, characterized in that: The data isolation module also includes: Two third resistors, one end of each of the two third resistors is connected to the positive electrode of the power supply, and the other end of each of the two third resistors is connected to the source electrode of the first switch tube and the source electrode of the second switch tube respectively; The clock isolation module comprises: Two fourth resistors, one end of each of the two fourth resistors is connected to the positive electrode of the power supply, and the other end of each of the two fourth resistors is connected to the source of the third switch tube and the source of the fourth switch tube respectively.

10. An electronic device, characterized in that: The invention comprises a master device and a slave device, and the multiplexing communication circuit according to any one of claims 1 to 9, wherein the multiplexing communication circuit is arranged between the master device and the slave device.

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