Semiconductor structure

Abstract

A semiconductor structure includes a first transistor, a second transistor, a first metal silicide layer, a first fluoride-free tungsten layer, and a first tungsten contact. The first transistor comprises a plurality of first semiconductor chips; a first gate structure surrounding each of the first semiconductor sheets; and a plurality of first source / drain structures on either side of each of the first semiconductor sheets. The second transistor is over the first transistor. The second transistor comprises a plurality of second semiconductor chips; a second gate structure surrounding each of the second semiconductor sheets; and a plurality of second source / drain structures on either side of each of the second semiconductor sheets. A first metal silicide layer is on one of the first source / drain structures. The first fluoride-free tungsten layer is located on the first metal silicide layer. The first tungsten contact is on the first fluoride-free tungsten layer.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor structure. Background Art

[0002] As the semiconductor industry moves further toward sub-10 nanometer (nm) technology process nodes in search of higher device density, higher performance, and lower cost, challenges from manufacturing and design issues have resulted in stacked device structure configurations, such as complementary field effect transistors (C-FETs), in which an n-type multi-gate transistor and a p-type multi-gate transistor are vertically stacked, one above the other. While existing C-FET structures are generally adequate, they are not satisfactory in all aspects. Utility Model Content

[0003] In some embodiments, a semiconductor structure includes a first transistor, a second transistor, a first metal silicide layer, a first fluorine-free tungsten layer, and a first tungsten contact. The first transistor includes a plurality of first semiconductor slices; a first gate structure surrounding each of the first semiconductor slices; and a plurality of first source / drain structures located on either side of each of the first semiconductor slices. The second transistor is located above the first transistor. The second transistor includes a plurality of second semiconductor slices; a second gate structure surrounding each of the second semiconductor slices; and a plurality of second source / drain structures located on either side of each of the second semiconductor slices. The first metal silicide layer is located on one of the first source / drain structures. The first fluorine-free tungsten layer is located on the first metal silicide layer. The first tungsten contact is located on the first fluorine-free tungsten layer.

[0004] In some embodiments, a semiconductor structure includes a bottom transistor, a top transistor, a first metal silicide, a first metal capping structure, and a front side contact. The top transistor is located above the bottom transistor, and the top transistor includes a first channel layer, a first gate structure located around the first channel layer, and a plurality of first source / drain regions located on a plurality of opposite sides of the first channel layer. The first metal silicide is located on one of the plurality of first source / drain regions. The first metal capping structure is located on the first metal silicide. The front side contact is located on the first metal capping structure.

[0005] In some embodiments, a semiconductor structure includes a first semiconductive nanostructure, a second semiconductive nanostructure, a plurality of first epitaxial structures, a plurality of second epitaxial structures, a first gate, a second gate, a first metal silicide layer, a second metal silicide layer, a first fluorine-free metal layer, and a second fluorine-free metal layer. The second semiconductive nanostructure is arranged in a vertical direction with the first semiconductive nanostructure. The plurality of first epitaxial structures are located on a plurality of opposite sides of the first semiconductive nanostructure. The plurality of second epitaxial structures are located on a plurality of opposite sides of the second semiconductive nanostructure. The first gate surrounds the first semiconductive nanostructure. The second gate surrounds the second semiconductive nanostructure. The first metal silicide layer is located on one of the plurality of first epitaxial structures. The second metal silicide layer is located on one of the plurality of second epitaxial structures. The first fluorine-free metal layer is located on the first metal silicide layer. The second fluorine-free metal layer is located on the second metal silicide layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure can be best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figures 1A to 17F Schematic diagrams illustrating intermediate stages of a semiconductor structure according to some embodiments of the present disclosure.

[0008]

Explanation of symbols

[0009] 100a: Semiconductor structure

[0010] 110:Substrate

[0011] 110b, 194b: dorsal

[0012] 112: Protruding part

[0013] 122a, 122b, 122m, 124a, 124b: epitaxial layer

[0014] 125: Fin-shaped structure

[0015] 140, 190: Isolation structure

[0016] 150: dummy gate structure

[0017] 152: dummy gate dielectric layer

[0018] 154: dummy gate electrode layer

[0019] 156: Oxide layer

[0020] 158: Nitride layer

[0021] 160, 233: Gate spacer

[0022] 162: Fin spacer

[0023] 172, 174: Internal dielectric spacer

[0024] 180: first source / drain epitaxial structure

[0025] 181': Small face

[0026] 182a, 186: metal silicide layer

[0027] 182b: Metal layer

[0028] 183a, 183b, 187: Metal covering structure

[0029] 184, 188: Pad

[0030] 185: Second source / drain epitaxial structure

[0031] 192, 196:CESL

[0032] 194, 198: ILD layer

[0033] 198f:Front side

[0034] S / D: Source / Drain region

[0035] 220, 230: Gate structure

[0036] 222: Interface layer

[0037] 224: High-k gate dielectric layer

[0038] 226, 236: gate electrode layer

[0039] 238: Hard Mask Layer

[0040] 242, 244: Source / drain contacts

[0041] 242b: Dorsal surface

[0042] 242p: Dorsal part

[0043] 242s, 244s: Sidewall

[0044] 244p: front part

[0045] 251:STI structure

[0046] B-B': Reference cross section

[0047] O1, O2: Source / drain contact openings

[0048] O21, O22: Auxiliary contact openings

[0049] P1, P2, P5, P6: Deposition process

[0050] P3, P4: Etching process

[0051] R1: Groove

[0052] R2: Horizontal groove

[0053] S1, S2: Space

[0054] T1, T2: thickness

[0055] Tb: Bottom transistor

[0056] Tt: Top transistor DETAILED DESCRIPTION

[0057] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. The specific examples of the components and configurations described below are for simplifying the disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are directly contacted, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be directly contacted. In addition, the disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0058] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0059] As used herein, "approximately," "about," "approximately," or "substantially" may refer to within 20%, or within 10%, or within 5% of a given value or range. However, those skilled in the art will recognize that the values ​​or ranges listed throughout the specification are merely examples and may decrease as integrated circuits shrink. The numerical quantities given herein are approximate, meaning that the terms "approximately," "about," "approximately," or "substantially" may be inferred in the absence of explicit provisions.

[0060] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those generally understood by those skilled in the art to which the present disclosure belongs. It should be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and should not be interpreted in an idealized or overly formal sense unless so explicitly defined herein.

[0061] The gate all around (GAA) transistor structure may be patterned by any suitable method. For example, the structure may be patterned using one or more lithography processes, including double patterning or multi-patterning processes. Typically, the double patterning or multi-patterning process combines lithography and self-alignment processes, thereby allowing the formation of patterns having, for example, a smaller pitch than can be obtained using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and a lithography process is used to pattern the sacrificial layer. A self-alignment process is used to form spacers next to the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the GAA structure.

[0062] The present disclosure relates to integrated circuit (IC) structures and methods for forming the same. More specifically, some embodiments of the present disclosure relate to gate-all-around (GAA) devices including improved isolation structures to reduce current leakage from a channel to a substrate. A GAA device includes a device having a gate structure or a portion thereof formed on four sides of a channel region (e.g., surrounding a portion of a channel region). The channel region of a GAA device may include a nanosheet channel, a strip channel, and / or other suitable channel configurations. In some embodiments, the channel region of a GAA device may have a plurality of horizontal nanosheets or horizontal strips spaced vertically apart, thereby making the GAA device a stacked horizontal GAA (S-HGAA) device. The GAA devices presented herein include a p-type metal oxide semiconductor GAA device and an n-type metal oxide semiconductor GAA device stacked together. In addition, a GAA device may have one or more channel regions (e.g., nanosheets) associated with a single continuous gate structure or a plurality of gate structures. A person generally familiar with the art may recognize other examples of semiconductor devices that may benefit from the various aspects of the present disclosure. In some embodiments, nanosheets may be interchangeably referred to as nanowires, nanoplates, nanorings, or nanostructures having nanoscale dimensions (e.g., a few nanometers), depending on their geometry. In addition, however, the embodiments of the present disclosure may also be applied to various metal oxide semiconductor transistors (e.g., complementary-field effect transistors (CFETs) and fin field effect transistors (FinFETs)).

[0063] Some embodiments discussed herein are discussed in the context of nano-FETs formed using a gate-last process. In other embodiments, a gate-first process may be used. In addition, some embodiments contemplate aspects used in planar devices such as planar FETs or in fin field-effect transistors (FinFETs).

[0064] For example, a FinFET may include a fin on a substrate, wherein the fin serves as a channel region of the FinFET. Similarly, a planar FET may include a substrate, wherein a portion of the substrate serves as a channel region of the planar FET.

[0065] In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be produced using a manufacturing process) has decreased. In order to increase the functional density of IC structures, complementary FETs (CFETs) in which p-type FETs and n-type FETs are vertically stacked have been proposed. Metal silicides may be formed on source / drain regions through dielectric-defined source / drain openings to increase the silicide diffusion contact resistance (Rcsd) of the IC structure. However, due to the small landing area of ​​the source / drain regions in the dielectric-defined source / drain openings, metal silicides and subsequent source / drain contact materials are difficult to form on the source / drain regions through the dielectric-defined source / drain openings, which in turn degrades the silicide diffusion contact resistance of the IC structure, and thus the performance of the IC structure may be reduced.

[0066] Therefore, in various embodiments, the present disclosure provides methods for selectively forming metal silicide and metal cap structures on source / drain regions of transistors rather than on surrounding dielectrics by deposition processes such as CVD or ALD processes. Thus, the deposited material of the metal silicide and the deposited material of the metal cap structure can be easily formed on the source / drain regions through the source / drain openings in a limited deposition area. In addition, because the metal silicide and the metal cap structure can only be formed on the source / drain regions and not on the surrounding dielectrics, the metal silicide and the metal cap structure occupy less space in the source / drain openings, which in turn facilitates the subsequent metal filling in the source / drain openings and thus can improve the silicide diffusion contact resistance of the IC structure. In some embodiments, the metal cap structure may also be interchangeably referred to as a metal cap layer or a metal cap.

[0067] refer to Figures 1A to 16B . Figure 1A , Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig. 9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.15A , Fig.16A and Fig.17A A cross-sectional view illustrating an intermediate stage in the formation of a semiconductor structure 100 a in accordance with some embodiments. Figure 1B , Figure 2B , Figure 3B , Figure 4B, Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B and Fig. 17B Describe respectively Figure 1A , Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig. 9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.15A , Fig.16A and Fig.17A Cross-sectional view obtained from the reference cross-section BB' in FIG.

[0068] refer to Figure 1A and Figure 1B . An epitaxial stack is formed over substrate 110. In some embodiments, substrate 110 may include silicon (Si). Alternatively, substrate 110 may include germanium (Ge), silicon germanium (SiGe), a III-V material (e.g., GaAs, GaP, GaAsP, AlInAs, AlGaAs, GaInAs, InAs, GaInP, InP, InSb and / or GaInAsP or a combination thereof), or other suitable semiconductor materials. In some embodiments, substrate 110 may include a semiconductor-on-insulator (SOI) structure, such as a buried dielectric layer. Further, alternatively, substrate 110 may include a buried dielectric layer, such as a buried oxide (BOX) layer, such as a buried oxide layer formed by a method known as separation by implantation of oxygen (SIMOX) technology, wafer bonding, SEG, or another suitable method.

[0069] The epitaxial stack includes epitaxial layers 122a, 122b, 122m of a first component inserted by epitaxial layers 124a, 124b of a second component. The first component and the second component may be different. In some embodiments, the epitaxial layers 122a, 122b, 122m may be made of SiGe, and the epitaxial layers 124a, 124b may be made of silicon (Si). However, other embodiments are possible, including those that provide first and second components with different etching selectivities.

[0070] The epitaxial layers 124a and 124b or portions thereof may form a nanostructure channel of a nanostructure transistor. The term nanostructure is used herein to designate any material portion having nanoscale or even microscale dimensions and having an elongated shape, regardless of the cross-sectional shape of the portion. Thus, the term designates elongated material portions of circular and substantially circular cross-sections and beam-shaped or strip-shaped material portions that include, for example, cylindrical shapes or substantially rectangular cross-sections. For example, the nanostructures are nanosheets, nanowires, nanoplates, or nanorings, depending on their geometry. The use of epitaxial layers 124a and 124b to define one or more channels of a device is discussed further below. In Figure 1A and Figure 1B In FIG. 1 , the epitaxial layer 124b is disposed above the epitaxial layer 124a. It should be noted that Figure 1A and Figure 1B The three epitaxial layers 124a and the three epitaxial layers 124b are generally configured for illustrative purposes only and are not intended to be limited beyond the specific description of the scope of the patent application. It can be understood that any number of epitaxial layers can be formed in the epitaxial stack; the number of layers depends on the desired number of channel regions of the transistor. In some embodiments, the number of each of the epitaxial layers 124a and 124b can be between 2 and 10.

[0071] Epitaxial layer 122a is inserted by epitaxial layer 124a, epitaxial layer 122b is inserted by epitaxial layer 124b, and epitaxial layer 122m is located between epitaxial layers 124a and 124b. In some embodiments, epitaxial layers 122a and 122b have substantially the same thickness T1, and epitaxial layer 122m has a thickness T2 that is less than thickness T1. In some embodiments, thickness T2 is formed by isolation structure 190 (see Figure 4A and Figure 4B ) is determined by the thickness and is in the range of about 20 nm to about 1000 nm.

[0072] As described in more detail below, epitaxial layers 124a and 124b can be used as channel regions for subsequently formed semiconductor devices, and the thickness is selected based on device performance considerations. Epitaxial layers 122a, 122b, and 122m in the channel region can eventually be removed and can be used to define the vertical distance between adjacent channel regions for subsequently formed multi-gate devices, and the thickness is selected based on device performance considerations. Therefore, epitaxial layers 122a, 122b, and 122m can also be referred to as sacrificial layers, and epitaxial layers 124a and 124b can also be referred to as channel layers. In some embodiments, epitaxial layers 124a and 124b can be interchangeably referred to as channel regions or channel patterns.

[0073] As an example, the epitaxial growth of the layers of the epitaxial stack can be performed by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes. In some embodiments, the epitaxial growth layers, such as epitaxial layers 124a and 124b, include the same material as the substrate 110. In some embodiments, the epitaxial layers 122a, 122b, 122m and 124a, 124b include a different material than the substrate 110. As described above, in at least some examples, the epitaxial layers 122a, 122b, and 122m include epitaxially grown silicon germanium (SiGe) layers, and the epitaxial layers 124a and 124b include epitaxially grown silicon (Si) layers. Alternatively, in some embodiments, any of the epitaxial layers 122a, 122b, 122m and 124a, 124b may include other materials such as germanium, tin, compound semiconductors (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide), alloy semiconductors (such as SiGe, GeSn, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP and / or GaInAsP), III-V, or combinations thereof. As discussed, the materials of the epitaxial layers 122a, 122b, 122m and 124a, 124b may be selected based on providing different oxidation and / or etching selectivity properties.

[0074] exist Figure 1A and Figure 1BIn the embodiment of the present invention, at least one fin structure 125 extending from the substrate 110 is formed. In various embodiments, the fin structure 125 includes a protruding portion 112 formed by a portion of each of the epitaxial layers of the substrate 110 and the epitaxial stack, the epitaxial stack including the epitaxial layers 122a, 122b, 122m and 124a, 124b. The fin structure 125 can be manufactured using a suitable process, including double patterning and multi-patterning processes. Typically, the double patterning or multi-patterning process combines lithography and self-alignment processes, thereby allowing the formation of patterns with, for example, a smaller pitch than that which can be obtained using a single direct lithography process. For example, in some embodiments, a sacrificial layer is formed over the substrate and the sacrificial layer is patterned using a lithography process. A self-alignment process is used to form spacers next to the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fin structure 125 by etching the epitaxial stack. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. Subsequently, the etching process forms a trench in the substrate 110, leaving the fin structure 125. The trench may be etched using dry etching (e.g., reactive ion etching), wet etching, and / or a combination thereof. Many other embodiments of the method of forming a fin on a substrate may also be used, including, for example, defining a fin region (e.g., by a mask or isolation region) and epitaxially growing an epitaxial stack in the form of the fin structure 125.

[0075] Next, if Figure 1A and Figure 1BAs illustrated in , the isolation structure 140 is formed to surround the fin structure 125. The isolation structure 140 may include a pad oxide (not shown). The pad oxide may be formed by a thermal oxide formed by thermal oxidation of a surface layer of the substrate 110. The pad oxide may also be a deposited silicon oxide layer formed using, for example, atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), or chemical vapor deposition (CVD). The isolation structure 140 may also include a dielectric material located above the pad oxide, and the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, or the like. Subsequently, the isolation structure 140 is recessed so that the top portion of the fin structure 125 protrudes above the top surface of the adjacent isolation structure 140. Etching may be performed using a dry etching process, in which NH3 and NF3 are used as etching gases. During the etching process, plasma may be generated. Argon may also be included. According to an alternative embodiment of the present disclosure, a wet etching process is used to perform the recessing of the isolation structure 140. For example, the etching chemistry may include diluted HF.

[0076] refer to Figure 2A and Figure 2B At least one dummy gate structure 150 is formed above the substrate 110 and is partially disposed above the fin structure 125. The portion of the fin structure 125 below the dummy gate structure 150 may be referred to as a channel region. The dummy gate structure 150 may also define a source / drain region S / D of the fin structure 125 (at Figure 3A ), for example, a region of the fin structure 125 that is adjacent to the channel region and is located on the opposite side of the channel region.

[0077] The dummy gate formation operation forms a dummy gate dielectric layer, a dummy gate electrode layer, and a hard mask, which may include multiple layers (e.g., an oxide layer and a nitride layer) located above the dummy gate electrode layer. The hard mask is then patterned, followed by patterning the dummy gate electrode layer by using the patterned hard mask as an etching mask. The etching process may include wet etching, dry etching, and / or a combination thereof. Thus, a dummy gate structure 150 including a dummy gate dielectric layer 152, a dummy gate electrode layer 154, and a hard mask (e.g., an oxide layer 156 and a nitride layer 158) is formed.

[0078] In some embodiments, the dummy gate dielectric layer 152 may be made of a dielectric material such as silicon nitride (SiN), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), or the like, and may have a single-layer structure or a multi-layer structure including a plurality of dielectric layers. In some embodiments, the dummy gate dielectric layer 152 may be made of a high-k dielectric material such as a metal oxide, a transition metal oxide, or the like. Examples of high-k dielectric materials include, but are not limited to, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide, titanium oxide, aluminum oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, or other suitable dielectric materials. In some embodiments, the dummy gate dielectric layer 152 is an oxide layer. The dummy gate dielectric layer 152 may be formed by a deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plasma enhanced CVD (PECVD), or other suitable techniques. In some embodiments, the dummy gate electrode layer 154 may include polysilicon (poly-Si), poly-silicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, or metal. In some embodiments, the dummy gate electrode layer 154 includes a metal-containing material such as TiN, TaN, TaC, Co, Ru, Al, combinations thereof, or multilayers thereof. The dummy gate electrode layer 154 may be deposited by CVD, physical vapor deposition (PVD), sputtering deposition, or other techniques suitable for depositing conductive materials.

[0079] After the formation of the dummy gate structure 150 is completed, Figure 2A On the sidewalls of the dummy gate structure 150 shown in FIG. Figure 2B A gate spacer 160 is formed on the sidewall of the fin structure 125 shown in FIG. Figure 2A ) and fin spacers 162 (see Figure 2B). For example, a spacer material layer is deposited on the substrate 110. The spacer material layer may be a conformal layer, which is then etched back to form a gate sidewall spacer. In the illustrated embodiment, the spacer material layer is conformally disposed on the top and sidewalls of the dummy gate structure 150 and the fin structure 125. The spacer material layer may include a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN film, silicon oxycarbide, SiOCN film and / or a combination thereof. In some embodiments, the spacer material layer includes multiple layers, such as a first spacer layer and a second spacer layer formed above the first spacer layer. As an example, the spacer material layer can be formed by depositing a dielectric material over the dummy gate structure 150 and the fin structure 125 using a suitable deposition process. The deposited spacer material layer is then subjected to an anisotropic etching process to expose portions of the fin structure 125 that are not covered by the dummy gate structure 150 (e.g., above the source / drain regions of the fin structure 125). The portions of the spacer material layer directly above the dummy gate structure 150 and the fin structure 125 may be completely removed by the anisotropic etching process. For simplicity, portions of the spacer material layer on the sidewalls of the dummy gate structure 150 and the fin structure 125 may remain to form gate sidewall spacers, which are represented as gate spacers 160 and fin spacers 162. Figure 2B As shown in , the process conditions for patterning the spacer material layer (e.g., the tilt angle of the directional plasma ion beam used in the plasma etching process) are controlled so that the top of the fin spacer 162 is lower than the top surface of the fin structure 125. In this way, the top surface and the upper portion of the sidewall of the fin structure 125 are exposed. A portion of the spacer material layer may remain on the isolation structure 140 and connect adjacent fin spacers 162. In some embodiments, the dummy gate structure 150 may be interchangeably referred to as a dummy gate, a dummy gate pattern, a dummy gate strip, an isolation structure, or a dielectric gate.

[0080] refer to Figure 3A and Figure 3BThe exposed portion of the fin structure 125 that laterally extends beyond the gate spacer 160 (e.g., in the source / drain region S / D of the fin structure 125) is etched using, for example, an anisotropic etching process that uses the dummy gate structure 150 and the gate spacer 160 as an etching mask, thereby generating a recess R1 in the fin structure 125. After the anisotropic etching, the end surfaces of the epitaxial layers 122a, 122b, 122m and the epitaxial layers 124a, 124b and the outermost sidewalls of the gate spacer 160 are substantially connected due to the anisotropic etching. In some embodiments, the anisotropic etching can be performed by dry chemical etching using a plasma source and a reactive gas. The plasma source may be an inductively coupled plasma (ICP) source, a transformer coupled plasma (TCP) source, an electron cyclotron resonance (ECR) source or the like, and the reaction gas may be, for example, a fluorine gas (such as SF6, CH2F2, CH3F, CHF3 or the like), a chlorine gas (such as Cl2), hydrogen bromide gas (HBr), oxygen (O2), the like or a combination thereof.

[0081] Subsequently, the epitaxial layers 122a, 122b, and 122m are recessed laterally or horizontally by using a suitable etching technique, thereby producing a lateral recess R2 and a space S1 each vertically located between the corresponding epitaxial layers 124a and 124b. This operation can be performed by using a selective etching process. As an example and not limitation, the epitaxial layers 122a, 122b, and 122m are SiGe, and the epitaxial layers 124a and 124b are silicon, thereby allowing selective etching of the epitaxial layers 122a, 122b, and 122m. In some embodiments, the selective dry etching etches SiGe at a faster etching rate than it etches Si. Therefore, the epitaxial layers 124a and 124b extend laterally beyond the opposite end surfaces of the epitaxial layers 122a and 122b. In addition, due to the epitaxial layer 122m (see Figure 2A ) has a greater germanium atomic concentration than the epitaxial layers 122a and 122b, the selective dry etching etches the epitaxial layer 122m at a faster etching rate than it etches the epitaxial layers 122a, 122b, and thus the epitaxial layer 122m can be completely removed while the epitaxial layers 122a, 122b can be only partially removed.

[0082] Then, in the groove R2 and the space S1 (see Figure 3A) is filled with internal dielectric spacers 172 and 174. For example, the spacer material layer is formed to fill the groove R2 and space S1 left by lateral etching of the epitaxial layers 122a, 122b and 122m discussed above. The spacer material layer may be a low-k dielectric material such as SiO2, SiN, SiC, SiON, SiCN or SiOCN, and may be formed by a suitable deposition method such as ALD. In some embodiments, the spacer material layer is intrinsic or undoped with impurities. The spacer material layer may be formed using CVD (including LPCVD and PECVD), PVD, ALD or other suitable processes. After depositing the spacer material layer, an anisotropic etching process may be performed to trim the deposited spacer material layer so that a portion of the deposited spacer material layer is left filling the groove R2 and space S1 left by lateral etching of the epitaxial layers 122a, 122b and 122m. After the trimming process, for simplicity, the remaining portions of the deposited spacer material are represented as inner dielectric spacers 172 in recess R2 and inner dielectric spacers 174 in space S1. The inner dielectric spacers 172 and 174 serve to isolate the metal gate from source / drain epitaxial structures formed in subsequent processing.

[0083] refer to Figure 4A and Figure 4B . The first source / drain epitaxial structure 180 is formed above the source / drain region S / D of the fin structure 125 and is connected to the epitaxial layer 124a. In some embodiments, each of the first source / drain epitaxial structures 180 has a facet 181' facing upward. In some embodiments, the facet 181' is a {111} facet. The first source / drain epitaxial structure 180 can be formed by performing an epitaxial growth process of providing an epitaxial material on the fin structure 125. In some embodiments, the first source / drain epitaxial structure 180 may include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable materials. The first source / drain epitaxial structure 180 can be doped by introducing doping species, which include: p-type dopants such as boron or BF2; n-type dopants such as phosphorus or arsenic; and / or other suitable dopants, including combinations thereof. In some exemplary embodiments, the first source / drain epitaxial structure 180 in p-type includes SiGeB and / or GeSnB. In some implementations, the first source / drain epitaxial structure 180 may be interchangeably referred to as a source / drain pattern or an epitaxial pattern.

[0084] An interlayer dielectric (ILD) layer 194 is formed over the substrate 110. In some embodiments, a contact etch stop layer (CESL) 192 is also formed before forming the ILD layer 194. In some examples, the CESL 192 includes a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, and / or other suitable materials having a different etching selectivity from the ILD layer 194. In some embodiments, the CESL 192 and the ILD layer 194 may be collectively referred to as an isolation structure 190. In some embodiments, the ILD layer 194 includes a material such as an oxide formed of tetraethylorthosilicate (TEOS), undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), borondoped silicon glass (BSG), and / or other suitable dielectric materials having a different etching selectivity from the CESL 192. Subsequently, the isolation structure 190 is recessed so that the upper portion of the recess R1 can be reproduced.

[0085] A second source / drain epitaxial structure 185 is formed over the epitaxial isolation structure 190. In some embodiments, the second source / drain epitaxial structure 185 may include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable materials. The second source / drain epitaxial structure 185 may be doped by introducing doping species, which include: p-type dopants such as boron or BF2; n-type dopants such as phosphorus or arsenic; and / or other suitable dopants, including combinations thereof. In some exemplary embodiments, the second source / drain epitaxial structure 185 in the n-type transistor includes silicon phosphide (SiP). The first source / drain epitaxial structure 180 and the second source / drain epitaxial structure 185 are made of different materials. For example, the first source / drain epitaxial structure 180 is made of SiGeB, and the second source / drain epitaxial structure 185 is made of SiP. In some embodiments, the second source / drain epitaxial structure 185 may be interchangeably referred to as a source / drain pattern or an epitaxial pattern. Each of the epitaxial isolation stacks 190 is located between one of the first source / drain epitaxial structures 180 and one of the second source / drain epitaxial structures 185 to electrically isolate the first source / drain epitaxial structure 180 from the second source / drain epitaxial structure 185.

[0086] refer to Figure 5A and Figure 5B An ILD layer 198 is formed over the substrate 110. In some embodiments, a CESL 196 is also formed before forming the ILD layer 198. In some examples, the CESL 196 includes a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, and / or other suitable materials having a different etch selectivity than the ILD layer 198. In some embodiments, the CESL 192, 196 and the ILD layers 194, 198 may be collectively referred to as a dielectric structure. In some embodiments, the ILD layer 198 includes a material such as an oxide formed of tetraethylorthosilicate (TEOS), undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), borondoped silicon glass (BSG), and / or other suitable dielectric materials having a different etch selectivity than the CESL. After the deposition of the CESL 196 and the ILD layer 198, a planarization process (eg, a CMP process) may be performed to remove excess material of the CESL 196 and the ILD layer 198 covering the dummy gate structure 150, and further remove the hard mask layers 156 and 158 (eg, Figure 4A and Figure 4B ), so that the dummy gate electrode layer 154 is exposed.

[0087] Subsequently, the dummy gate dielectric layer 152 and / or the dummy gate electrode layer 154 are removed, thereby creating a gate trench between the gate spacers 160, wherein the epitaxial layers 122a and 122b are exposed in the gate trench. Subsequently, the epitaxial layers 122a and 122b in the gate trench are removed, thereby forming a space S2 between adjacent epitaxial layers (i.e., channel layers) 124a and 124b. In some embodiments, the epitaxial layers 124a and 124b may be interchangeably referred to as nanostructures (nanowires, nanoplates and nanorings, nanosheets, etc., depending on their geometric shapes).

[0088] A (metal) gate structure 220 is formed in the gate trench and space S2 to surround each of the epitaxial layers 124a and 124b suspended in the gate trench and space S2. In various embodiments, the gate structure 220 includes an interface layer 222 formed around the respective epitaxial layers 124a and 124b, a high-k gate dielectric layer 224 formed on the interface layer 222, and a gate electrode layer 226 formed around the high-k gate dielectric layer 224 and filling the rest of the gate trench. In some embodiments, the interface layer 222 may include a dielectric material such as silicon oxide (SiO2), HfSiO, or silicon oxynitride (SiON). The high-k dielectric layer 224 may include a dielectric material having a high dielectric constant (high-k), such as a dielectric material having a dielectric constant greater than that of thermal silicon oxide (about 3.9). For example, the high-k dielectric layer 224 may include hafnium oxide (HfO2). The gate electrode layer 226 may include a work function metal layer and / or a fill metal formed around the work function metal layer. For an n-type FinFET, the gate electrode layer 226 may include one or more n-type work function metals. On the other hand, for a p-type FinFET, the work function metal layer 226 may include one or more p-type work function metals. In some embodiments, the fill metal may illustratively include but is not limited to tungsten, aluminum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN or other suitable materials. After forming the gate structure 220, the gate electrode layer 226 is etched back using an etching process so that the upper portion of the gate trench can be reproduced. In some embodiments, the gate structure 220 may be interchangeably referred to as a metal gate, a gate pattern, or a gate strip.

[0089] The gate electrode layer 236 is deposited in the gate trench and above the high-k gate dielectric layer 224. Thus, a gate structure 230 including the interface layer 222, the high-k gate dielectric layer 224, and the gate electrode layer 236 is formed in the remaining portion of the space S2. Thus, a semiconductor device 100a is formed. In some embodiments, the gate structure 230 may be interchangeably referred to as a metal gate, a gate pattern, or a gate strip. In some embodiments, the gate electrode layer 236 may include a work function metal layer and / or a fill metal formed around the work function metal layer. For n-type FinFETs, the work function metal layer may include one or more n-type work function metals. On the other hand, for p-type FinFETs, the work function metal layer may include one or more p-type work function metals. In some embodiments, the fill metal may illustratively include but is not limited to tungsten, aluminum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN, or other suitable materials.

[0090] The semiconductor device 100a includes a bottom transistor Tb and a top transistor Tt. The top transistor Tt is located above the bottom transistor Tb. The bottom transistor Tb includes a channel layer 124a, a first source / drain epitaxial structure 180 located on the opposite side of the channel layer 124a and connected to the channel layer 124a, and a gate structure 220 surrounding the channel layer 124a. The top transistor Tt includes a channel layer 124b, a second source / drain epitaxial structure 185 located on the opposite side of the channel layer 124b and connected to the channel layer 124b, and a (metal) gate structure 230 surrounding the channel layer 124b. In some embodiments, the bottom transistor Tb is a p-type transistor, and the top transistor Tt is an n-type transistor. In some other embodiments, the bottom transistor Tb is an n-type transistor, and the top transistor Tt is a p-type transistor. Subsequently, a hard mask layer 238 is formed above the gate structure 230. In some embodiments, the hard mask layer 238 may be made of a nitride-based material (such as Si 3 N 4 , SiON) or a carbon-based material (such as SiC, SiOC, SiOCN, or a combination thereof).

[0091] refer to Fig. 6A and Figure 6B A source / drain contact opening O1 is formed through the CESL 196 and the ILD layer 198 to expose the second source / drain epitaxial structure 185 from the front side 198f of the ILD layer 198. Specifically, one or more etching processes may be performed to sequentially etch down through the CESL 196 and the ILD layer 198 to the second source / drain epitaxial structure 185 to form the source / drain contact opening O1. In some embodiments, the etching process will consume the second source / drain epitaxial structure 185, and thus the second source / drain epitaxial structure 185 may be damaged, such as Fig. 6A and Figure 6B That is, the first source / drain epitaxial structure 180 may have an asymmetric cross-sectional view. In some embodiments, the source / drain contact opening O1 may further extend downward to the ILD layer 194, such as Figure 6B as shown in .

[0092] In some embodiments, the etching process is an anisotropic dry etching process (e.g., a reactive-ion etching (RIE) process or an atomic layer etching (ALE) process). As an example and not limitation, the dry etching process can be implemented with an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, CH3F and / or C4F8), a chlorine-containing gas (e.g., Cl2 and / or BCl3), a bromine-containing gas (e.g., HBr), an iodine-containing gas, other suitable gases and / or plasma, and / or combinations thereof.

[0093] refer to Fig. 7A and Figure 7B . In forming source / drain contacts 242 (see Fig. 9A and Fig. 9B ), a metal silicide layer 186 may be selectively formed on the second source / drain epitaxial structure 185 by a metal silicide process. In some embodiments, the metal silicide layer 186 may be formed to surround the second source / drain epitaxial structure 185, and its formation may be referred to as a silicide-first approach with a thermally stable silicide that can withstand potential HK / MG heat treatment (>850°C). The metal silicide process is a reaction between a metal and silicon (or polysilicon). With respect to the metal silicide process, a first rapid thermal annealing (RTA) process may be performed in an atmosphere such as Ar, He, N2 or other inert atmosphere at a first temperature such as below 200°C to 300°C to convert the deposited metal layer into a metal silicide. This is followed by an etching process for removing the unreacted metal layer from the metal silicide. The etching process may include wet etching, dry etching and / or a combination thereof. As an example, the etchant for the wet etching may include a mixed solution of H2SO4, H2O2, H2O and / or other suitable wet etching solutions, and / or combinations thereof. Then, a second annealing or RTA step is performed at a second temperature higher than the first temperature, such as 400°C to 500°C, to form a metal silicide layer 186 having a low resistance. In some embodiments, when the second source / drain epitaxial structure 185 is an n-type source / drain region, the metal silicide layer 186 formed above the second source / drain epitaxial structure 185 may be interchangeably referred to as n-type silicide. In some embodiments, the metal silicide layer 186 may include titanium silicide (TiSi), nickel silicide (NiSi), cobalt silicide (CoSi), Ni-Pt, or a combination thereof. The metal silicide layer 186 formed on the second source / drain epitaxial structure 185 may provide a flat silicide surface area without damaging Rcsd. In some embodiments, the metal silicide layer 186 may be interchangeably referred to as a front-side metal silicide layer.

[0094] refer to Fig. 8A and Figure 8B. A metal capping structure 187 is formed on the metal silicide layer 186 by a suitable process such as CVD or ALD. In some embodiments, a deposition process P1 such as a bottom-up approach is used to form the metal capping structure 187 on the metal silicide layer 186. For example, the metal capping structure 187 is selectively grown on a metal surface such as the metal silicide layer 186, and thus the ILD layers 194 and 198 are substantially free of growth of the metal capping structure 187. Because the metal silicide layer 186 and the metal capping structure 187 can be selectively formed on the second source / drain epitaxial structure 185 rather than on the surrounding dielectric, the metal silicide layer 186 and the metal capping structure 187 can occupy less space in the source / drain opening O1, which in turn facilitates subsequent metal (e.g., such as Fig. 9A and Fig. 9B The source / drain contacts 242 shown in FIG. 1 are filled in the source / drain openings O1 and thus can improve the silicide diffusion contact resistance of the IC structure.

[0095] As an example and not limitation, the metal capping structure 187 may be a substantially fluorine-free tungsten (FFW) film having an amount of fluorine contaminants less than 5 atomic percent. The FFW film or the FFW-containing film may be formed by ALD or CVD using one or more non-fluorine-based tungsten precursors, such as but not limited to tungsten pentachloride (WCl5), tungsten hexachloride (WCl6). In some embodiments, the metal capping structure 187 may have a chlorine atomic concentration in a range of about 0.1% to about 5%, and thus a distinguishable interface may be formed between the metal capping structure 187 and the source / drain contacts 242 (see Fig. 9A and Fig. 9B ). In some embodiments, a portion of the metal capping structure 187 may overflow the metal silicide layer 186 so that the metal capping structure 187 may also cover the exposed surface of the ESL 196. Since the metal capping structure 187 is formed in a bottom-up manner, its formation can be simplified by, for example, reducing repeated etch-back processes for removing undesired metal materials generated by conformal growth. In some embodiments, the metal capping structure 187 may be interchangeably referred to as the front-side metal capping structure 187.

[0096] The selective formation of the metal capping structure 187 on the metal silicide layer 186 rather than on the dielectric layers (e.g., ILD layers 194 and 198) is primarily due to the relative electrical behaviors exhibited by the metal silicide and dielectric materials. Deposition process P1 exploits this difference to achieve the targeted growth of the metal capping structure 187 only on the metal silicide layer 186. The electrical behavior of a material is constrained by the nature of the chemical bonding between its constituent atoms and its ability to efficiently transport charge. In this context, the different electrical behaviors exhibited by the metal silicide and dielectric materials are caused by the difference in conductivity between the metal silicide layer 186 and the dielectric layers 194 and 198.

[0097] Specifically, the metal silicide layer 186 may be composed of a metal (e.g., tungsten) and a semiconductor (e.g., silicon) that form compounds with metallic properties. These compounds exhibit high electrical conductivity due to the presence of free electrons, which can pass through the material relatively easily. Therefore, the metal silicide layer 186 can retain charge and generate an electrostatic field in its vicinity. On the other hand, dielectric materials (e.g., dielectric layers 194 and 198) are insulators with poor charge conduction. These dielectric materials exhibit extremely low electrical conductivity because the electrons in the material are firmly bonded to their parent atoms, thereby limiting their mobility. This characteristic hinders the ability of the dielectric layer to retain charge and generate an electrostatic field.

[0098] In a deposition process using a tungsten precursor such as tungsten pentachloride (WCl5) or tungsten hexachloride (WCl6), tungsten atoms are surrounded by negatively charged chloride ions. Due to the higher conductivity of the metal silicide layer 186, it can accumulate a net positive charge that attracts the negatively charged chloride ions, thereby facilitating the adsorption of tungsten atoms on the metal silicide layer. In contrast, the dielectric layers 194 and 198 cannot hold a large amount of charge due to their insulating properties, making it less likely that tungsten atoms will be adsorbed on their surfaces. Therefore, the metal capping structure 187 is selectively formed on the metal silicide layer 186 rather than on the dielectric layer.

[0099] refer to Fig. 9A and Fig. 9B. A source / drain contact 242 is formed in the remaining portion of the source / drain contact opening O1 and on the metal capping structure 187. In some embodiments, the source / drain contact 242 may be interchangeably referred to as a metal-like defined (MD) layer. In some embodiments, the source / drain contact 242 may be interchangeably referred to as a front-side contact. In more detail, a conductive material may be formed by using a metallization process and using a deposition process P2 that is different from the deposition process P1 to fill the source / drain contact opening O1. As an example and not limitation, the deposition process P1 to form the metal capping structure 187 may be a chemical vapor deposition (CVD) process, and the deposition process P2 to form the source / drain contact 242 may be a physical vapor deposition (PVD) process. Subsequently, excess portions of the conductive layer are removed by etching, chemical mechanical polishing (CMP), or the like, thereby forming an upper surface of the metal-filled opening that is substantially coplanar with the top surface of the ILD layer 198. The remaining portion of the conductive material in the source / drain contact opening O1 forms the source / drain contact 242. The conductive material may include a low resistivity conductive material selected from a group of conductive materials, the group of conductive materials including but not limited to tungsten and tungsten-based alloys. Alternatively, the conductive material may include various materials such as cobalt, copper, ruthenium, aluminum, gold, silver, another suitable conductive material, or a combination thereof. In some embodiments, the conductive material may be a tungsten-containing layer formed above the tungsten seed layer (e.g., a tungsten cap formed on the second source / drain epitaxial structure 185). In some embodiments, the source / drain contact 242 has a first cross-sectional profile and a second cross-sectional profile located between the first cross-sectional profile and the metal capping structure 187, and the first cross-sectional profile has a wider width than the second cross-sectional profile.

[0100] refer to FIG. 10A to FIG. 11B . Fig. 9A and Fig. 9B The structure is "flipped" upside down (see Fig. 10A and Fig. 10B ), and the substrate 110 may be thinned from the back side 110b of the substrate 110 (see Fig.11A and Fig. 11B The substrate 110 may be thinned in a number of process operations such as CMP, HNA and / or TMAH etching performed from the back side 110 b of the substrate 110 .

[0101] refer to FIG. 12A to FIG. 13B Source / drain contact openings O2 are formed through the ILD layer 194 (see Fig.13A and Fig. 13B) to expose the first source / drain epitaxial structure 180 and the source / drain contact 242.

[0102] like Fig. 12A and Fig. 12B As shown, one or more etching processes P3 may be performed to sequentially etch downward from the back side 194b of the ILD layer 194 through the isolation structure 140, the fin spacer 162, the CESL 192, and the ILD layer 194 to reach the source / drain contact 242 to form an auxiliary contact opening O21, and also expose the small face 181' of the first source / drain epitaxial structure 180 from the auxiliary contact opening O21. In some embodiments, the etching process is performed until the back side surface 242b of the source / drain contact 242 is exposed, and the source / drain contact 242 can serve as an etching stop layer for the etching process. In some embodiments, the etching process will consume the first source / drain epitaxial structure 180, and thus the first source / drain epitaxial structure 180 may be damaged, such as Fig. 12A and Fig. 12B As shown in . That is, the second source / drain epitaxial structure 185 may have an asymmetric cross-sectional view. In some embodiments, the etching process is an anisotropic dry etching process (e.g., a reactive-ionetching (RIE) process or an atomic layer etching (ALE) process). As an example and not limitation, the dry etching process may be implemented with an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, CH3F and / or C4F8), a chlorine-containing gas (e.g., Cl2 and / or BCl3), a bromine-containing gas (e.g., HBr), an iodine-containing gas, other suitable gases and / or plasma, and / or combinations thereof.

[0103] Then, if Fig.13A and Fig. 13B As shown in FIG. 1 , the protruding portion 112 is removed to expose the first source / drain epitaxial structure 180. An etching process P4 may be performed to remove the protruding portion 112 on the first source / drain epitaxial structure 180, thereby forming an auxiliary contact opening O22 (see FIG. 1 ). Fig. 13B), wherein the first source / drain epitaxial structure 180 may act as an etch stop layer so that the auxiliary contact opening O22 may inherit the shape of the protruding portion 112 and be self-aligned with the first source / drain epitaxial structure 180. In some embodiments, the auxiliary contact openings O21 and O22 may be collectively referred to as the source / drain contact opening O2. In some embodiments, the etching process P4 may be an anisotropic dry etching process, such as a dry etching process (e.g., RIE, NBE, or the like), and may use an etchant different from the etchant used in the etching process P3. In some embodiments, the protruding portion 112 may be made of a material having a high etching selectivity relative to the source / drain region 180, the isolation structure 140, and the gate spacer 160. For example, the etching selectivity is the ratio of the etching speed of the protruding portion 112 to the first source / drain epitaxial structure 180, the fin spacer 162, the CESL 192, and the ILD layer 194 when etching the protruding portion 112.

[0104] refer to Fig.14A and Fig. 14B . In forming source / drain contacts 244 (see Fig.16A and Fig. 16B), a metal silicide layer 182a may be selectively formed on the first source / drain epitaxial structure 180 by a metal silicide process. In some embodiments, the metal silicide layer 182a may be formed to surround the first source / drain epitaxial structure 180, and its formation may be referred to as a silicide-first pathway with a thermally stable silicide that can withstand potential HK / MG thermal treatment (>850°C). The metal silicide process is a reaction between a metal and silicon (or polysilicon). With respect to the metal silicide process, a first rapid thermal annealing (RTA) process may be performed in an atmosphere such as Ar, He, N2 or other inert atmosphere at a first temperature such as below 200°C to 300°C to convert the deposited metal layer into a metal silicide. This is followed by an etching process for removing the unreacted metal layer from the metal silicide. The etching process may include wet etching, dry etching and / or a combination thereof. As an example, the etchant of the wet etching may include a mixed solution of H2SO4, H2O2, H2O and / or other suitable wet etching solutions, and / or combinations thereof. Then, a second annealing or RTA step is performed at a second temperature higher than the first temperature, such as 400°C to 500°C, to form a metal silicide layer 182a having a low resistance. In some embodiments, when the first source / drain epitaxial structure 180 is a p-type source / drain region, the metal silicide layer 182a formed above the first source / drain epitaxial structure 180 may be interchangeably referred to as a p-type silicide. In some embodiments, the metal silicide layer 182a may include molybdenum silicon germanium (MoSiGe), titanium silicide (TiSi), nickel silicide (NiSi), cobalt silicide (CoSi), Ni-Pt, or a combination thereof. The metal silicide layer 182a formed on the first source / drain epitaxial structure 180 may provide a flat silicide surface area without damaging Rcsd. In some embodiments, the metal silicide layer 182a may be interchangeably referred to as a backside metal silicide layer. In some embodiments, the metal silicide layer 182a on the first source / drain epitaxial structure 180 may be made of a different material than the metal silicide layer 186 on the second source / drain epitaxial structure 185, and thus the formation of the metal silicide layers 182a and 186 may be referred to as a double silicide for low Rcsd on different device types (e.g., n-type devices, p-type devices). As an example and not limitation, the metal silicide layer 182a may be made of MoSiGe, while the metal silicide layer 186 may be made of TiSi.

[0105] refer to Fig.15A and Fig. 15B. A metal capping structure 183a is formed on the metal silicide layer 182a by a suitable process such as CVD or ALD. In some embodiments, a deposition process P5 such as a bottom-up approach is used to form the metal capping structure 183a on the metal silicide layer 182a. For example, the metal capping structure 183a is selectively grown on a metal surface such as the metal silicide layer 182a, and thus the ILD layer 194 is substantially free of growth of the metal capping structure 183a. Because the metal silicide layer 182a and the metal capping structure 183a can be selectively formed on the first source / drain epitaxial structure 180 rather than on the surrounding dielectric, the metal silicide layer 182a and the metal capping structure 183a can occupy less space in the source / drain opening O2, which in turn facilitates subsequent metal (e.g., such as Fig.16A and Fig. 16B The source / drain contacts 244 shown in FIG. 1 are filled in the source / drain openings O2 and thus can improve the silicide diffusion contact resistance of the IC structure.

[0106] The selective formation of the metal capping structure 183a on the metal silicide layer 182a rather than on the dielectric layer (e.g., ILD layer 194) is primarily due to the relative electrical behaviors exhibited by the metal silicide and dielectric materials. Deposition process P5 exploits this difference to achieve the targeted growth of the metal capping structure 183a only on the metal silicide layer 182a. The electrical behavior properties of a material are constrained by the nature of the chemical bonding between its constituent atoms and its ability to efficiently transport charge. In this context, the different electrical behaviors exhibited by the metal silicide and dielectric materials are caused by the difference in conductivity between the metal silicide layer 182a and the dielectric layer 194.

[0107] Specifically, the metal silicide layer 182a can be composed of a metal (e.g., tungsten) and a semiconductor (e.g., silicon), which form compounds with metallic properties. These compounds exhibit high electrical conductivity due to the presence of free electrons, which can pass through the material relatively easily. Therefore, the metal silicide layer 182a can retain charge and generate an electrostatic field in its vicinity. On the other hand, dielectric materials (e.g., dielectric layer 194) are insulators with poor charge conduction. These dielectric materials exhibit extremely low electrical conductivity because the electrons in the material are firmly bonded to their parent atoms, thereby limiting their mobility. This characteristic hinders the ability of the dielectric layer to retain charge and generate an electrostatic field.

[0108] In a deposition process using a tungsten precursor such as tungsten pentachloride (WCl5) or tungsten hexachloride (WCl6), tungsten atoms are surrounded by negatively charged chloride ions. Due to the higher conductivity of the metal silicide layer 182a, it can accumulate a net positive charge that attracts negatively charged chloride ions, thereby facilitating the adsorption of tungsten atoms on the metal silicide layer. In contrast, the dielectric layer 194 cannot hold a large amount of charge due to its insulating properties, making it less likely that tungsten atoms will be adsorbed on their surfaces. Therefore, the metal capping structure 183a is selectively formed on the metal silicide layer 182a, rather than on the dielectric layer.

[0109] As an example and not limitation, the metal capping structure 183a may be a substantially fluorine-free tungsten (FFW) film having an amount of fluorine contaminants less than 5 atomic percent. The FFW film or the FFW-containing film may be formed by ALD or CVD using one or more non-fluorine-based tungsten precursors, such as but not limited to tungsten pentachloride (WCl5), tungsten hexachloride (WCl6). In some embodiments, the metal capping structure 183a may have a chlorine atomic concentration in a range of about 0.1% to about 5%, and thus a distinguishable interface may be formed between the metal capping structure 183a and the source / drain contacts 244 (see Fig.16A and Fig. 16B ). In some embodiments, a portion of the metal capping structure 183a may overflow the metal silicide layer 182a, so that the metal capping structure 183a may also cover the exposed surface of the ESL 192. Since the metal capping structure 183a is formed in a bottom-up manner, its formation can be simplified by, for example, reducing repeated etch-back processes for removing undesired metal materials generated by conformal growth. In some embodiments, the metal capping structure 183a may be interchangeably referred to as a backside metal capping structure.

[0110] refer to Fig.16A and Fig. 16B. A source / drain contact 244 is formed in the remaining portion of the source / drain contact opening O2 and on the metal capping structure 183a and the source / drain contact 242. In some embodiments, the source / drain contact 244 may be interchangeably referred to as a metal-like defined (MD) layer. In some embodiments, the source / drain contact 244 may be interchangeably referred to as a backside contact. In more detail, a conductive material may be formed by using a metallization process and using a deposition process P6 that is different from the deposition process P5 to fill the source / drain contact opening O2. As an example and not limitation, the deposition process P5 for forming the metal capping structure 183a may be a chemical vapor deposition (CVD) process, and the deposition process P6 for forming the source / drain contact 244 may be a physical vapor deposition (PVD) process. Subsequently, excess portions of the conductive layer are removed by etching, chemical mechanical polishing (CMP), or the like, thereby forming an upper surface of the metal-filled opening that is substantially coplanar with the top surface of the ILD layer 194. The remainder of the conductive material in the source / drain contact opening O2 forms the source / drain contact 244. The conductive material may include a low-resistivity conductive material selected from a group of conductive materials, the group of conductive materials including but not limited to tungsten and tungsten-based alloys. Alternatively, the conductive material may include various materials, such as cobalt, copper, ruthenium, aluminum, gold, silver, another suitable conductive material, or a combination thereof. In some embodiments, the conductive material may be a tungsten-containing layer formed above the tungsten seed layer (e.g., a tungsten cap formed on the second source / drain epitaxial structure 180). For ease of description, Fig.17A and Fig. 17B The structure and Fig.16A and Fig. 16B The structure is "flipped" upside down to describe the relationship of one component or feature to another component or feature as illustrated in the figure. In some embodiments, the back portion 242p of the source / drain contact 242 and the front portion 244p of the source / drain contact 244 can be collectively referred to as an internal connecting hole. In some embodiments, because there is no metal nitride as a pad for surrounding the source / drain contacts 242 and 244, the source / drain contacts 242 and 244 can be directly connected through the conductive material therein, respectively, which in turn improves the low Rcsd of the semiconductor device 100a. In some embodiments, the source / drain contact 244 has a first cross-sectional profile and a second cross-sectional profile located between the first cross-sectional profile and the metal capping structure 183a, and the first cross-sectional profile has a wider width than the second cross-sectional profile.

[0111] refer to FIG. 17C to FIG. 17F . FIG. 17C to FIG. 17F Description of some embodiments of the present disclosure Fig.17A and Fig. 17B Schematic cross-sectional view of a semiconductor structure of FIG. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0112] like Fig. 17C As shown in Fig. 17C The examples in Fig.17A and Fig. 17B The difference between the embodiments in FIG. 1 and FIG. 2 is that the additional metal layer 182b and the additional metal capping structure 183b may be formed on the back side 242b of the source / drain contact 242 and sandwiched between the source / drain contacts 242 and 244. Specifically, before forming the source / drain contact 244, a metal silicide layer 182a may be selectively formed on the second source / drain epitaxial structure 185 by a metal silicide process. The deposited metal of the metal silicide process for forming the metal silicide layer 182a may also be deposited on the back side 242b of the source / drain contact 242, so that the metal layer 182b may be formed on the back side 242b of the source / drain contact 242 and made of the same metal element as the metal silicide layer 182a, such as molybdenum.

[0113] The selective formation of the metal layer 182b on the back side 242b of the source / drain contact 242 rather than on the dielectric layer (e.g., ILD layer 194) can be attributed to the difference in the electronic properties of the metal and dielectric materials. The electronic properties of a material are determined by the nature of the chemical bonds between its constituent atoms and its performance in conducting charge. In this context, the difference lies in the conductivity of the source / drain contact 242 and the dielectric layer 194. The source / drain contact 242 is made of a conductive material that exhibits high conductivity due to the presence of free electrons, which can move through the material relatively easily. Therefore, the source / drain contact 242 is more likely to hold a charge and generate an electrostatic field around it. On the other hand, dielectric materials (e.g., dielectric layer 194) are insulators that do not conduct charge well. These dielectric materials have extremely low conductivity because the electrons in the material are firmly bonded to their parent atoms, thereby limiting their movement. This makes it difficult for the dielectric layer to hold a charge and generate an electrostatic field. During the deposition process, the higher conductivity of the source / drain contact 242 affects the regional electric field near the surface, which can help promote the adsorption and accumulation of metal atoms, resulting in the formation of the metal layer 182b. In contrast, the dielectric layer 194 cannot hold a large amount of charge due to its insulating properties, making it less likely that metal atoms will be adsorbed on its surface. Therefore, the metal layer 182b is selectively formed on the back side 242b of the source / drain contact 242, and not on the dielectric layer 194.

[0114] In some embodiments, a molybdenum precursor may be used to form a metal silicide and used in a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process so that molybdenum may be deposited on the SiGe source / drain regions. During a subsequent annealing step, the deposited molybdenum reacts with the silicon and germanium atoms in the source / drain regions to form the desired molybdenum silicon germanium (MoSiGe) silicide. On the other hand, when the molybdenum precursor is deposited during the metal silicidation process, the molybdenum atoms in the precursor may be in a neutral state. The source / drain contact 242 is made of a conductive material that exhibits a high conductivity. This means that the source / drain contact 242 may have a better ability to dissipate any regional charge accumulation that may occur during the deposition process. This may help create a more favorable environment for the molybdenum precursor to adsorb and accumulate on the back side 242b of the source / drain contact 242, resulting in the formation of the metal layer 182b. In contrast, the dielectric layer 194 is an insulating material with a low conductivity. Therefore, its ability to dissipate any regional charge accumulation is reduced, which can create an environment that is unfavorable for the adsorption and accumulation of the molybdenum precursor. This difference in electronic properties can help to selectively form the metal layer 182b on the back side 242b of the source / drain contact 242 rather than on the dielectric layer 194.

[0115] In some embodiments, the metal layer 182b may also be deposited on the dielectric layer, albeit with a thinner thickness than it is deposited on the source / drain contact 242. After the metal silicide process is completed, a removal step is performed to eliminate the unreacted metal on the source / drain region and consume any residual metal in other locations, such as any residual metal on the dielectric layer and on the source / drain contact 242. Due to the difference in thickness, the metal layer 182b on the dielectric layer is completely consumed and removed during the removal process. However, the metal layer 182b on the source / drain contact 242 is not completely consumed because its thickness is greater than that on the dielectric layer. This results in the formation of the remaining metal layer 182b on the source / drain contact 242.

[0116] In addition, by using Fig.15A and Fig. 15B In the case of forming the metal capping structure 183a by a deposition process P5 such as a bottom-up approach as shown in , the metal capping structure 183b may be formed on the metal layer 182b so that the metal capping structure 183b has the same material as the metal capping structure 183a. The metal capping structure 183b is selectively grown on the metal surface (e.g., the metal layer 182b) as the metal capping structure 183a, and the ILD layer 194 does not substantially grow the metal capping structures 183a and 183b. In some embodiments, as an example and not limitation, the metal capping structure 183b may be a substantially fluorine-free tungsten (FFW) film having an amount of fluorine contaminants less than 5 atomic percent. The FFW film or the FFW-containing film may be formed by ALD or CVD using one or more non-fluorine-based tungsten precursors, such as, but not limited to, tungsten pentachloride (WCl5), tungsten hexachloride (WCl6). In some embodiments, the metal capping structure 183b may have a chlorine atomic concentration in a range of about 0.1% to about 5%, and thus a distinguishable interface may be formed between the metal capping structure 183b and the source / drain contacts 244. Fig. 17C The metal layer 182b shown in FIG. 1 (eg, an unreacted metal layer in the metal silicidation process) can be removed from the back side 242b of the source / drain contact 242 by the etching process in the metal silicidation process described in the foregoing description (see FIG. 1 ). Fig.14A and Fig. 14B ), so that the metal capping structure 183b can be directly formed on the back side 242b of the source / drain contact 242, such as Fig.17D as shown in .

[0117] The selective formation of the metal capping structure 183b on the metal layer 182b rather than on the dielectric layer (e.g., ILD layer 194) can be attributed to the difference in the electronic properties of the metal and dielectric materials. The metal layer 182b is a conductive material, while the dielectric layer 194 is an insulating material. The high conductivity of the metal layer 182b can promote the adsorption and accumulation of the metal capping structure precursor due to the presence of a higher density of free charge carriers (electrons or holes) compared to the dielectric layer. The lower conductivity of the dielectric layer makes it less likely to attract and retain the metal capping structure precursor. During the deposition process, the conductive metal layer 182b can maintain a more uniform charge distribution on its surface, which can provide a more favorable environment for the metal capping structure precursor to adsorb and react. In contrast, the dielectric layer 194 can exhibit an uneven charge distribution due to its insulating properties, which can hinder the adsorption and reaction of the metal capping structure precursor. The conductive metal layer 182b can promote charge transfer between the precursor species and the surface, thereby promoting the adsorption, reaction and bonding of the metal capping structure precursor to form the metal capping structure 183b. On the other hand, the insulating dielectric layer has limited charge transfer capability, which can hinder the formation of the metal capping structure 183b on its surface.

[0118] like Fig.17E and Fig.17F As shown, Fig.17E and Fig.17F The examples in Fig.17A and Fig. 17BThe difference between the embodiments in FIG. 1 and FIG. 2 is that the additional liners 184 and 188 may be formed to line the sidewalls 242s and 244s of the source / drain contacts 242 and 244. Specifically, before forming the source / drain contact 242, the liner 188 may be conformally formed over the second source / drain epitaxial structure 185 and the ILD layer 198 and formed to line the source / drain contact opening O1. Thus, after the source / drain contact 242 is formed in the source / drain contact opening O1, the liner 188 may surround the source / drain contact 242. Similarly, before forming the source / drain contact 244, the liner 184 may be conformally formed over the first source / drain epitaxial structure 180 and the ILD layer 194 and formed to line the source / drain contact opening O2. Thus, after the source / drain contact 244 is formed in the source / drain contact opening O2, the liner 184 may surround the source / drain contact 244. In some embodiments, the liner 184 / 188 may be a seed layer for forming the source / drain contact 242 / 244. As an example and not limitation, if the source / drain contact 242 / 244 is made of tungsten, the liner 184 / 188 may be a tungsten-containing layer. In some embodiments, as an example and not limitation, the liner 184 / 188 may be formed by physical vapor deposition. In some embodiments, in order to prevent the metal from diffusing from the source / drain contacts 242 and 244 into the ILD layers 194 and 198, the liners 184 and 188 may be used as a diffusion barrier to prevent the metal from diffusing, and as an adhesion layer between the metal and the dielectric. As an example and not limitation, refractory metals, refractory metal nitrides, refractory metal-silicon-nitrides, and combinations thereof, such as TaN, Ta, Ti, TiN, TiSiN, WN, or combinations thereof, may be used for the barrier. In some embodiments, as an example and not limitation, the liner 184 / 188 may be formed by physical vapor deposition.

[0119] Therefore, based on the above discussion, it can be seen that the present disclosure provides advantages. However, it should be understood that other embodiments may provide additional advantages, and not all advantages must be disclosed herein, and not all embodiments require specific advantages. In various embodiments, the present disclosure provides a method for selectively forming metal silicide and metal capping structures on the source / drain region of a transistor rather than on the surrounding dielectric by a deposition process such as a CVD or ALD process. Thus, the deposition material of the metal silicide and the deposition material of the metal capping structure can be easily formed on the source / drain region through the source / drain opening in a limited deposition area. In addition, because the metal silicide and the metal capping structure can only be formed on the source / drain region and cannot be formed on the surrounding dielectric, the metal silicide and the metal capping structure occupy a smaller space in the source / drain opening, which in turn facilitates the subsequent metal filling in the source / drain opening, and thus the silicide diffusion contact resistance of the IC structure can be improved.

[0120] In some embodiments, a method includes the following steps: forming a bottom transistor and a top transistor located above the bottom transistor, the top transistor including a first channel layer, a first gate structure located around the first channel layer, and a plurality of first source / drain regions located on opposite sides of the first channel layer; forming a first dielectric layer above the first source / drain regions of the top transistor; etching the first dielectric layer to form a first opening exposing one of the first source / drain regions of the top transistor; selectively forming a first metal silicide on one of the first source / drain regions; selectively forming a first metal capping structure on the first metal silicide but not on the first dielectric layer; forming a front side contact on the first metal capping structure. In some embodiments, the first metal silicide includes TiSi or MoSiGe. In some embodiments, the first metal capping structure includes fluorine-free tungsten. In some embodiments, the first metal capping structure includes the same metal element as the front side contact. In some embodiments, the front side contact includes tungsten. In some embodiments, the selective formation of the first metal capping structure is performed by a deposition process different from the formation of the front side contact. In some embodiments, the bottom transistor includes a second channel layer, a second gate structure located around the second channel layer, and a plurality of second source / drain regions located on opposite sides of the second channel layer, and the method further includes the following steps: forming a second dielectric layer over the second source / drain region of the bottom transistor, wherein the first source / drain region of the top transistor is formed over the second dielectric layer; etching the second dielectric layer to form a second opening in the second dielectric layer, the second opening exposing one of the second source / drain regions of the bottom transistor; after etching the second dielectric layer, selectively forming a second metal silicide on one of the second source / drain regions, wherein the second metal silicide is made of a material different from the first metal silicide. In some embodiments, etching the second dielectric layer is performed until the front side contact is exposed. In some embodiments, the method further includes selectively forming a second metal capping structure on the second metal silicide but not on the second dielectric layer. In some embodiments, the method further includes forming a liner lining the first opening after selectively forming the first metal capping structure and before forming the front side contact, the liner having the same metal element as the front side contact.

[0121] In some embodiments, a method includes the following steps: forming a first semiconductive nanostructure and a second semiconductive nanostructure arranged in a vertical direction with respect to the first semiconductive nanostructure; forming a plurality of first epitaxial structures on opposite sides of the first semiconductive nanostructure, and forming a plurality of second epitaxial structures on opposite sides of the second semiconductive nanostructure; forming a first gate surrounding the first semiconductive nanostructure and a second gate surrounding the second semiconductive nanostructure; selectively forming a first metal silicide layer on one of the first epitaxial structures, and selectively forming a second metal silicide layer on one of the second epitaxial structures; selectively forming a first fluorine-free metal layer on the first metal silicide layer, and selectively forming a second fluorine-free metal layer on the second metal silicide layer. In some embodiments, the first epitaxial structure includes SiGe, and the second epitaxial structure includes SiP. In some embodiments, the second metal silicide layer has a different metal element from the first metal silicide layer. In some embodiments, the first metal silicide layer includes MoSiGe, and the second metal silicide layer includes TiSi. In some embodiments, the second fluorine-free metal layer is made of the same material as the first fluorine-free metal layer.

[0122] In some embodiments, a semiconductor structure includes a first transistor, a second transistor, a first metal silicide layer, a first fluorine-free tungsten layer, and a first tungsten contact. The first transistor includes a plurality of first semiconductor slices; a first gate structure surrounding each of the first semiconductor slices; and a plurality of first source / drain structures located on either side of each of the first semiconductor slices. The second transistor is located above the first transistor. The second transistor includes a plurality of second semiconductor slices; a second gate structure surrounding each of the second semiconductor slices; and a plurality of second source / drain structures located on either side of each of the second semiconductor slices. The first metal silicide layer is located on one of the first source / drain structures. The first fluorine-free tungsten layer is located on the first metal silicide layer. The first tungsten contact is located on the first fluorine-free tungsten layer. In some embodiments, the semiconductor structure further includes a tungsten liner lining the sidewalls of the first tungsten contact. In some embodiments, there is no metal nitride between the first tungsten contact and one of the first source / drain structures. In some embodiments, the semiconductor structure further includes a second metal silicide layer, a second fluorine-free tungsten layer, and a second tungsten contact. The second metal silicide layer is located on one of the second source / drain structures. The second fluorine-free tungsten layer is located on the second metal silicide layer. The second tungsten contact is located on the second fluorine-free tungsten layer. In some embodiments, the first tungsten contact has a first cross-sectional profile and a second cross-sectional profile located between the first cross-sectional profile and the first fluorine-free tungsten layer, the second tungsten contact has a third cross-sectional profile and a fourth cross-sectional profile located between the third cross-sectional profile and the second fluorine-free tungsten layer, the first cross-sectional profile has a width wider than the second cross-sectional profile, and the third cross-sectional profile has a width wider than the fourth cross-sectional profile.

[0123] In some embodiments, a semiconductor structure includes a bottom transistor, a top transistor, a first metal silicide, a first metal capping structure, and a front side contact. The top transistor is located above the bottom transistor, and the top transistor includes a first channel layer, a first gate structure located around the first channel layer, and a plurality of first source / drain regions located on a plurality of opposite sides of the first channel layer. A first metal silicide is located on one of the plurality of first source / drain regions. The first metal capping structure is located on the first metal silicide. The front side contact is located on the first metal capping structure. In some embodiments, the bottom transistor includes a second channel layer, a second gate structure located around the second channel layer, and a plurality of second source / drain regions located on a plurality of opposite sides of the second channel layer. The semiconductor structure further includes a second metal silicide. The second metal silicide is located on one of the plurality of second source / drain regions. In some embodiments, the semiconductor structure further includes a second metal capping structure. The second metal capping structure is located on the second metal silicide.

[0124] In some embodiments, a semiconductor structure includes a first semiconductive nanostructure, a second semiconductive nanostructure, a plurality of first epitaxial structures, a plurality of second epitaxial structures, a first gate, a second gate, a first metal silicide layer, a second metal silicide layer, a first fluorine-free metal layer, and a second fluorine-free metal layer. The second semiconductive nanostructure is arranged in a vertical direction with the first semiconductive nanostructure. The plurality of first epitaxial structures are located on a plurality of opposite sides of the first semiconductive nanostructure. The plurality of second epitaxial structures are located on a plurality of opposite sides of the second semiconductive nanostructure. The first gate surrounds the first semiconductive nanostructure. The second gate surrounds the second semiconductive nanostructure. The first metal silicide layer is located on one of the plurality of first epitaxial structures. The second metal silicide layer is located on one of the plurality of second epitaxial structures. The first fluorine-free metal layer is located on the first metal silicide layer. The second fluorine-free metal layer is located on the second metal silicide layer. In some embodiments, the semiconductor structure further includes a tungsten contact. The tungsten contact is located on the first fluorine-free metal layer. In some embodiments, the semiconductor structure further includes a front side contact. The front side contact is located on the second fluorine-free metal layer.

[0125] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: include: A first transistor comprising: a plurality of first semiconductor wafers; a first gate structure surrounding each of the plurality of first semiconductor slices; and a plurality of first source / drain structures located on either side of each of the plurality of first semiconductor slices; a second transistor, located above the first transistor, the second transistor comprising: a plurality of second semiconductor wafers; a second gate structure surrounding each of the plurality of second semiconductor slices; and a plurality of second source / drain structures located on either side of each of the plurality of second semiconductor sheets; a first metal silicide layer located on one of the plurality of first source / drain structures; a first fluorine-free tungsten layer located on the first metal silicide layer; and A first tungsten contact is located on the first fluorine-free tungsten layer.

2. The semiconductor structure according to claim 1, wherein: Further including: A tungsten liner lines a side wall of the first tungsten contact.

3. The semiconductor structure according to claim 1, wherein: Further including: a second metal silicide layer located on one of the plurality of second source / drain structures; a second fluorine-free tungsten layer located on the second metal silicide layer; and A second tungsten contact is located on the second fluorine-free tungsten layer.

4. The semiconductor structure according to claim 3, characterized in that The first tungsten contact has a first cross-sectional profile and a second cross-sectional profile between the first cross-sectional profile and the first fluorine-free tungsten layer, the second tungsten contact has a third cross-sectional profile and a fourth cross-sectional profile between the third cross-sectional profile and the second fluorine-free tungsten layer, the first cross-sectional profile has a width wider than the second cross-sectional profile, and the third cross-sectional profile has a width wider than the fourth cross-sectional profile.

5. A semiconductor structure, characterized in that: include: A bottom layer transistor; a top transistor located above the bottom transistor, the top transistor comprising a first channel layer, a first gate structure located around the first channel layer, and a plurality of first source / drain regions located on a plurality of opposite sides of the first channel layer; a first metal silicide disposed on one of the plurality of first source / drain regions; a first metal capping structure located on the first metal silicide; and A front side contact is located on the first metal capping structure.

6. The semiconductor structure according to claim 5, characterized in that The bottom transistor includes a second channel layer, a second gate structure located around the second channel layer, and a plurality of second source / drain regions located on a plurality of opposite sides of the second channel layer. The semiconductor structure further includes: A second metal silicide is located on one of the second source / drain regions.

7. The semiconductor structure according to claim 6, wherein: Further including: A second metal capping structure is located on the second metal silicide.

8. A semiconductor structure, characterized in that: include: a first semiconductive nanostructure; a second semiconductive nanostructure, arranged in a vertical direction with respect to the first semiconductive nanostructure; a plurality of first epitaxial structures disposed on a plurality of opposite sides of the first semiconductive nanostructure; a plurality of second epitaxial structures disposed on opposite sides of the second semiconductive nanostructure; a first gate surrounding the first semiconductive nanostructure; a second gate surrounding the second semiconductive nanostructure; a first metal silicide layer located on one of the plurality of first epitaxial structures; a second metal silicide layer located on one of the plurality of second epitaxial structures; a first fluorine-free metal layer located on the first metal silicide layer; and A second fluorine-free metal layer is located on the second metal silicide layer.

9. The semiconductor structure according to claim 8, characterized in that Further including: A tungsten contact is located on the first fluorine-free metal layer.

10. The semiconductor structure according to claim 8, wherein: Further including: A front side contact is located on the second fluorine-free metal layer.

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