Photoelectric device based on multi-surface reflection

Abstract

The utility model relates to a photoelectric device based on multi-surface reflection, which comprises a driving wafer and a pixel unit, and the driving wafer comprises an anode contact. Each pixel unit comprises a pixel main body and an outer edge wall body, the outer edge wall body is arranged on the side wall of the pixel main body, the outer edge wall body comprises a side surface insulating layer and a side surface reflecting metal layer, one side of the pixel main body is provided with an N-type semiconductor layer, and the other side of the pixel main body is provided with a P-type semiconductor layer; a transparent conductive film layer and a bottom surface reflection metal layer are formed between the P-type semiconductor layer and the driving wafer; the N-type semiconductor layer and the P-type semiconductor layer in each pixel unit are insulated through a side insulating layer, and the N-type semiconductor layers in all the pixel units are connected through a common cathode. According to the utility model, the phenomena of short circuit and electric leakage can be effectively avoided, meanwhile, each pixel unit can achieve a multi-surface reflection effect, and the optical intensity of the LED photoelectric device is increased.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a photoelectric device based on multi-faceted reflection. Background Art

[0002] Existing LED optoelectronic devices generally only have a single-sided reflector, and the reflector is generally located at the bottom of the pixel light-emitting unit, while the LED's emitted light source is facing all directions. This single-sided reflection method only utilizes bottom surface reflection. The luminous angle of this single-sided reflector is generally above 110°. The light collection rate and utilization rate of the pixel unit are low, which is not conducive to improving the overall optical efficiency and cannot meet the use requirements. For example, for some projection fields, the light source is required to have a high degree of collimation and a small luminous angle to improve the utilization rate of the light source, thereby ensuring the brightness of the LED optoelectronic device, but the existing LED optoelectronic devices cannot meet the requirements. In addition, the internal electrical isolation effect of the pixel unit of the existing LED optoelectronic device is poor, which is easy to cause short circuit leakage, thereby causing the optoelectronic device to fail, and the reliability of the LED optoelectronic device cannot be guaranteed.

[0003] Therefore, the existing LED optoelectronic devices cannot effectively guarantee good optical intensity and the pixel unit is prone to leakage failure due to poor electrical isolation, thereby affecting the reliability of the LED optoelectronic devices. Utility Model Content

[0004] Therefore, the technical problem to be solved by the present invention is to overcome the defects in the prior art that LED optoelectronic devices cannot effectively guarantee good optical intensity and pixel units are prone to leakage failure, so as to improve the reliability of LED optoelectronic devices.

[0005] In order to solve the above technical problems, the utility model provides a photoelectric device based on multi-faceted reflection, comprising:

[0006] A driving wafer, wherein the driving wafer includes an anode contact;

[0007] A pixel unit, wherein the pixel unit is disposed on the driving wafer and corresponds to the anode contact, the pixel unit comprises a pixel body and an outer edge wall, the outer edge wall is disposed on a side wall of the pixel body, the outer edge wall comprises a side insulating layer and a side reflective metal layer, the inner wall of the side insulating layer is in contact with the side wall of the pixel body, and the outer wall of the side insulating layer is in contact with the side reflective metal layer;

[0008] An N-type semiconductor layer is disposed on a side of the pixel body away from the driving wafer, and a P-type semiconductor layer is disposed on a side close to the driving wafer, a transparent conductive film layer is formed between the P-type semiconductor layer and the driving wafer, the P-type semiconductor layer is electrically connected to a corresponding anode contact on the driving wafer through the transparent conductive film layer, and a bottom reflective metal layer is formed between the transparent conductive film layer and the driving wafer;

[0009] The N-type semiconductor layer and the P-type semiconductor layer in each of the pixel units are insulated from each other by the side insulating layer, and the N-type semiconductor layers in all the pixel units are connected via a common cathode.

[0010] In one embodiment of the utility model, a bonding layer is further arranged between the bottom reflective metal layer and the driving wafer, and the bonding layer is a conductive layer. The bonding layer includes a first bonding metal layer and a second bonding metal layer. The first bonding metal layer is electrically connected to the bottom reflective metal layer, and the second bonding metal layer is electrically connected to the anode contact.

[0011] In one embodiment of the present invention, the P-type semiconductor layer and the bottom reflective metal layer are both in direct contact with the transparent conductive film layer to be electrically connected.

[0012] In one embodiment of the present utility model, a bottom reflective medium layer is further provided between the transparent conductive film layer and the bottom reflective metal layer, and the bottom reflective medium layer is a non-conductive layer.

[0013] In one embodiment of the present invention, the pixel unit further includes a side metal fence, which is located outside the side reflective metal layer, and the transparent conductive film layer and the bottom reflective metal layer are electrically connected via the side metal fence.

[0014] In one embodiment of the present invention, the refractive index of the bottom reflective medium layer is smaller than the refractive index of the transparent conductive film layer.

[0015] In one embodiment of the present invention, the transparent conductive film layer is one or more of an ITO film layer, a ZnO film layer and an IZO film layer.

[0016] In one embodiment of the present invention, a step portion is formed at one end of the side insulating layer close to the transparent conductive film layer, and the side reflective metal is located on the step portion.

[0017] In one embodiment of the present invention, a metal grid is further arranged between two adjacent pixel units, and each of the metal grids is electrically connected to the common cathode.

[0018] In one embodiment of the present invention, each pixel unit is further connected to a microlens.

[0019] The above technical solution of the utility model has the following advantages compared with the prior art:

[0020] The optoelectronic device based on multi-faceted reflection described in the utility model can effectively avoid short circuit leakage between the N-type semiconductor layer and the P-type semiconductor layer of the pixel unit by arranging an outer edge wall at the side wall of the pixel body, thus effectively avoiding leakage risk and crosstalk between pixels, and can better ensure the reliability of the use of the LED optoelectronic device; at the same time, each pixel unit can realize multi-faceted reflection of "side surface + bottom surface", thereby achieving a multi-faceted reflection effect, improving the light collection rate and utilization rate, and increasing the optical strength and brightness performance of the LED optoelectronic device. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to make the content of the utility model more clearly understood, the utility model is further described in detail below based on specific embodiments of the utility model in combination with the accompanying drawings.

[0022] Figure 1 This is a schematic structural diagram of an implementation of a multi-faceted reflection-based optoelectronic device of the utility model (the common cathode is omitted);

[0023] Figure 2 It is a structural schematic diagram of another embodiment of the photovoltaic device based on multi-faceted reflection of the utility model (the common cathode is omitted);

[0024] Figure 3 It is a structural schematic diagram of the driving wafer in the utility model;

[0025] Figure 4 It is a schematic structural diagram of an implementation mode of the compound semiconductor in the utility model;

[0026] Figure 5 It is a structural schematic diagram of another embodiment of the compound semiconductor in the utility model;

[0027] Figure 6 is to use Figure 4 Schematic diagram of preparing optoelectronic devices using compound semiconductors shown;

[0028] Figure 7 is to use Figure 5 Schematic diagram of preparing optoelectronic devices using compound semiconductors shown;

[0029] Figure 8 It is a schematic diagram of an implementation method of preparing a common cathode and a microlens of the optoelectronic device of the utility model;

[0030] Fig. 9 It is a schematic diagram of another implementation method of preparing a common cathode and a microlens of the optoelectronic device of the utility model;

[0031] Fig.10 It is a schematic diagram of a third implementation mode of preparing a common cathode and a microlens of an optoelectronic device of the utility model;

[0032] Description of the Figures in the Specification:

[0033] 10. driving wafer; 101. anode contact;

[0034] 20, pixel unit; 201, pixel body; 2011, N-type semiconductor layer; 2012, active layer; 2013, P-type semiconductor layer; 202, outer wall; 2021, side insulating layer; 20211, step portion; 2022, side reflective metal layer; 2023, side metal fence; 203, transparent conductive film layer; 204, bottom reflective metal layer; 205, bottom reflective dielectric layer;

[0035] 30, bonding layer; 301, first bonding metal layer; 302, second bonding metal layer;

[0036] 40. Common cathode;

[0037] 50. Compound semiconductor; 501. Substrate;

[0038] 60. Metal grid;

[0039] 70. Microlens; DETAILED DESCRIPTION

[0040] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments so that those skilled in the art can better understand the present invention and implement it, but the embodiments are not intended to limit the present invention. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and is by no means intended to limit the present disclosure and its application or use.

[0041] In the description of the present utility model, it should be understood that the terms "vertical", "upper", "lower", "top", "side", "inner", "outer" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present utility model. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present utility model, unless otherwise specified, "multiple" means two or more.

[0042] This embodiment provides an optoelectronic device based on multi-faceted reflection, so that the LED optoelectronic device has better optical strength and effectively avoids leakage failure of pixel units, thereby improving the reliability of the LED optoelectronic device.

[0043] The following will be combined with the attached Figure 1-10 , the structure of this embodiment is further described.

[0044] Embodiment 1

[0045] See also Figure 1 , this embodiment discloses an optoelectronic device based on multi-faceted reflection, including a driving wafer 10 and a pixel unit 20, wherein the driving wafer 10 is used for driving and controlling light emission of the pixel unit 20;

[0046] The driving wafer 10 includes an anode contact 101 for realizing an anode connection with the pixel unit 20;

[0047] The pixel unit 20 is disposed on the driving wafer 10 and corresponds to the anode contact 101;

[0048] The pixel unit 20 includes a pixel body 201 and an outer edge wall 202, the outer edge wall 202 is arranged on the side wall of the pixel body 201, the outer edge wall 202 includes a side insulating layer 2021 and a side reflective metal layer 2022, the inner wall of the side insulating layer 2021 is attached to the side wall of the pixel body 201, so that there is no gap between the two, and the outer wall of the side insulating layer 2021 is attached to the side reflective metal layer 2022, so that there is no gap between the two;

[0049] An N-type semiconductor layer 2011 is disposed on a side of the pixel body 201 away from the driving wafer 10 , and a P-type semiconductor layer 2013 is disposed on a side close to the driving wafer 10 ;

[0050] A transparent conductive film layer 203 is formed between the P-type semiconductor layer 2013 and the driving wafer 10; the P-type semiconductor layer 2013 is electrically connected to the corresponding anode contact 101 on the driving wafer 10 through the transparent conductive film layer 203;

[0051] A bottom reflective metal layer 204 is formed between the transparent conductive film layer 203 and the driving wafer 10 to achieve bottom reflection;

[0052] The N-type semiconductor layer 2011 and the P-type semiconductor layer 2013 in each pixel unit 20 are insulated from each other by a side insulating layer 2021 , and the N-type semiconductor layers 2011 in all pixel units 20 are connected via a common cathode 40 .

[0053] In the above structure, a side reflector is formed by the side insulating layer 2021 and the side reflective metal layer 2022, and a bottom reflector is formed by the transparent conductive film layer 203 and the bottom reflective metal layer 204, thereby forming a multi-faceted reflective cavity, so that the light emitted by the pixel unit 20 can be reflected not only from the bottom surface but also from the side, thereby achieving a multi-faceted reflection effect, improving the light collection rate and utilization rate, and facilitating the improvement of the overall optical efficiency, and also greatly improving the brightness of the pixel unit 20 and the collimation of the light, while improving the performance and further constraining the divergence angle, thereby improving the optical intensity and brightness of the pixel unit 20 as a whole.

[0054] Furthermore, the side insulating layer 2021 and the side reflective metal layer 2022 can be used to form an omnidirectional reflector - an ODR (Omnidirectional Refl ector) reflector, and the transparent conductive film layer 203 and the bottom reflective metal layer 204 can also form an ODR reflector to better reduce reflection loss and improve reflectivity, thereby better improving the light output brightness and intensity of the pixel unit 20.

[0055] In addition, the above-mentioned pixel unit 20 structure, by setting an outer edge wall 202 at the side wall of the pixel body 201, makes the N-type semiconductor layer 2011 and the P-type semiconductor layer 2013 in each pixel unit 20 insulated from each other by the side insulating layer 2021, which can effectively avoid the short circuit leakage phenomenon between the N-type semiconductor layer 2011 and the P-type semiconductor layer 2013, thereby better ensuring the reliability of the pixel unit 20 structure.

[0056] An active layer 2012 is generally provided between the N-type semiconductor layer 2011 and the P-type semiconductor layer 2013 of each pixel body 201 for emitting light; and the driving wafer 10 may be a CMOS integrated circuit.

[0057] In addition, the pixel units and the anode contacts may correspond one to one, or multiple anode contacts may correspond to one pixel unit.

[0058] Taking the field of Micro-LED as an example, some compound materials involved in this embodiment are shown in Table 1 below. In some practical applications, the film layer of the compound will be more complicated, or there will be cross-use of materials, mainly including P-type semiconductor layer materials, N-type semiconductor layer materials and an active layer (MQW quantum well) sandwiched between the two:

[0059] Table 1. Materials of various compound films

[0060] Layer Name Material Material Material Material Material Material Material P-type semiconductor layer GaP GaAs GaAs GaAs AlGaN GaN GaN MQW Active Quantum Well AlGaInP AlGaInP InGaAs AlGaAs InGaN InGaN InGaN N-type semiconductor layer GaAs AlGaAs AlGaAs GaAs GaN GaN GaN

[0061] In one embodiment, a bonding layer 30 is further provided between the bottom reflective metal layer 204 and the driving wafer 10. The bonding layer 30 is a conductive layer for realizing electrical conduction between the P-type semiconductor layer 2013 and the driving wafer 10. The bonding layer 30 includes a first bonding metal layer 301 and a second bonding metal layer 302. The bottom reflective metal layer 204 is electrically connected to the first bonding metal layer 301, and the second bonding metal layer 302 is electrically connected to the anode contact 101.

[0062] Among them, the P-type semiconductor layer 2013 and the bottom reflective metal layer 204 are both in direct contact with the transparent conductive film layer 203 and electrically connected. At this time, the P-type semiconductor layer 2013 is directly electrically connected through the transparent conductive film layer 203, the bottom reflective metal layer 204 and the bonding layer 30 in sequence without the need to set up an external conductive structure.

[0063] In one embodiment, the transparent conductive film layer 203 on the bottom surface is one or more of an ITO (tin-doped indium oxide) film layer, a ZnO (zinc oxide) film layer, or an IZO (indium zinc oxide) film layer.

[0064] The transparent conductive film layer 203 on the bottom surface can directly serve as a P-type ohmic contact layer of the P-type semiconductor layer 2013 .

[0065] For example, a Si-based blue light indium gallium nitride (InGaN) compound is selected, and an ITO film is coated on the surface of the P-type semiconductor layer by evaporation, sputtering, etc. The thickness of the ITO film layer is 70nm, and an ohmic contact is formed by high-temperature annealing, thereby forming a P-type ohmic contact layer. The specific film thickness and contact forming conditions can be adjusted and changed according to needs, and are not limited here.

[0066] In one embodiment, the thickness of the side insulating layer 2021 is greater than the thickness of the side reflective metal layer 2022 to better ensure the insulating effect of the side insulating layer.

[0067] For example, the side insulating layer 2021 is a silicon dioxide layer with a thickness of 300 nm, and the side reflective metal layer 2022 is an aluminum layer with a thickness of 100 nm.

[0068] In one embodiment, if Figure 1 As shown, a step portion 20211 is formed at one end of the side insulating layer 2021 close to the transparent conductive film layer 203 , and the side reflective metal is located on the step portion 20211 .

[0069] In another embodiment, Figure 2 As shown, the end of the side insulating layer 2021 close to the transparent conductive film layer 203 may not have the step portion 20211 .

[0070] In actual working conditions, a structure with a step portion 20211 or a structure without a step portion 20211 can be obtained according to the actual preparation process.

[0071] In one embodiment, if Figure 8-Figure 10 As shown, a metal grid 60 is further disposed between two adjacent pixel units 20 , and each metal grid 60 is electrically connected to the common cathode 40 to enhance the current expansion of the common cathode 40 , further enhance the light intensity and convergent luminous angle, and better prevent pixel crosstalk.

[0072] The metal grid 60 can be realized by patterned evaporation or patterned etching after coating. For example, aluminum metal can be used as the metal grid.

[0073] In one embodiment, if Figure 8-Figure 10 As shown, a micro lens 70 is also provided on each pixel unit 20. The lens may be hemispherical or semi-rugby. The focus of the lens may be the surface where the common cathode 40 is located, or the surface where the metal grid is located.

[0074] like Figure 6 As shown, this embodiment also discloses a method for preparing an optoelectronic device based on multi-faceted reflection, comprising:

[0075] 1) If Figure 3 As shown, a driving wafer 10 is first prepared, so that the driving wafer 10 includes an anode contact 101;

[0076] 2) Connecting the compound semiconductor and the driving wafer 10, and processing the compound semiconductor 50 to form a pixel unit 20 corresponding to the anode contact 101; wherein the structure of the compound semiconductor 50 is referred to in Figure 4 ;

[0077] The pixel unit 20 comprises a pixel body 201 and an outer edge wall 202, wherein the outer edge wall 202 is disposed on the side wall of the pixel body 201, and the outer edge wall 202 comprises a side insulating layer 2021 and a side reflective metal layer 2022, wherein the inner wall of the side insulating layer 2021 is in contact with the side wall of the pixel body 201, and the outer wall of the side insulating layer 2021 is in contact with the side reflective metal layer 2022;

[0078] An N-type semiconductor layer 2011 is disposed on the side of the pixel body 201 away from the driving wafer 10, and a P-type semiconductor layer 2013 is disposed on the side close to the driving wafer 10; a transparent conductive film layer 203 is formed between the P-type semiconductor layer 2013 and the driving wafer 10, and a bottom reflective metal layer 204 is formed between the transparent conductive film layer 203 and the driving wafer 10;

[0079] The P-type semiconductor layer 2013 is electrically connected to the corresponding anode contact 101 on the driving wafer 10 through the transparent conductive film layer 203, and the N-type semiconductor layer 2011 and the P-type semiconductor layer 2013 in each pixel unit 20 are insulated from each other by a side insulating layer 2021;

[0080] 3) Finally, the N-type semiconductor layers 2011 in all pixel units 20 are connected via the common cathode 40 .

[0081] In one embodiment, the compound semiconductor and the driver wafer 10 are bonded and connected via a bonding layer 30 , the bonding layer 30 is a conductive layer, and the bonding layer 30 includes a first bonding metal layer 301 and a second bonding metal layer 302 ;

[0082] Before bonding, it is necessary to deposit bonding metal on the bottom reflective metal of the compound semiconductor 50 to form a first bonding metal layer 301, and also deposit bonding metal on the driving wafer 10 to form a second bonding metal layer 302, so that the anode contact 101 and the second bonding metal layer 302 are electrically connected, and then the compound semiconductor 50 is inverted so that the first bonding metal layer 301 and the second bonding metal layer 302 are hot-pressed and bonded together to form a bonding layer 30.

[0083] The above-mentioned bonding metal material can be one or more of a Ni+Sn combination, an Au+Sn combination, a Cu+Sn combination, an Au+In combination, an Au+Au combination, an Al+Al combination, a Cu+Cu combination, an ITO+ITO combination, etc.

[0084] Compound semiconductors generally refer to compounds formed by two or more elements, including crystalline inorganic compounds (such as II IV and III-VI compound semiconductors) and oxide semiconductors. The compound semiconductors involved in this application are mainly LED epitaxial materials, such as InGaN ternary material system or AlGaInP quaternary material system.

[0085] In one embodiment, if Figure 4 As shown, the compound semiconductor 50 includes a substrate 501, and an N-type semiconductor layer 2011, a P-type semiconductor layer 2013, a transparent conductive film layer 203, a bottom reflective metal layer 204 and a first bonding metal layer 301 formed in sequence in a direction away from the substrate 501, and an active layer 2012 is arranged between the N-type semiconductor layer 2011 and the P-type semiconductor layer 2013; a second bonding metal layer 302 is arranged on the driving wafer 10, and the anode contact 101 and the second bonding metal layer 302 are electrically connected;

[0086] Then, the method of connecting the compound semiconductor and the driving wafer 10 and processing the compound semiconductor 50 to form the pixel unit 20 corresponding to the anode contact 101 includes:

[0087] Step S1), as Figure 6 In the middle stage a, the first bonding metal layer 301 of the compound semiconductor 50 and the second bonding metal layer 302 of the driving wafer 10 are bonded by thermocompression bonding to achieve bonding connection;

[0088] Step S2), removing the substrate 501 of the compound semiconductor 50;

[0089] The substrate removal method uses different process methods according to different substrate materials, such as laser stripping to remove sapphire substrates, HNA wet etching to remove silicon substrates, etc. After removing the substrate, the N-type semiconductor can be exposed on the surface of the wafer, which meets the conditions for pixel preparation. If necessary, an N-ohmic contact layer can be prepared on the N-type semiconductor. The ohmic contact layer can be a transparent conductive layer or a metal layer, such as a single layer or a stack of Au, Ge, Al, etc.

[0090] The above-mentioned substrate can be gallium nitride (GaN), silicon (Si), silicon carbide (SiC), sapphire (Sapphire), gallium arsenide (GaAs), indium phosphide (InP), etc.

[0091] Step S3), as Figure 6 In the middle b stage, the compound semiconductor 50 is etched by a first etching method, and the transparent conductive film layer 203 is used as an etching cut-off layer during etching, so as to obtain a plurality of pixel bodies 201 corresponding to the anode contacts 101;

[0092] The first etching method may be photolithography, dry etching or wet etching.

[0093] Step S4), as Figure 6 In the middle CD stage, an outer edge wall 202 is formed at the side wall of each pixel body 201, and the outer edge wall 202 includes a side insulating layer 2021 and a side reflective metal layer 2022. The side insulating layer 2021 is deposited on the side wall of the pixel body 201, and the side reflective metal layer 2022 is deposited on the outer wall of the side insulating layer 2021;

[0094] Step S5), as Figure 6 In the middle e stage, the bonding layer 30 between the outer edge walls 202 of two adjacent pixel bodies 201 and the material layer above the bonding layer 30 are removed by etching, so that the pixel bodies 201 are electrically isolated from each other.

[0095] It can be understood that the so-called removal of "material layers above the bonding layer 30" refers to the removal of all material layers on the upper part of the bonding layer 30 between the outer edge walls 202. For example, if the upper part of the bonding layer 30 between the outer edge walls 202 also has a bottom metal reflective layer and a transparent conductive film layer 203, they are removed together. If a bottom reflective medium layer 205 is also provided between the bottom metal reflective layer and the transparent conductive film layer 203, the three in this area are removed together.

[0096] Among them, the etching method in step S5) can adopt IBE (ion beam etching, Ion Beam Etching) etching method.

[0097] Finally, Figure 6 The common cathode 40 is prepared as shown in stage f.

[0098] Furthermore, in step S4), when forming the outer edge wall 202 at the side wall of each pixel body 201, an overall etching method or a layered etching method can be adopted:

[0099] See also Figure 6 In the middle CD stage, the overall etching method is: depositing a side insulating layer 2021 on the outside of the pixel body 201, and then depositing a side reflective metal layer 2022 on the outside of the side insulating layer 2021. After all the deposition is completed, the overall structure composed of the side insulating layer 2021 and the side reflective metal layer 2022 is etched by dry etching. After etching, only the side insulating layer 2021 and the side reflective metal layer 2022 located at the side wall of the pixel body 201 are retained;

[0100] In the pixel unit 20 prepared by the overall etching method, a step portion 20211 is formed at one end of the side insulating layer 2021 close to the transparent conductive film layer 203 , and the side reflective metal is located on the step portion 20211 .

[0101] See also Figure 7 In the middle cf stage, the layered etching method is: after depositing the side insulating layer 2021 on the outside of the pixel body 201, the side insulating layer 2021 is first etched by dry etching, and only the side insulating layer 2021 located at the side wall of the pixel body 201 is retained after etching, and then the side reflective metal layer 2022 is deposited on the outside of the side insulating layer 2021. After the deposition is completed, the side reflective metal layer 2022 is etched by dry etching, and only the side reflective metal layer 2022 located at the side wall of the pixel body 201 is retained after etching.

[0102] In the pixel unit 20 prepared by layered etching, no step portion is formed on the end of the side insulating layer 2021 close to the transparent conductive film layer 203 .

[0103] The above-mentioned method for preparing the outer edge wall of the pixel unit does not require a photolithography machine during preparation, but is implemented by dry etching. This can get rid of the need for more advanced photolithography machines and does not require an exposure process. It avoids the defects of graphic failure, large overlay offset, and high production cost caused by the use of photolithography machines for graphic etching in the prior art. At the same time, it can also effectively ensure the preparation accuracy, achieve in-situ or self-alignment type accuracy, and achieve sub-micron accuracy using micron-level equipment technology.

[0104] In one embodiment, the side insulating layer 2021 includes one or more of silicon dioxide, silicon nitride, aluminum oxide, titanium pentoxide, and niobium pentoxide.

[0105] In one embodiment, the bottom reflective metal layer 204 and the side reflective metal layer 2022 both include one or more of silver, aluminum, aluminum-copper alloy, aluminum-nickel alloy, gold, rhodium, and platinum.

[0106] In one embodiment, if Figure 8 , Fig. 9 or Fig.10 As shown, when the N-type semiconductor layers 2011 in all pixel units 20 are connected through a common cathode 40, a transparent conductive film can be deposited on the N-type semiconductor side of all pixel units 20 by sputtering, evaporation, etc. to form a common cathode 40. The film layer can be a combination of one or more of an ITO (tin-doped indium oxide) film, an AZO (aluminum-doped zinc oxide) film, an ATO (antimony-doped tin oxide) film, and a FTO (fluorine-doped tin dioxide) film, or a metal-doped ITO is formed by annealing after thinly plating Al, Au, and Ag on the surface of the ITO to enhance the current transmission capacity of the common cathode 40 layer.

[0107] Specifically, Figure 8As shown in stage a, the surface can be flattened by CMP to expose the N-type semiconductor layer, and then a common cathode deposition can be performed by sputtering, evaporation, etc.; or as shown in stage a Fig.10 As shown in stage a, a graphic etching method can also be used to expose the N-type semiconductor layer, and then a common cathode deposition can be performed by sputtering, evaporation, etc.: or in the stage of graphic etching to expose the N-type semiconductor layer, the dielectric layer between the pixels is also graphic etched. The etching depth of the dielectric layer can be the same as the etching depth of the exposed N-type semiconductor layer, or it can be etched separately to a deeper depth. After etching, the metal is filled in the etched groove to prepare the common cathode 40.

[0108] In one embodiment, during preparation, after the N-type semiconductor layers 2011 in all pixel units 20 are connected via the common cathode 40 , a metal grid 60 is also electrically connected to the common cathode 40 .

[0109] Embodiment 2

[0110] like Figure 2 As shown, the main difference between this embodiment and the first embodiment is that a bottom reflective medium layer 205 is further provided between the transparent conductive film layer 203 and the bottom reflective metal layer 204, and the bottom reflective medium layer 205 is a non-conductive layer, so as to enhance the bottom reflection effect through the bottom reflective medium layer 205.

[0111] Furthermore, the bottom reflective medium layer 205 includes one or more of silicon dioxide, silicon nitride, aluminum oxide, titanium pentoxide and niobium pentoxide.

[0112] The above structure can form an ODR reflector through the transparent conductive film layer 203 , the bottom reflective medium layer 205 and the bottom reflective metal layer 204 , or can form an ODR reflector through the bottom reflective medium layer 205 and the bottom reflective metal layer 204 .

[0113] In one embodiment, the refractive index of the bottom reflective medium layer 205 is smaller than the refractive index of the transparent conductive film layer 203 to enhance the ODR reflection effect.

[0114] In one embodiment, the pixel unit 20 also includes a side metal fence 2023, which is located outside the side reflective metal layer 2022. The transparent conductive film layer 203 and the bottom reflective metal layer 204 are electrically connected through the side metal fence 2023, thereby realizing the anode connection between the P-type semiconductor layer 2013 and the bonding layer 30.

[0115] like Figure 7 As shown, this embodiment also discloses a method for preparing an optoelectronic device based on multi-faceted reflection. The main difference between this method and the method of the first embodiment is that the structure of the compound semiconductor 50 is shown in FIG. Figure 5 When the compound semiconductor and the driving wafer 10 are connected and the compound semiconductor 50 is processed to form a pixel unit 20 corresponding to the anode contact 101, when the bonding layer 30 between the outer edge wall 202 of two adjacent pixel bodies 201 and the material layer above the bonding layer are etched away in step S5), a side metal fence 2023 needs to be formed. The side metal fence 2023 is located outside the side reflective metal layer 2022, so that the transparent conductive film layer 203 and the bottom reflective metal layer 204 are electrically connected through the side metal fence 2023.

[0116] The metal fence 2023 may be a fence formed by IBE etching, so that the fence can be utilized without being eliminated, which is beneficial to simplifying the process and improving process stability, and is also beneficial to improving product yield and reducing costs; the metal fence may also be a fence formed by other methods.

[0117] The optoelectronic devices based on multi-faceted reflection and the preparation methods thereof in the above-mentioned embodiments introduce a side insulating layer and a side reflective metal layer to form a side reflector, and a bottom reflector is formed by a transparent conductive film layer and a bottom reflective metal layer, thereby forming a multi-faceted reflective cavity, thereby achieving a multi-faceted reflection effect, improving the light collection rate and utilization rate, and increasing the brightness performance of the device; in addition, it can also well avoid the risk of leakage and crosstalk between pixels, and is also beneficial to improving the pixel density of the LED device.

[0118] All the above-mentioned optional technical solutions can be combined in any way to form optional embodiments of the present invention, that is, any multiple embodiments can be combined to meet the needs of different application scenarios. They are all within the protection scope of this application and will not be described one by one here.

[0119] It should be noted that the above embodiments are merely examples for the purpose of clear explanation and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the invention.

Claims

1. An optoelectronic device based on multi-faceted reflection, characterized in that: include, A driving wafer, wherein the driving wafer includes an anode contact; A pixel unit, wherein the pixel unit is disposed on the driving wafer and corresponds to the anode contact, the pixel unit comprises a pixel body and an outer edge wall, the outer edge wall is disposed on a side wall of the pixel body, the outer edge wall comprises a side insulating layer and a side reflective metal layer, the inner wall of the side insulating layer is in contact with the side wall of the pixel body, and the outer wall of the side insulating layer is in contact with the side reflective metal layer; An N-type semiconductor layer is disposed on a side of the pixel body away from the driving wafer, and a P-type semiconductor layer is disposed on a side close to the driving wafer, a transparent conductive film layer is formed between the P-type semiconductor layer and the driving wafer, the P-type semiconductor layer is electrically connected to a corresponding anode contact on the driving wafer through the transparent conductive film layer, and a bottom reflective metal layer is formed between the transparent conductive film layer and the driving wafer; The N-type semiconductor layer and the P-type semiconductor layer in each of the pixel units are insulated from each other by the side insulating layer, and the N-type semiconductor layers in all the pixel units are connected via a common cathode.

2. The optoelectronic device based on multi-faceted reflection according to claim 1, characterized in that: A bonding layer is also arranged between the bottom reflective metal layer and the driving wafer. The bonding layer is a conductive layer. The bonding layer includes a first bonding metal layer and a second bonding metal layer. The first bonding metal layer is electrically connected to the bottom reflective metal layer, and the second bonding metal layer is electrically connected to the anode contact.

3. The optoelectronic device based on multi-faceted reflection according to claim 2, characterized in that: The P-type semiconductor layer and the bottom reflective metal layer are both in direct contact with the transparent conductive film layer to be electrically connected.

4. The optoelectronic device based on multi-faceted reflection according to claim 2, characterized in that: A bottom reflective medium layer is further arranged between the transparent conductive film layer and the bottom reflective metal layer, and the bottom reflective medium layer is a non-conductive layer.

5. The optoelectronic device based on multi-faceted reflection according to claim 4, characterized in that: The pixel unit further includes a side metal fence, which is located outside the side reflective metal layer. The transparent conductive film layer and the bottom reflective metal layer are electrically connected via the side metal fence.

6. The optoelectronic device based on multi-faceted reflection according to claim 4, characterized in that: The refractive index of the bottom reflective medium layer is smaller than the refractive index of the transparent conductive film layer.

7. The multi-faceted reflective optoelectronic device according to claim 1, characterized in that: The transparent conductive film layer is one or more of an ITO film layer, a ZnO film layer and an IZO film layer.

8. The multi-faceted reflective optoelectronic device according to claim 1, characterized in that: A step portion is formed on one end of the side insulating layer close to the transparent conductive film layer, and the side reflective metal is located on the step portion.

9. The multi-faceted reflective optoelectronic device according to claim 1, characterized in that: A metal grid is further arranged between two adjacent pixel units, and each of the metal grids is electrically connected to the common cathode.

10. The multi-faceted reflective optoelectronic device according to claim 1, characterized in that: Each pixel unit is also connected to a micro lens.

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