True random number generation system
By designing a true random number generation system, the light source generation module, a single photon detector and a time-digit converter generate unpredictable random numbers, and combined with the time value of the timing device, the problem of pseudo-random numbers being easily cracked is solved, and high-security true random number generation is achieved.
Patent Information
- Application Number
- CN202421492092.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-27
- Publication Date
- 2025-04-29
- Estimated Expiration
- 2034-06-27
AI Technical Summary
The keys generated by pseudo-random numbers used in the prior art are easily cracked and difficult to meet the needs of information security.
A true random number generation system is designed, including a light source generation module, a single photon detector, a time digitizer, a time digitizer, a time digitizer to convert the single photon number detected by the single photon detector into an unpredictable numerical value, and a true random number is generated in combination with the time digitizer provided by the time digitizer.
The generated true random numbers are unpredictable, avoiding attackers finding rules and using algorithm vulnerabilities to attack, greatly ensuring information security.
Smart Images
Figure CN222813131U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of random number generation, in particular to a true random number generation system. Background Art
[0002] With the rapid development of the global information age, information security is becoming more and more important. In order to ensure information security, people usually use keys to encrypt information. Random numbers are the basis of keys, and the market is currently flooded with a variety of products that use pseudo-random numbers as the main character.
[0003] The seed in the key generated by the pseudo-random number is obtained through a mathematical algorithm and is not truly random and irregular. The rules of the pseudo-random number can be cracked through mathematical rules and big data analysis, which creates a risk of attack and makes it difficult to meet information security needs.
[0004] Theoretical physicists have proposed a variety of methods for generating quantum random numbers. Quantum random number generators generate quantum random numbers by detecting the results of quantum physical processes. Due to the intrinsic randomness of quantum mechanics in quantum physical processes, the random numbers generated by quantum random number generators are generally believed to have Poisson distribution true randomness, cannot be predicted, and are an ideal random number.
[0005] Therefore, it is necessary to improve the existing technology and propose a system that can generate true random numbers. Utility Model Content
[0006] In order to solve the problem of the risk of being attacked when using pseudo-random number encryption, the utility model proposes a true random number generation system.
[0007] In order to achieve the above purpose, the technical solution adopted by the utility model is as follows:
[0008] A true random number generation system includes a light source generation module, a single photon detector, a time digital converter, a timing device and a processing module;
[0009] The output end of the light source generating module is connected to the input end of the single photon detector, the output end of the single photon detector is connected to the input end of the time digital converter, the output end of the time digital converter and the output end of the timing device are respectively connected to the input end of the processing module, and the processing module outputs a gating signal to the single photon detector.
[0010] In the above scheme, the number of single photons detected by the single photon detector is converted into an unpredictable specific value through a time-to-digital converter, and combined with the time value provided by the timing device to form a true random number. The number is unpredictable, which prevents attackers from finding patterns and exploiting algorithm loopholes to attack, greatly ensuring information security.
[0011] Preferably, it further includes a first level conversion unit, a second level conversion unit and a buffer;
[0012] The output end of the time-to-digital converter is connected to the input end of the first level conversion unit, the output end of the first level conversion unit is connected to the input end of the second level conversion unit, the output end of the second level conversion unit is connected to the input end of the buffer, and the output end of the buffer is connected to the input end of the processing module.
[0013] Preferably, the chip model used by the first level conversion unit is MC100EPT26DR2G.
[0014] Preferably, the chip model used by the second level conversion unit is DSLVDS1001DBVR.
[0015] Preferably, the buffer uses a chip model NB6N11S.
[0016] Preferably, it also includes a rail to rail analog comparator;
[0017] An output end of the timing device is connected to an input end of the rail to rail analog comparator, and another output end of the timing device and an output end of the rail to rail analog comparator are respectively connected to an input end of the processing module.
[0018] Preferably, the chip model used by the rail to rail analog comparator is ADCMP604.
[0019] Preferably, the light source generating module comprises a plurality of laser light source generating circuits, each laser light source generating circuit comprising a trigger signal synchronization unit, a driving unit and a DFB laser;
[0020] In each laser light source generating circuit, the output end of the trigger signal synchronization unit is connected to the input end of the driving unit, the output end of the driving unit is connected to the input end of the DFB laser, and the output end of the DFB laser is connected to the input end of the single photon detector.
[0021] Preferably, the processing module is a FPGA processing module.
[0022] Preferably, the timing device is a Beidou timing device.
[0023] Beneficial technical effects of the utility model:
[0024] The utility model provides a true random number generation system, which converts the number of single photons detected by a single photon detector into an unpredictable specific value through a time-to-digital converter, and combines the time value provided by a timing device to form a true random number, which is unpredictable and prevents attackers from finding patterns and exploiting algorithm loopholes to attack, thereby greatly ensuring information security. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] Figure 1 This is a schematic diagram of module connection of the utility model;
[0026] Figure 2 A schematic diagram of the circuit principle for connecting the buffer and the FPGA processing module in the utility model;
[0027] Figure 3 It is a schematic diagram of the circuit principle of connecting the rail to rail analog comparator and the FPGA processing module in the utility model;
[0028] Among them: 001, light source generation module; 002, single photon detector; 003, time digital converter; 004, timing device; 005, processing module; 006, first level conversion unit; 007, second level conversion unit; 008, buffer; 009, rail to rail analog comparator. DETAILED DESCRIPTION
[0029] In order to make the purpose, technical solutions and advantages of the utility model more clearly understood, the utility model is further described in detail below in conjunction with embodiments, but the scope of protection claimed in the utility model is not limited to the following specific embodiments. Example
[0030] like Figure 1 As shown, a true random number generation system includes a light source generation module 001, a single photon detector 002, a time digital converter 003, a timing device 004 and a processing module 005;
[0031] The output end of the light source generating module 001 is connected to the input end of the single photon detector 002, the output end of the single photon detector 002 is connected to the input end of the time digital converter 003, the output end of the time digital converter 003 and the output end of the timing device 004 are respectively connected to the input end of the processing module 005, and the processing module 005 outputs a gating signal to the single photon detector 002.
[0032] During the specific implementation process, the number of single photons detected by the single photon detector 002 is converted into an unpredictable specific value through the time-to-digital converter 003, and combined with the time value provided by the timing device 004 to form a true random number, which is unpredictable and prevents attackers from finding patterns and exploiting algorithm loopholes to attack, thereby greatly ensuring information security.
[0033] In the specific implementation process, the light source generating module 001 is used to generate a narrow pulse signal light; the pulse width of the narrow pulse signal light is about 300ps;
[0034] The single photon detector 002 is used to detect the photons of the narrow pulse signal light generated by the light source generating module 001; the single photon detector 002 is used to detect and count single photons;
[0035] The high-precision time-to-digital converter 003 (TDC) is used to convert the number of single photons detected and output by the single photon detector 002 into digital form. The TDC inputs the photoelectron signal pulse from the single photon detector 002 and the reference pulse from the laser into the delay chain. The timing logic looks at the data in the delay chain, identifies the start-stop pairs of single photons and laser pulses, and in this way determines the time position of the single photon in the laser pulse sequence;
[0036] The processing module 005 is used to process the count value output by the TDC and the current accurate time value obtained by the timing device 004 and then output a true random number; the adjustable gating signal output by the processing module 005 is consistent with the frequency of the signal light, which is used to make the APD inside the single-photon detector 002 produce an avalanche effect within this frequency, and then the number of single photons detected after the avalanche effect occurs is connected to the TDC through an SMA radio frequency connection line after AD conversion inside the single-photon detector 002, and the number of single photons currently detected is displayed on the TDC;
[0037] The timing device 004 is based on Beidou satellites and is used to obtain accurate time values, accurate to the microsecond level, and the timing accuracy is less than or equal to 100ns; the current system time to the second or microsecond level can be considered random.
[0038] More specifically, the processing module 005 is an FPGA processing module.
[0039] In the specific implementation process, the FPGA processing module defines the number of single photons currently detected as p, and the current specific time value as q, and uses the RSA algorithm for encryption to generate a random number key:
[0040] Arbitrarily select two different large prime numbers p and q to calculate the product n = pq, β(n) = (p - 1)(g - 1).
[0041] Arbitrarily select a large integer e that satisfies gcd(e,β(n)) = 1, and the integer e is used for encryption (the selection of e is easy, such as all prime numbers greater than p and q can be used).
[0042] More specifically, the timing device 004 is a Beidou timing device.
[0043] In the specific implementation process, the high-precision timing device 004 is a highly integrated, high-performance, and highly reliable universal time and frequency device. The product is based on soft time synchronization technology and universal and platform-based software and hardware. It has functions such as high-precision time and frequency synchronization, high-precision timing, high-precision timekeeping, and high-performance time and frequency output. It can also realize high-precision PTP synchronization and NTP / SNTP high-precision time server functions through Ethernet to provide accurate time and frequency signals. Beidou timing equipment is based on high-precision time synchronization of satellites, receives Beidou satellite signals, and realizes high-precision time reference and location information. The current time obtained by the Beidou timing equipment with a precision of microseconds is input into the FPGA through the IRIG-B code. In addition, the Beidou timing equipment has a built-in rubidium clock and OCXO, and the output of the high-precision frequency reference signal tamed by the satellite is input into the FPGA.
[0044] More specifically, it also includes a first level conversion unit 006, a second level conversion unit 007 and a buffer 008;
[0045] The output end of the time-to-digital converter 003 is connected to the input end of the first level conversion unit 006, the output end of the first level conversion unit 006 is connected to the input end of the second level conversion unit 007, the output end of the second level conversion unit 007 is connected to the input end of the buffer 008, and the output end of the buffer 008 is connected to the input end of the processing module 005.
[0046] More specifically, the chip model used by the first level conversion unit 006 is MC100EPT26DR2G.
[0047] More specifically, the chip model used by the second level conversion unit 007 is DSLVDS1001DBVR.
[0048] More specifically, the buffer 008 uses a chip model NB6N11S.
[0049] In the specific implementation process, the signal FROM_APD_SIG1+ and the signal FROM_APD_SIG1- represent a pair of differential signals formed after the single photon number detected after the APD inside the single photon detector 002 avalanche occurs, which can effectively suppress electromagnetic interference (EMI), have strong anti-interference ability, and accurate timing positioning. This pair of differential signals is input into the chip MC100EPT26DR2G. After level conversion, the signal FROM_APD_SIG1+ that originally entered using the LVPECL level is converted into the LVTTL level. The 130 ohm pull-up resistor and 82 ohm pull-down resistor on the right side of FROM_APD_SIG1+ are the matching resistors of the LVPECL level at the receiving end; then the LVTTL level output by the chip MC100EPT26DR2G is impedance matched through a series 33 ohm resistor and enters the subsequent chip DSLVDS1001DBVR. The subsequent chip DSLVDS1001DBVR converts the LVTTL level into the LVDS level, signal APD01_DET_P and signal APD01_DET_N, which is convenient for transmission within the PCB board. Figure 2 As shown, the converted signal APD01_DET_P is input to the chip NB6N11S. The chip NB6N11S is used as buffer 008 here. It has high input impedance and low output impedance, and is suitable as the front-end input of the main chip such as FPGA. The signal APD01_DET_P is input to the FPGA processing module after passing through the chip NB6N11S. The FPGA processing module obtains the specific value of the detected single photon, combines it with the specific current time obtained later, and generates a random number.
[0050] More specifically, it also includes a rail to rail analog comparator 009;
[0051] An output end of the timing device 004 is connected to an input end of the rail to rail analog comparator 009 , and another output end of the timing device 004 and an output end of the rail to rail analog comparator 009 are connected to an input end of the processing module 005 , respectively.
[0052] More specifically, the chip model used by the rail to rail analog comparator 009 is ADCMP604.
[0053] In the specific implementation process, Figure 3As shown, the 5V5 voltage is first converted into the required TOD_5V voltage through the power conversion chip TPS7A2401DBVR. Then the high-precision timing device 004 has a built-in rubidium clock and OCXO, and the high-precision frequency reference signal that has been tamed by the satellite is input into the chip ADCMP604 through the SMA radio frequency socket. The 10MHz signal CLK_10MHZ input from the high-precision timing device 004 is compared with the voltage of the pin 4 of the chip ADCMP604, and a pair of differential signals are output and enter the FPGA processing module. At the same time, the SMA radio frequency socket above inputs the time signal IRIG-B code output by the high-precision timing device 004 into the FPGA processing module to obtain the current specific time.
[0054] More specifically, the light source generating module 001 includes a plurality of laser light source generating circuits, each of which includes a trigger signal synchronization unit, a driving unit and a DFB laser;
[0055] In each laser light source generating circuit, the output end of the trigger signal synchronization unit is connected to the input end of the driving unit, the output end of the driving unit is connected to the input end of the DFB laser, and the output end of the DFB laser is connected to the input end of the single photon detector 002.
[0056] In the specific implementation process, the laser light source generating circuits in the light source generating module 001 are arranged in parallel, and each laser light source generating circuit is connected to the processor and the temperature control circuit; and each laser light source generating circuit includes a trigger signal synchronization unit, a driving unit and a DFB (Distributed Feedback) laser; in order to generate the narrow pulse laser signal required subsequently, the processor is used to control the trigger signal synchronization unit to perform corresponding delay adjustment on the trigger signal, and the processor is used to control the driving unit to perform ultra-narrow pulse width modulation and amplification processing on the trigger signal.
[0057] The trigger signal modulation range is: to achieve signal delay adjustment in the range of 2.2ns to 12.4ns with a step of 10ps.
[0058] The signal light output by the light source generating module 001 has good performance, and the frequency and amplitude are very stable. The output optical power is adjustable, and the output threshold current and SMSR parameters are in line with the standards. When the output signal light is input into the oscilloscope through the photodetector, it can be seen that the signal light waveform has less jitter. Therefore, the number of photons detected using this signal light is within a certain range, laying a good foundation for the subsequent decoding at the receiving end.
[0059] According to the disclosure and teaching of the above specification, the technicians in the field of the utility model can also change and modify the above implementation. Therefore, the utility model is not limited to the specific implementation methods disclosed and described above, and some modifications and changes to the utility model should also fall within the scope of protection of the claims of the utility model. In addition, although some specific terms are used in this specification, these terms are only for convenience and do not constitute any limitation to the utility model.
Claims
1. A true random number generation system, characterized in that: It includes a light source generation module, a single photon detector, a time digital converter, a timing device and a processing module; The output end of the light source generating module is connected to the input end of the single photon detector, the output end of the single photon detector is connected to the input end of the time digital converter, the output end of the time digital converter and the output end of the timing device are respectively connected to the input end of the processing module, and the processing module outputs a gating signal to the single photon detector.
2. A true random number generation system according to claim 1, characterized in that: Also includes a first level conversion unit, a second level conversion unit and a buffer; The output end of the time-to-digital converter is connected to the input end of the first level conversion unit, the output end of the first level conversion unit is connected to the input end of the second level conversion unit, the output end of the second level conversion unit is connected to the input end of the buffer, and the output end of the buffer is connected to the input end of the processing module.
3. A true random number generation system according to claim 2, characterized in that: The chip model used by the first level conversion unit is MC100EPT26DR2G.
4. A true random number generation system according to claim 2, characterized in that: The chip model used by the second level conversion unit is DSLVDS1001DBVR.
5. A true random number generation system according to claim 2, characterized in that: The buffer uses a chip model NB6N11S.
6. A true random number generation system according to claim 1, characterized in that: Also includes rail to rail analog comparator; An output end of the timing device is connected to an input end of the rail to rail analog comparator, and another output end of the timing device and an output end of the rail to rail analog comparator are respectively connected to an input end of the processing module.
7. A true random number generation system according to claim 6, characterized in that: The chip model used by the rail to rail analog comparator is ADCMP604.
8. A true random number generation system according to claim 1, characterized in that: The light source generation module includes multiple laser light source generation circuits, each of which includes a trigger signal synchronization unit, a driving unit and a DFB laser; In each laser light source generating circuit, the output end of the trigger signal synchronization unit is connected to the input end of the driving unit, the output end of the driving unit is connected to the input end of the DFB laser, and the output end of the DFB laser is connected to the input end of the single photon detector.
9. A true random number generation system according to claim 1, characterized in that: The processing module is an FPGA processing module.
10. A true random number generation system according to claim 1, characterized in that: The timing device is Beidou timing device.