Package structure

Abstract

A package structure includes a first bonding film formed on a first substrate and a first alignment mark formed in the first bonding film. The first alignment mark includes a plurality of first patterns spaced apart from each other. The package structure includes a second bonding film formed on the second substrate and bonded to the first bonding film. The package structure includes a second alignment mark formed in the second bonding film. The second alignment mark includes a plurality of second patterns spaced apart from each other. In a top view, the first alignment marks are separated from the second alignment marks, and the distance between adjacent first patterns is smaller than the distance between the first alignment marks and the second alignment marks.

Description

Technical Field

[0001] The embodiment of the utility model relates to a packaging structure, and more particularly to a packaging structure provided with an alignment mark composed of a plurality of patterns. Background Art

[0002] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. Individual dies are usually packaged separately. The package not only provides protection for the semiconductor device from environmental contamination, but also provides a connection interface for the semiconductor device packaged therein.

[0003] Three dimensional integrated circuit (3DIC) is the latest development in semiconductor packaging, in which multiple semiconductor dies are stacked on top of each other, such as package-on-package (PoP) and system-in-package (SiP) packaging technologies. Some 3D integrated circuits are prepared at the semiconductor wafer level by placing dies on top of dies. 3D integrated circuits offer improved integration density and other advantages, such as faster speed and higher bandwidth, due to, for example, shortened interconnect lengths between stacked dies. However, there are still many challenges associated with 3D integrated circuits. Utility Model Content

[0004] An embodiment of the utility model provides a packaging structure, including a first bonding film formed on a first substrate and a first alignment mark formed in the first bonding film. The first alignment mark includes a plurality of first patterns separated from each other. The packaging structure includes a second bonding film formed on a second substrate and bonded to the first bonding film. The packaging structure includes a second alignment mark formed in the second bonding film. The second alignment mark includes a plurality of second patterns separated from each other. In a top view, the first alignment mark is separated from the second alignment mark, and the distance between adjacent first patterns is less than the distance between the first alignment mark and the second alignment mark.

[0005] According to one embodiment of the present disclosure, each of the plurality of first patterns includes: a dielectric layer disposed in the first bonding film; and a metal layer disposed in the first bonding film, so that the dielectric layer is disposed between the metal layer and the first bonding film, wherein a top surface of the metal layer is flush with a top surface of the first bonding film.

[0006] According to one embodiment of the present disclosure, a plurality of the first patterns and a plurality of the second patterns are arranged symmetrically about a central axis, and the central axis is perpendicular to a top surface of the first substrate. In the top view, the central axis is separated from the first alignment mark and the second alignment mark.

[0007] According to one embodiment of the present disclosure, in the top view, the shapes of the plurality of the first patterns or the plurality of the second patterns are circular, elliptical, rounded rectangular or polygonal.

[0008] According to one embodiment of the present disclosure, in a top view, an area of ​​each of the plurality of first patterns and the plurality of second patterns is between about 0.1 μm 2 to about 30 μm 2 .

[0009] The utility model embodiment provides a packaging structure, including a first bonding film on a first packaging element and a second bonding film on a second packaging element. A plurality of first grooves are formed in the first bonding film, a first plurality of first patterns and a second plurality of first patterns are formed by filling the first dielectric material and the first conductive material in the first grooves, and the distance between two adjacent first patterns is less than the distance between one of the first plurality of first patterns and one of the second plurality of first patterns. A plurality of second grooves are formed in the second bonding film, and a plurality of second patterns are formed by filling the second dielectric material and the second conductive material in the second grooves. The second packaging element is bonded to the first packaging element through the first bonding film and the second bonding film.

[0010] According to one embodiment of the present disclosure, a distance between two adjacent ones of the first plurality of first patterns is between about 0.1 μm and about 2 μm.

[0011] According to one embodiment of the present disclosure, a depth of the plurality of first grooves is smaller than a thickness of the first bonding film.

[0012] According to one embodiment of the present disclosure, a third bonding film is located on a third packaging component, wherein a plurality of third grooves are formed in the third bonding film, and a plurality of third patterns are formed by filling a third dielectric material and a third conductive material in the plurality of third grooves, wherein the third packaging component is bonded to the first packaging component through the first bonding film and the third bonding film, and on an upper surface of the first bonding film, an area of ​​the plurality of third patterns is different from an area of ​​the plurality of second patterns.

[0013] According to one embodiment of the present disclosure, the first bonding film further includes a first bonding pad disposed adjacent to the plurality of first patterns, and the second bonding film further includes a second bonding pad aligned with the first bonding pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The following detailed description and the accompanying drawings provide a better understanding of the concepts of the embodiments of the present invention. It should be noted that, in accordance with standard practice in the industry, the various features in the drawings are not necessarily drawn to scale. In fact, the sizes of the various features may be arbitrarily enlarged or reduced to make the description clear. Similar features are indicated by similar reference numerals throughout the specification and drawings.

[0015] Figures 1A to 1D are cross-sectional views illustrating various stages of forming a first alignment mark according to some embodiments of the present disclosure.

[0016] FIG. 2A to FIG. 2B are cross-sectional views illustrating various stages of forming a package structure according to some embodiments of the present disclosure.

[0017] FIG. 3A to FIG. 3C is a schematic diagram showing a first alignment mark and a second alignment mark according to some embodiments of the present disclosure.

[0018] FIG. 4A to FIG. 4C is a schematic diagram showing a first alignment mark and a second alignment mark according to some embodiments of the present disclosure.

[0019] FIG. 5A to FIG. 5C is a schematic diagram showing a first alignment mark and a second alignment mark according to some embodiments of the present disclosure.

[0020] FIG. 6A to FIG. 6C is a schematic diagram showing a first alignment mark and a second alignment mark according to some embodiments of the present disclosure.

[0021] Figure 7 is a cross-sectional view showing a package structure according to some embodiments of the present disclosure.

[0022] Figure 8 is a cross-sectional view showing a package structure according to some embodiments of the present disclosure.

[0023] The reference numerals are as follows:

[0024] 10,20,30: packaging structure

[0025] 100: First base

[0026] 110: First bonding film

[0027] 110T: Top surface

[0028] 115: First groove

[0029] 115B: Bottom

[0030] 115S: Sidewall

[0031] 120,120A,120B,120C,120D,120E,120F,120G,120H,120I,120J,120K,120L: First alignment mark

[0032] 120A1,120A2,120A3,120A4: Sub-alignment mark

[0033] 122: first dielectric material

[0034] 124: first conductive material

[0035] 125,125A,125B,125C,125D,125E,125F,125G,125H,125I,125J,125K,125L:First pattern

[0036] 200: Second base

[0037] 210: Second bonding film

[0038] 210T: Top

[0039] 220,220A,220B,220C,220D,220E,220F,220G,220H,220I,220J,220K,220L: Second alignment mark

[0040] 220A1, 220A2, 220A3, 220A4: Sub-alignment mark

[0041] 222: Second dielectric material

[0042] 224: second conductive material

[0043] 225,225A,225B,225C,225D,225E,225F,225G,225H,225I,225J,225K,225L: Second pattern

[0044] 300: first packaging component

[0045] 302,304: Dielectric layer

[0046] 310:Through Silicon Via Structure

[0047] 312:Metalized pattern

[0048] 314: Conductive characteristics

[0049] 315:Internal connection structure

[0050] 320: Bonding film

[0051] 322: Bonding pad

[0052] 330: First alignment mark

[0053] 360: Bump structure

[0054] 400: second packaging component

[0055] 420: Bonding film

[0056] 422: Bonding pad

[0057] 430: Second alignment mark

[0058] 500: The third package component

[0059] 520: Bonding film

[0060] 522: Bonding pad

[0061] 530: Third alignment mark

[0062] C: Center axis

[0063] C1: First central axis

[0064] C2: Second central axis

[0065] D1,D2,D3: distance

[0066] S1, S2, S3: Distance DETAILED DESCRIPTION

[0067] The following disclosure provides many different embodiments or examples to implement different features of the embodiments of the present disclosure. Reference numerals and / or letters may be repeated in the various examples described in the present disclosure. These repetitions are for the purpose of simplicity and clarity, and do not in themselves indicate any relationship between the various embodiments and / or configurations disclosed. In addition, specific examples of components and configurations are described below to simplify the description of the embodiments of the present disclosure. Of course, these specific examples are only for demonstration and are not intended to limit the embodiments of the present disclosure. For example, in the following description, it is mentioned that the first feature is formed on or above the second feature, which means that it may include an embodiment in which the first feature and the second feature are in direct contact, and may also include an additional feature formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not in itself specify the relationship between the various embodiments and / or configurations described.

[0068] Additionally, spatially relative terms may be used herein. For example, "below," "below," "lower," "above," "higher," and similar terms may be used to describe the relationship between one element or feature and another element or features shown in the accompanying drawings. These spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation shown in the accompanying drawings. The device may be turned to different orientations (rotated 90 degrees or other orientations), and the spatially relative terms used herein may be interpreted similarly.

[0069] An embodiment of a packaging structure and a method for forming the same is provided. The packaging structure includes a corresponding alignment mark, the alignment mark includes an area of ​​no more than 30 μm on a horizontal plane. 2 Therefore, the recess problem that may occur during the planarization process can be reduced. In this way, the recognition error of the alignment mark pattern can be reduced during the subsequent bonding process.

[0070] Figures 1A to 1D A cross-sectional view of various stages of forming a first alignment mark according to some embodiments of the present disclosure is shown. For example, the first substrate 100 includes a semiconductor substrate, which includes, for example, doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. In some embodiments, the first substrate 100 includes other semiconductor materials, such as germanium, compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide), alloy semiconductors (including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP), or combinations of the foregoing. Other substrates, such as multilayer substrates or gradient substrates, may also be used.

[0071] In addition, a first bonding film 110 is formed on the first substrate 100 for subsequent bonding processes. For example, the material of the first bonding film 110 includes SiON, SiO 2, any other suitable material or a combination of the foregoing materials. In some embodiments, a patterned photoresist layer (not shown) is formed over the first bonding film 110. The patterned photoresist layer may be formed by a deposition process and a patterning process. The deposition process for forming the patterned photoresist layer may include a chemical vapor deposition (CVD) process, a high-density plasma chemical vapor deposition (HDPCVD) process, a spin coating process, a sputtering process or other applicable processes. The patterning process for forming the patterned photoresist layer may include a photolithography process and an etching process. The photolithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing and drying (e.g., hard baking). The etching process may include a dry etching process or a wet etching process. Next, the patterned photoresist layer may be used as a mask to recess the first substrate 100 through an etching process and form a plurality of first grooves 115 in the first bonding film 110. The etching process may be a dry etching process or a wet etching process. In some embodiments, the dry etching process includes using a fluorine-based etchant gas, such as SF 6 , C x F y NF 3 Or a combination of the foregoing. The etching process may be a time-controlled process. Next, the patterned photoresist layer is removed.

[0072] In some embodiments, each first groove 115 has a bottom surface 115B and a side wall 115S connected to the bottom surface 115B. For example, the exemplary side wall 115S is substantially perpendicular to the bottom surface 115B. However, the present disclosure is not limited thereto. The first grooves 115 are separated from each other by a portion of the first bonding film 110. In some embodiments, a portion of the first bonding film 110 is sandwiched between adjacent first grooves 115 in a horizontal direction (e.g., a direction parallel to the X-axis). In some embodiments, the depth of the first groove 115 is less than the thickness of the first bonding film 110. That is, the first groove 115 may not penetrate the first bonding film 110 and expose the first substrate 100 below. However, the present disclosure is not limited thereto. In some embodiments, the first grooves 115 are formed to have the same width in a direction parallel to the XY plane. In some embodiments, the first grooves 115 are formed at fixed intervals. Therefore, the spacing between the first grooves 115 is fixed in a direction parallel to the XY plane. However, the present disclosure is not limited thereto.

[0073] Then, if Figure 1BAs shown, a first dielectric material 122 is deposited in the first trench 115. In some embodiments, the first dielectric material 122 covers the bottom surface 115B and the sidewall 115S of the first trench 115, and the top surface 110T of the first bonding film 110 is also covered by the first dielectric material 122. In some embodiments, the first dielectric material 122 is conformally formed on the first bonding film 110, but the present disclosure is not limited thereto. In some embodiments, the thickness of the first dielectric material 122 on the bottom surface 115B of the first trench 115 is greater than the thickness of the first dielectric material 122 on the sidewall 115S of the first trench 115.

[0074] For example, the first dielectric material 122 includes silicon dioxide (SiO 2 ), phosphor-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phosphor-silicate glass (BPSG), undoped silicate glass (USG), and the like. In some embodiments, the first dielectric material 122 is formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), and the like. However, the present disclosure is not limited thereto. Any suitable material and method for forming the first dielectric material 122 are considered within the scope of the present disclosure.

[0075] like Figure 1C As shown, the first conductive material 124 is deposited in the first trench 115 and on the first dielectric material 122. For example, the first conductive material 124 includes, for example, tungsten (W), cobalt (Co), nickel (Ni), copper (Cu), silver (Ag), gold (Au), aluminum (Al), any other suitable conductive material, or a combination of the foregoing. In some embodiments, the first conductive material 124 and the first dielectric material 122 fill and overflow the first trench 115 and cover the top surface 110T of the first bonding film 110.

[0076] like Figure 1DAs shown, a planarization process (e.g., chemical mechanical polishing (CMP) or any other suitable planarization process) is performed on the first dielectric material 122 and the first conductive material 124. In this way, the top surfaces of the first dielectric material 122 and the first conductive material 124 can be substantially coplanar with the top surface 110T of the first bonding film 110. After the planarization process is completed, a first alignment mark 120 is formed in the first bonding film 110. The first alignment mark 120 includes a plurality of first patterns 125 separated from each other. More specifically, each first pattern 125 is formed by the first dielectric material 122 and the first conductive material 124 in each first trench 115. That is, the first dielectric material 122 and the first conductive material 124 in each first trench 115 define each first pattern 125.

[0077] In some embodiments, each of the first patterns 125 has a thickness of no greater than 30 μm on a horizontal plane (eg, parallel to the top surface 110T of the first bonding film 110 ). 2 As a result, the concavity problem that may occur during the planarization process can be reduced. As a result, the top surface of the first conductive material 124 in the first pattern 125 can be less curved and remain coplanar with the top surface 110T of the first bonding film 110. Therefore, the recognition error of the first pattern 125 can be reduced during the subsequent bonding process. The following paragraphs will be used in conjunction with FIG. 2A to FIG. 2B The details of the bonding process are further described.

[0078] FIG. 2A to FIG. 2B 1 and 2 show cross-sectional views of various stages of forming a package structure 10 according to some embodiments of the present disclosure. In some embodiments, the package structure 10 is formed by bonding the second substrate 200 to the first substrate 100. Figure 2A As shown, the first alignment mark 120 is formed in the first bonding film 110 located above the first substrate 100. In addition, the second alignment mark 220 is formed in the second bonding film 210 located above the second substrate 200. In some embodiments, the second alignment mark 220 is formed in the second bonding film 210 using the same material as the first alignment mark 120. For example, the second dielectric material 222 and the second conductive material 224 are filled into the plurality of second grooves 215 in the second bonding film 210. Then, the second bonding film 210 is subjected to a planarization process to form the second alignment mark 220. The second alignment mark 220 includes a plurality of second patterns 225 separated from each other. More specifically, each second pattern 225 is formed by the second dielectric material 222 and the second conductive material 224 in each second groove 215. That is, the second dielectric material 222 and the second conductive material 224 in each second groove 215 define each second pattern 225.

[0079] In some embodiments, the first alignment mark 120 has a first central axis C1, and the second alignment mark 220 has a second central axis C2. More specifically, the first central axis C1 is located at the center of the entire first alignment mark 120 and is perpendicular to the top surface 110T of the first bonding film 110. In some embodiments, the first pattern 125 is formed, for example, symmetrically to the first central axis C1. FIG. 3A to FIG. 3C Similarly, the second central axis C2 is located at the center point of the entire second alignment mark 220 and is perpendicular to the top surface 210T of the second bonding film 210. In some embodiments, the second pattern 225 is formed symmetrically to the second central axis C2.

[0080] like Figure 2A As shown, before the second substrate 200 is bonded to the first substrate 100, the first central axis C1 of the first alignment mark 120 is aligned with the second central axis C2 of the second alignment mark 220. Figure 2B As shown, after determining that the first central axis C1 of the first alignment mark 120 coincides with the second central axis C2 of the second alignment mark 220, the second substrate 200 is moved toward the first substrate 100, and the first bonding film 110 is bonded (e.g., in contact) with the second bonding film 210. In this embodiment, the first central axis C1 and the second central axis C2 are integrated together as the central axis C. In some embodiments, the first alignment mark 120 and the second alignment mark 220 are staggered in the horizontal direction (e.g., parallel to the central axis). By configuring the first alignment mark 120 and the second alignment mark 220, the process time and cost for bonding the first substrate 100 and the second substrate 200 can be reduced.

[0081] FIG. 3A to FIG. 3C Schematic diagrams showing first alignment marks 120A to 120C and second alignment marks 220A to 220C according to some embodiments of the present disclosure. Figure 3A As shown, the first alignment mark 120A includes a plurality of sub-alignment marks 120A1, 120A2, 120A3, and 120A4, and each sub-alignment mark includes a plurality of first patterns 125A. Correspondingly, the second alignment mark 220A includes a plurality of sub-alignment marks 220A1, 220A2, 220A3, and 220A4, and each sub-alignment mark includes a plurality of second patterns 225A. In the present embodiment, the sub-alignment marks 120A1, 120A2, 120A3, and 120A4 may have a rectangular outline, and the sub-alignment marks 220A1, 220A2, 220A3, and 220A4 may also have a rectangular outline. In some embodiments, in a top view, the area of ​​each of the first pattern 125A and the second pattern 225A is between about 0.1 μm 2 to about 30 μm 2As described above, the first pattern 125A of the first alignment mark 120A can reduce the recess problem that may occur during the planarization process, thereby improving the accuracy of identifying and aligning the first alignment mark 120A (and the second alignment mark 220A).

[0082] In the present embodiment, the first alignment mark 120A is separated from the second alignment mark 220A, and the first alignment mark 120A and the second alignment mark 220A are arranged around the central axis C. In the present embodiment, the distance D1 between adjacent first patterns 125A is less than the distance S1 between the first alignment mark 120A and the second alignment mark 220A, which helps to determine the boundary between the first alignment mark 120A and the second alignment mark 220A. In some embodiments, the distance S1 between the first alignment mark 120A and the second alignment mark 220A may be in the range of about 2 μm to about 3 μm. However, the present disclosure is not limited thereto.

[0083] like Figure 3B As shown, the first alignment mark 120B includes a plurality of sub-alignment marks 120B1, 120B2, 120B3, and 120B4, and each sub-alignment mark includes a plurality of first patterns 125B. In this embodiment, the first pattern 125B may have a rectangular outline. Accordingly, the second alignment mark 220B includes a plurality of second patterns 225B located between the sub-alignment marks 120B1, 120B2, 120B3, and 120B4, and the second patterns 225B may be collectively considered to have a cross outline.

[0084] In this embodiment, the first alignment mark 120B is separated from the second alignment mark 220B, and the first alignment mark 120B and the second alignment mark 220 are arranged around the central axis C. In this embodiment, the distance D2 between adjacent first patterns 125B is smaller than the distance S2 between the first alignment mark 120B and the second alignment mark 220B, which helps to determine the boundary between the first alignment mark 120B and the second alignment mark 220B.

[0085] like Figure 3C As shown, the first alignment mark 120C includes a plurality of sub-alignment marks 120C1, 120C2, 120C3, and 120C4, each of which includes a plurality of first patterns 125C. In this embodiment, the first pattern 125C may have a triangular outline. Accordingly, the second alignment mark 220C includes a plurality of sub-alignment marks 220C1, 220C2, 220C3, 220C4, and 220C5, and each of which includes a plurality of second patterns 225C located around the sub-alignment marks 120C1, 120C2, 120C3, and 120C4.

[0086] In this embodiment, the first alignment mark 120C is separated from the second alignment mark 220C, and the first alignment mark 120C and the second alignment mark 220C are arranged around the central axis C. In this embodiment, the distance D3 between adjacent first patterns 125C is smaller than the distance S3 between the first alignment mark 120C and the second alignment mark 220C, which helps to determine the boundary between the first alignment mark 120C and the second alignment mark 220C.

[0087] FIG. 4A to FIG. 4C Schematic diagram showing first alignment marks 120D to 120F and second alignment marks 220D to 220F according to some embodiments of the present disclosure. It should be noted that the first alignment marks 120D to 120F and the second alignment marks 220D to 220F in this embodiment may include FIG. 3A to FIG. 3C The first alignment marks 120A to 120C are shown as identical or similar elements to the second alignment marks 220A to 220C. These elements are represented by identical or similar reference numerals and will not be described in detail in the following paragraphs. FIG. 4A to FIG. 4C As shown, the first patterns 125D to 125F in the first alignment marks 120D to 120F and the second patterns 225D to 225F in the second alignment marks 220D to 220F may have a rounded rectangular shape.

[0088] FIG. 5A to FIG. 5C Schematic diagram showing first alignment marks 120G to 120I and second alignment marks 220G to 220I according to some embodiments of the present disclosure. It should be noted that the first alignment marks 120G to 120I and the second alignment marks 220G to 220I in this embodiment may include FIG. 3A to FIG. 3C The first alignment marks 120A to 120C are shown as identical or similar elements to the second alignment marks 220A to 220C. These elements are represented by identical or similar reference numerals and will not be described in detail in the following paragraphs. FIG. 5A to FIG. 5C As shown, the first patterns 125G to 125I in the first alignment marks 120G to 120I and the second patterns 225G to 225I in the second alignment marks 220G to 220I may have a hexagonal shape. It should be noted that other types of polygons are also contemplated within the scope of the present disclosure.

[0089] FIG. 6A to FIG. 6C Schematic diagram showing the first alignment marks 120J to 120L and the second alignment marks 220J to 220L according to some embodiments of the present disclosure. It should be noted that the first alignment marks 120J to 120L and the second alignment marks 220J to 220L in this embodiment may include FIG. 3A to FIG. 3CThe first alignment marks 120A to 120C are shown as identical or similar elements to the second alignment marks 220A to 220C. These elements are represented by identical or similar reference numerals and will not be described in detail in the following paragraphs. FIG. 6A to FIG. 6C As shown, the first pattern in the first alignment marks 120J to 120L and the second pattern in the second alignment marks 220J to 220L may have an elliptical shape.

[0090] Figure 7 A cross-sectional view of a package structure 20 according to some embodiments of the present disclosure is shown. For example, the first package component 300 includes a semiconductor substrate, including, for example, doped or undoped silicon, or an active layer of a semiconductor on insulator (SOI) substrate. In some embodiments, the first package component 300 includes other semiconductor materials, such as germanium, compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide), alloy semiconductors (including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP), or combinations thereof. Other substrates, such as multi-layered step bottoms or gradient substrates, may also be used.

[0091] In some embodiments, the interconnect structure 315 is formed in the first package component 300. In some embodiments, the interconnect structure 315 includes a plurality of through-silicon via (TSV) structures 310, a plurality of metallization patterns 312, and a plurality of conductive features 314. In some embodiments, the through-silicon via structure 310 is formed in the first package component 300, and the dielectric layer 302 is formed on the first package component 300. However, the present disclosure is not limited thereto. In some other embodiments, the dielectric layer 302 may be omitted, and the through-silicon via structure 310 is completely located in the first package component 300.

[0092] In some embodiments, the dielectric layer 302 includes, for example, silicon dioxide (SiO 2 ), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. In some embodiments, the dielectric layer 302 is formed by, for example, spin coating, lamination, chemical vapor deposition (CVD), etc.

[0093] In some embodiments, the formation of the through silicon via structure 310 includes forming a plurality of grooves in the first package component 300. In some embodiments, the grooves extend into the first package component 300 and penetrate the dielectric layer 302 (if present) to electrically and physically couple the metallization pattern 312 above. In some other embodiments, the through silicon via structure 310 may have a rectangular profile in a cross-sectional view. In some embodiments, the through silicon via structure 310 is formed of tungsten (W), cobalt (Co), nickel (Ni), copper (Cu), silver (Ag), gold (Au), aluminum (Al), any other suitable conductive material, or a combination of the foregoing materials. However, the present disclosure is not limited thereto.

[0094] The metallization pattern 312 and the conductive features 314 are surrounded by the dielectric layer 304 for proper insulation, thereby reducing the possibility of forming a short circuit. In some embodiments, the dielectric layer 304 includes one or more layers of, for example, silicon dioxide (SiO 2 ), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), and the like. In some embodiments, dielectric layer 304 is formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), and the like. In some embodiments, dielectric layer 304 is formed using the same material or method as dielectric layer 302. However, the present disclosure is not limited thereto. In some embodiments, dielectric layer 304 is formed using a different material or method than dielectric layer 302.

[0095] In some embodiments, one or more devices (not shown separately) are formed in the dielectric layers 302, 304 on or above the first package component 300 and are electrically connected to the through silicon via structure 310, the metallization pattern 312 and / or the conductive feature 314. In some embodiments, the above-mentioned devices are active devices (such as transistors, diodes, etc.), capacitors, resistors, etc. For example, according to some embodiments of the present disclosure, the above-mentioned devices are metal-oxide-semiconductor field-effect transistors (MOSFETs).

[0096] In some embodiments, the metallization pattern 312 includes metal lines, and the conductive features 314 include vias formed in the dielectric layer 304. For example, the metallization pattern 312 and / or the conductive features 314 include conductive materials such as tungsten (W), cobalt (Co), nickel (Ni), copper (Cu), silver (Ag), gold (Au), aluminum (Al), any other suitable conductive material, or a combination of the foregoing materials. In some embodiments, the through silicon via structure 310, the metallization pattern 312, and / or the conductive features 314 are formed of the same material. In some other embodiments, the through silicon via structure 310, the metallization pattern 312, and / or the conductive features 314 are formed of different materials.

[0097] Thus, the through silicon via structure 310 is electrically connected to the metallization pattern 312 and the conductive feature 314 to form a conductive path connected to the external environment (e.g., other semiconductor dies or external devices). For example, when the device in the first package component 300 is a transistor, the through silicon via structure 310 can be coupled to the gate or source / drain region of the transistor. The source / drain region can be referred to as a source or a drain individually or collectively depending on the context.

[0098] In addition, a bonding film 320 is formed on the first package element 300 to perform a bonding process. For example, the material of the bonding film 320 includes SiON, SiO 2 , any other suitable material, or a combination of the foregoing materials. In some embodiments, a plurality of bonding pads 322 are formed in the bonding film 320. For example, the bonding pad 322 includes a conductive material, such as tungsten (W), cobalt (Co), nickel (Ni), copper (Cu), silver (Ag), gold (Au), aluminum (Al), any other suitable conductive material, or a combination of the foregoing materials. In some embodiments, the bonding pad 322 is formed to correspond to the second package component 400. However, the present disclosure is not limited thereto. In some embodiments, a first alignment mark 330 may be formed in the bonding film 320 and adjacent to the bonding pad 322. The first alignment mark 330 may be selected from the first alignment marks 120A to 120L shown in the present disclosure. However, by Figures 1A to 1D All possible registration marks formed by the illustrated method are considered to be within the scope of the present disclosure.

[0099] In some embodiments, the second package component 400 is bonded above the first package component 300. For example, the second package component 400 may be a device die, a package encapsulating a device die, a system-on-chip (SoC) die including a plurality of device dies packaged as a system, etc. The second package component 400 may be or may include a logic die, a memory die, an input / output die, an integrated passive device (IPD), etc., or a combination thereof. For example, the logic device die in the second package component 400 may be a central processing unit (CPU) die, a graphic processing unit (GPU) die, a mobile device die, a micro control unit (MCU) die, a baseband (BB) die, an application processor (AP) die, etc. The memory die in the second package component 400 may include a static random access memory (SRAM) die, a dynamic random access memory (DRAM) die, etc. The second package component 400 may include a semiconductor substrate and an interconnect structure, which are not separately shown in this embodiment.

[0100] In addition, another bonding film 420 is formed on the second package element 400 to perform a bonding process. For example, the material of the bonding film 420 includes SiON, SiO 2 , any other suitable material, or a combination of the foregoing. In some embodiments, the material of the bonding film 420 is the same as the material of the bonding film 320. Although two bonding films (e.g., the bonding film 320 and the bonding film 420) are shown in the present disclosure, it should be understood that the present disclosure may also employ one or more (more than two) bonding films.

[0101] In some embodiments, a plurality of bonding pads 422 are formed in the bonding film 420. For example, the bonding pads 422 include a conductive material, such as tungsten (W), cobalt (Co), nickel (Ni), copper (Cu), silver (Ag), gold (Au), aluminum (Al), any other suitable conductive material, or a combination thereof. In some embodiments, the bonding pads 422 are each aligned with a bonding pad 322 above the first package component 300 to form an electrical connection between the second package component 400 and the interconnect structure 315. In some embodiments, a second alignment mark 430 may be formed in the bonding film 420 and adjacent to the bonding pad 422. The second alignment mark 430 may be selected from the second alignment marks 220A to 220L shown in the present disclosure. However, by Figures 1A to 1D All possible alignment marks formed by the method shown are considered within the scope of the present disclosure. In some embodiments, the second alignment mark 430 is aligned with the first alignment mark 330 to facilitate the bonding process.

[0102] In some embodiments, a plurality of bump structures 360 are formed on the exposed through silicon via structure 310. That is, the bump structure 360 ​​is formed on the first package component 300 and covers the exposed surface of the through silicon via structure 310. In some embodiments, the bump structure 360 ​​may include a controlled collapse chip connection (C4) bump, a solder bump, a copper bump, a micro bump, a bump formed by electroless nickel-electroless palladium-immersion gold technique (ENEPIG), a ball grid array (BGA) bump, a copper pillar, etc.

[0103] Figure 8 FIG. 4 is a cross-sectional view of a package structure 30 according to some embodiments of the present disclosure. It should be noted that the package structure 30 of this embodiment may include Figure 7 The same or similar elements of the package structure 20 shown in the figure are represented by the same or similar reference numerals and will not be described in detail in the following paragraphs. Figure 8 As shown, the package structure 30 includes a first package component 300 , an interconnect structure 315 in the first package component 300 , and a second package component 400 . The second package component 400 is bonded onto the first package component 300 through a plurality of bonding films 120 and 140 .

[0104] In some embodiments, the third package component 500 is bonded above the first package component 300. For example, the third package component 500 may be a device die, a package encapsulating a device die, a system on chip (SoC) die including a plurality of device dies packaged as a system, etc. The third package component 500 may be or may include a logic die, a memory die, an input-output die, an integrated passive device (IPD), etc., or a combination thereof. For example, the logic device die in the third package component 500 may be a central processing unit (CPU) die, a graphics processing unit (GPU) die, a mobile device die, a microcontroller unit (MCU) die, a baseband (BB) die, an application processor (AP) die, etc. The memory die in the third package component 500 may include a static random access memory (SRAM) die, a dynamic random access memory (DRAM) die, etc. The third package component 500 may include a semiconductor substrate and an internal connection structure, but they are not shown separately in this embodiment.

[0105] In addition, another bonding film 520 is formed on the third package component 500 to perform a bonding process. For example, the material of the bonding film 520 includes SiON, SiO 2 , any other suitable material, or a combination of the foregoing. In some embodiments, the material of the bonding film 520 is the same as the material of the bonding film 320. Although two bonding films (e.g., the bonding film 320 and the bonding film 520) are shown in the present disclosure, it should be understood that the present disclosure may also use one or more (more than two) bonding films.

[0106] In some embodiments, a plurality of bonding pads 522 are formed in the bonding film 520. For example, the bonding pads 522 include a conductive material, such as tungsten (W), cobalt (Co), nickel (Ni), copper (Cu), silver (Ag), gold (Au), aluminum (Al), any other suitable conductive material, or a combination thereof. In some embodiments, the bonding pads 522 are each aligned with the bonding pads 322 above the first package component 300 to form an electrical connection between the third package component 500 and the interconnect structure 315.

[0107] In some embodiments, the third alignment mark 530 may be formed in the bonding film 520 and adjacent to the bonding pad 522. The third alignment mark 530 may be selected from the second alignment marks 220A to 220L shown in the present disclosure. Figures 1A to 1D All possible alignment marks formed by the method shown are considered within the scope of the present disclosure. In some embodiments, the third alignment mark 530 is aligned with the first alignment mark 330 to facilitate the bonding process. In some embodiments, the third alignment mark 530 is different from the second alignment mark 430 to reduce the risk of the third package component 500 and / or the second package component 400 being installed in the wrong position.

[0108] As described above, the present disclosure is related to a packaging structure and a method for forming the same. The packaging structure includes a corresponding alignment mark having an area not greater than 30 μm on a horizontal plane. 2 Therefore, the problem of depression that may occur during the planarization process can be reduced. In this way, the recognition error of the alignment mark pattern can be reduced during the subsequent bonding process. In addition, the distance between adjacent patterns in the first alignment mark is smaller than the distance between the first alignment mark and the second alignment mark, which helps to determine the boundary between the first alignment mark and the second alignment mark. In addition, different alignment marks can be used for different packaging components to reduce the risk of incorrectly installing the packaging components.

[0109] According to some embodiments, a packaging structure is provided. The packaging structure includes a first bonding film formed on a first substrate and a first alignment mark formed in the first bonding film. The first alignment mark includes a plurality of first patterns separated from each other. The packaging structure includes a second bonding film formed on a second substrate and bonded to the first bonding film. The packaging structure includes a second alignment mark formed in the second bonding film. The second alignment mark includes a plurality of second patterns separated from each other. In a top view, the first alignment mark is separated from the second alignment mark, and the distance between adjacent first patterns is less than the distance between the first alignment mark and the second alignment mark.

[0110] According to some embodiments, a method for manufacturing a packaging structure is provided, including forming a first bonding film on a first substrate. The method includes forming a first alignment mark in the first bonding film. The first alignment mark includes a plurality of first patterns separated from each other. The method includes forming a second bonding film on a second substrate. The method includes forming a second alignment mark in the second bonding film. The second alignment mark includes a plurality of second patterns separated from each other. The method includes aligning the second substrate with the first substrate by aligning the first center axis of the first alignment mark with the second center axis of the second alignment mark. In a direction perpendicular to the first center axis, the distance between adjacent first patterns is less than the distance between one of the first patterns and one of the second patterns. The method also includes bonding the second substrate to the first substrate.

[0111] According to some embodiments, a packaging structure is provided, including a first bonding film on a first packaging element and a second bonding film on a second packaging element. A plurality of first grooves are formed in the first bonding film, a first plurality of first patterns and a second plurality of first patterns are formed by filling the first dielectric material and the first conductive material in the first grooves, and the distance between two adjacent first patterns is less than the distance between one of the first plurality of first patterns and one of the second plurality of first patterns. A plurality of second grooves are formed in the second bonding film, and a plurality of second patterns are formed by filling the second dielectric material and the second conductive material in the second grooves. The second packaging element is bonded to the first packaging element through the first bonding film and the second bonding film.

[0112] The features of many embodiments are summarized above so that those skilled in the art to which the present disclosure belongs can better understand the various embodiments of the present disclosure. Those skilled in the art to which the present disclosure belongs should understand that other processes and structures can be easily designed or changed based on the embodiments of the present disclosure to achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art to which the present disclosure belongs should also understand that these equivalent structures do not deviate from the spirit and scope of the present disclosure. Various changes, substitutions and modifications may be made to the embodiments of the present disclosure without departing from the spirit and scope of the appended claims.

Claims

1. A packaging structure, characterized in that: include: a first bonding film formed on a first substrate; a first alignment mark formed in the first bonding film, wherein the first alignment mark includes a plurality of first patterns separated from each other; a second bonding film formed on a second substrate and bonded to the first bonding film; as well as a second alignment mark formed in the second bonding film, wherein the second alignment mark includes a plurality of second patterns separated from each other, In a top view, the first alignment mark is separated from the second alignment mark, and a distance between adjacent first patterns is smaller than a distance between the first alignment mark and the second alignment mark.

2. The packaging structure according to claim 1, characterized in that: Each of the plurality of first patterns comprises: a dielectric layer disposed in the first bonding film; and A metal layer is disposed in the first bonding film, so that the dielectric layer is disposed between the metal layer and the first bonding film, wherein a top surface of the metal layer is flush with a top surface of the first bonding film.

3. The packaging structure according to claim 1, characterized in that: The first patterns and the second patterns are symmetrically arranged about a central axis, and the central axis is perpendicular to a top surface of the first substrate. In the top view, the central axis is separated from the first alignment mark and the second alignment mark.

4. The packaging structure according to claim 1, characterized in that: In the top view, the shapes of the plurality of the first patterns or the plurality of the second patterns are circular, elliptical, rounded rectangular or polygonal.

5. The packaging structure according to claim 1, characterized in that: In a top view, an area of ​​each of the plurality of first patterns and the plurality of second patterns is between about 0.1 μm 2 to about 30 μm 2 .

6. A packaging structure, characterized in that: include: a first bonding film located on a first package component, wherein a plurality of first grooves are formed in the first bonding film, a first plurality of first patterns and a second plurality of first patterns are formed by a first dielectric material and a first conductive material filled in the first plurality of grooves, and a distance between two adjacent ones of the first plurality of first patterns is smaller than a distance between one of the first plurality of first patterns and one of the second plurality of first patterns; as well as a second bonding film located on a second packaging element, wherein a plurality of second grooves are formed in the second bonding film, and a plurality of second patterns are formed by a second dielectric material and a second conductive material filled in the plurality of second grooves, The second packaging component is bonded to the first packaging component through the first bonding film and the second bonding film.

7. The packaging structure according to claim 6, characterized in that: A distance between two adjacent ones of the first plurality of first patterns is between about 0.1 μm and about 2 μm.

8. The packaging structure according to claim 6, characterized in that: A depth of the plurality of first grooves is smaller than a thickness of the first bonding film.

9. The packaging structure according to claim 6, characterized in that: Also includes: a third bonding film located on a third package component, wherein a plurality of third grooves are formed in the third bonding film, and a plurality of third patterns are formed by a third dielectric material and a third conductive material filled in the plurality of third grooves, The third packaging component is bonded to the first packaging component through the first bonding film and the third bonding film, and on an upper surface of the first bonding film, an area of ​​the plurality of third patterns is different from an area of ​​the plurality of second patterns.

10. The packaging structure according to claim 6, characterized in that: The first bonding film further includes a first bonding pad disposed adjacent to the first patterns, and the second bonding film further includes a second bonding pad aligned with the first bonding pad.

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