SiC-based VDMOSFET device capable of resisting single-particle gate damage
By adding an N+ buffer layer and a gate oxide layer with a composite gate dielectric layer structure in the SiC-based VDMOSFET device, the problem of SiC MOSFET device being sensitive to single-particle effects is solved, and the effect of effectively suppressing single-particle burn-out and gate pass-through effects is achieved, and the performance and radiation resistance of the device are improved.
Patent Information
- Application Number
- CN202421718211.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-19
- Publication Date
- 2025-04-29
- Estimated Expiration
- 2034-07-19
AI Technical Summary
SiC MOSFET devices are sensitive to single-particle effects, and may cause single-particle burning and single-particle gate penetration effects, resulting in device damage.
A SiC-based VDMOSFET device that resists single-particle gate damage is designed. By adding an N+ buffer layer between the high-concentration substrate and the epitaxial layer, and using a composite gate dielectric layer structure in the gate oxide layer, the thickness is controlled between 29-30 nm to suppress the occurrence of single-particle burn-out and gate pass-through effects.
It effectively suppresses the occurrence of single-particle burning effect, reduces the probability of single-particle gate penetration effect, and improves the device's parameter performance and radiation resistance.
Smart Images
Figure CN222814762U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of power semiconductor devices, and more specifically discloses a SiC-based VDMOSFET device resistant to single particle gate damage. Background Art
[0002] Power devices with higher efficiency and higher power density are one of the important directions for the development of semiconductor technology. In recent years, the emerging wide bandgap semiconductor materials have brought new development momentum to the field of semiconductor power device technology with their superior properties. Among them, the bandgap width of SiC is more than twice that of Si, the breakdown field strength is more than 10 times that of Si, the thermal conductivity is about 2.5 times that of Si, and the saturated electron drift velocity is twice that of Si. These characteristics make SiC MOSFET devices have the advantages of high voltage resistance, high frequency, and high power density, and they are gradually replacing Si-based power devices in some application fields.
[0003] In the application of aerospace and nuclear industry, SiC MOSFET devices will be affected by the radiation environment. Compared with Si-based devices, SiC MOSFET devices have stronger total dose resistance. However, SiC MOSFET devices are sensitive to single particle effects. SiC MOSFET devices may experience single particle burnout and single particle gate punchthrough effects. Single particle burnout is the local burnout of the drain and source. The transient current generated by the incident ions causes the sensitive parasitic bipolar junction transistor to turn on. The regeneration backlash mechanism of the bipolar junction transistor causes the collector junction current to continue to increase until a secondary breakdown occurs, causing a permanent short circuit between the drain and source and circuit burnout. Single particle gate punchthrough is a destructive burnout caused by a single particle passing through the gate oxide layer, resulting in a conductive path formed in the gate oxide layer.
[0004] Therefore, a SiC-based VDMOSFET device resistant to single particle gate damage is designed. Summary of the invention
[0005] The utility model provides a SiC-based VDMOSFET device resistant to single particle gate damage, which can solve the problem that SiCMOSFET devices are relatively sensitive to single particle effects and may experience single particle burnout and single particle gate penetration effects.
[0006] To solve the above technical problems, according to one aspect of the utility model, more specifically, a SiC-based VDMOSFET device resistant to single-particle gate damage comprises a substrate and a drain located below the substrate, the upper surface of the substrate having an N+ buffer layer, the upper surface of the N+ buffer layer having an N-epitaxial layer etched thereon, ion implantation forming P-type hydrazine on both sides of the upper surface of the N-epitaxial layer, each of the P-type hydrazine having a P+ region and an N+ region independently therein, the P+ region and the side of the N+ region being in contact, a first conductive column being embedded between two of the P-type hydrazines in the interior of the N-epitaxial layer, a lightly doped N-type semiconductor region being provided between the first conductive column and the P-type hydrazines, a gate oxide layer being formed on the upper surfaces of the lightly doped N-type semiconductor region, the first conductive column, part of the P-type hydrazines, and part of the N+ region, a gate being wrapped on the left and right sides of the gate oxide layer, a source being provided on the left and right sides of the gate oxide layer, and the lower surface of the source being in contact with the N-epitaxial layer, the P+ region, and the top of the P-type hydrazines.
[0007] In some embodiments, as a preferred technical solution, the substrate is an N-type doped silicon substrate.
[0008] In some embodiments, as a preferred technical solution, the thickness of the N+ buffer layer is 0.5 μm.
[0009] In some embodiments, as a preferred technical solution, the gate oxide layer adopts a composite gate dielectric layer structure, the composite gate dielectric layer is SiO2 and Si3N4, and the thickness of the gate oxide layer is 29-30nm.
[0010] In some embodiments, as a preferred technical solution, the N+ region is doped with high concentration of phosphorus ions by ion implantation.
[0011] In some embodiments, as a preferred technical solution, the P+ region is doped with high concentration of boron ions by ion implantation.
[0012] In some embodiments, as a preferred technical solution, the lightly doped N-type semiconductor region is an N-type semiconductor region, and the first conductive pillar is a P-type semiconductor region.
[0013] In some embodiments, as a preferred technical solution, a PN junction is formed between the P+ region and the N+ region.
[0014] The utility model provides a SiC-based VDMOSFET device resistant to single particle gate damage with the following beneficial effects:
[0015] In the utility model, by adding a buffer layer between the high-concentration substrate and the epitaxial layer, the occurrence of the single particle burnout effect can be suppressed without changing the basic characteristics of the VDMOSFET device.
[0016] In the utility model, by increasing the thickness of the gate oxide layer, the gate oxide is not easily broken down, and the equivalent capacitance between the gate and the drain can be reduced, so that the parameter performance of the device is well improved.
[0017] In the utility model, the leakage current will gradually decrease as the gate oxide thickness increases, reducing the probability of single particle gate penetration effect
[0018] In the utility model, the gate oxide layer adopts a composite gate dielectric layer structure, and the composite gate dielectric layer is SiO2 and Si3N4, which can reduce the triggering single particle gate penetration effect of the VDMOSFET device. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] The utility model is further described in detail below with reference to the accompanying drawings and specific implementation methods.
[0020] Figure 1 It is a structural schematic diagram of the utility model.
[0021] In the figure: 1. drain; 2. substrate; 3. N+ buffer layer; 4. N+ region; 5. lightly doped N-type semiconductor region; 6. P hydrazine; 7. P+ region; 8. source; 9. gate oxide layer; 10. first conductive column; 11. gate; 12. N- epitaxial layer. DETAILED DESCRIPTION
[0022] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other without conflict.
[0023] According to the attached Figure 1 , providing a SiC-based VDMOSFET device that is resistant to single-particle gate damage.
[0024] Example 1
[0025] A SiC-based VDMOSFET device resistant to single-particle gate damage comprises a substrate 2 and a drain 1 located below the substrate 2, wherein the substrate 2 is an N-type doped silicon substrate formed by doping a pentavalent element into a silicon wafer, the substrate 2 has conductive properties, and the substrate 2 is a high-concentration substrate; an N+ buffer layer 3 is provided on the upper surface of the substrate 2, the thickness of the N+ buffer layer 3 is 0.5 μm, and the occurrence of a single-particle burnout effect can be suppressed without changing the basic characteristics of the VDMOSFET device; an N- epitaxial layer 12 is etched on the upper surface of the N+ buffer layer 3, and the upper surface of the N- epitaxial layer 12 Ion implantation is performed on both sides to form P-type transistors 6. Each P-type transistor 6 has a P+ region 7 and an N+ region 4 inside. The doping concentration of the N+ region 4 is 10^16 / cm^3, and the implantation dose of the P+ region 7 is 10^15 / cm^2. Since the sensitivity of the single particle burnout effect is manifested in the influence on the base resistance of the parasitic tube, by increasing the implantation dose of the P+ region 7 and deepening the junction depth of the P+ region 7, the base resistance of the parasitic tube can be reduced, and the occurrence of single particle burnout can be reduced. The side surfaces of the P+ region 7 and the N+ region 4 are in contact, and a PN junction is formed between the P+ region 7 and the N+ region 4. The N-type transistor 6 has a PN junction with a N-type transistor 7. A first conductive column 10 is embedded between two P-type hydrides 6 in the inner part of the layer 12. The first conductive column 10 is a P-type semiconductor region. A lightly doped N-type semiconductor region 5 is provided between the first conductive column 10 and the P-type hydrides 6. The lightly doped N-type semiconductor region 5 is an N-type semiconductor region. A gate oxide layer 9 is formed on the upper surfaces of the lightly doped N-type semiconductor region 5, the first conductive column 10, part of the P-type hydrides 6, and part of the N+ region 4. The thickness of the gate oxide layer 9 is 29 nm. Considering that excessively thickening the thickness of the gate oxide layer 9 will affect the basic characteristics of the VDMOSFET device, the thickness of the gate oxide layer is controlled to be 29 nm. The leakage current will gradually decrease with time, reducing the triggered single-particle gate penetration effect, the electric field is not easily broken down, and at the same time, the equivalent capacitance between the gate and the drain can be reduced, and the parameter performance of the device is greatly improved. In addition, the gate oxide layer 9 adopts a composite gate dielectric layer structure, and the composite gate dielectric layer is SiO2 and Si3N4, which can reduce the triggered single-particle gate penetration effect of the VDMOSFET device; the gate oxide layer 9 is wrapped with a gate 11 on the left and right sides, and the gate oxide layer 9 has a source 8 on the left and right sides respectively, and the lower surface of the source 8 is in contact with the N-epitaxial layer 12, the P+ region 7, and the top of the P hydrazine 6.
[0026] Example 2
[0027] A SiC-based VDMOSFET device resistant to single-particle gate damage comprises a substrate 2 and a drain 1 located below the substrate 2, wherein the substrate 2 is an N-type doped silicon substrate formed by doping a pentavalent element into a silicon wafer, the substrate 2 has conductive properties, and the substrate 2 is a high-concentration substrate; an N+ buffer layer 3 is provided on the upper surface of the substrate 2, the thickness of the N+ buffer layer 3 is 0.5 μm, and the single-particle burnout effect can be suppressed without changing the basic characteristics of the VDMOSFET device; an N-epitaxial layer 12 is etched on the upper surface of the N+ buffer layer 3, and the N-epitaxial layer 12 Ion implantation is performed on both sides of the upper surface to form P-type hydrazine 6. Each P-type hydrazine 6 has a P+ region 7 and an N+ region 4 independently. The doping concentration of the N+ region 4 is 10^17 / cm^3, and the implantation dose of the P+ region 7 is 10^15 / cm^2. Since the sensitivity of the single particle burnout effect is manifested in the influence on the base resistance of the parasitic tube, by increasing the implantation dose of the P+ region 7 and deepening the junction depth of the P+ region 7, the base resistance of the parasitic tube can be reduced, and the occurrence of single particle burnout can be reduced; the side surfaces of the P+ region 7 and the N+ region 4 are in contact, and a P+ region 7 is formed between the P+ region 7 and the N+ region 4. N junction, a first conductive column 10 is embedded between two P hydrazines 6 inside the N- epitaxial layer 12, the first conductive column 10 is a P-type semiconductor region, a lightly doped N-type semiconductor region 5 is provided between the first conductive column 10 and the P hydrazines 6, the lightly doped N-type semiconductor region 5 is an N-type semiconductor region, a gate oxide layer 9 is formed on the upper surface of the lightly doped N-type semiconductor region 5, the first conductive column 10, part of the P hydrazines 6, and part of the N+ region 4, the thickness of the gate oxide layer 9 is 30nm, considering that excessively thickening the thickness of the gate oxide layer 9 will affect the basic characteristics of the VDMOSFET device, and thus, the gate oxide layer The thickness is controlled at 30nm, which can reduce the triggered single-particle gate punch-through effect, and the electric field is not easily broken down. At the same time, the equivalent capacitance between the gate and the drain can be reduced, and the parameter performance of the device is greatly improved. In addition, the gate oxide layer 9 adopts a composite gate dielectric layer structure, and the composite gate dielectric layer is SiO2 and Si3N4, which can reduce the triggered single-particle gate punch-through effect of the VDMOSFET device; the gate oxide layer 9 is wrapped with a gate 11 on the left and right sides, and the gate oxide layer 9 has a source 8 on the left and right sides respectively, and the lower surface of the source 8 is in contact with the N-epitaxial layer 12, the P+ region 7, and the top of the P hydrazine 6.
[0028] The working principle of this device is:
[0029] The thickness of the gate oxide layer 9 is 29-30nm. Considering that excessively thickening the thickness of the gate oxide layer 9 will affect the basic characteristics of the VDMOSFET device, the thickness of the gate oxide layer is controlled to be 29-30nm. Under the premise of not changing the basic characteristics of the VDMOSFET device, the leakage current will gradually decrease with time, reducing the triggering single-particle gate penetration effect. By increasing the thickness of the gate oxide layer, the electric field is not easily broken down, and the equivalent capacitance between the gate and the drain can be reduced, and the parameter performance of the device is well improved. In addition, the gate oxide layer 9 adopts a composite gate dielectric layer structure, and the composite gate dielectric layer is SiO2 and Si3N4, which can reduce the triggering single-particle gate penetration effect of the VDMOSFET device. By adding a buffer layer between the high-concentration substrate and the epitaxial layer, when the thickness of the buffer layer is 0.5μm, the occurrence of the single-particle burnout effect can be suppressed without changing the basic characteristics of the VDMOSFET device.
[0030] The electrical components that appear in this article are all electrical components that exist in reality.
[0031] Of course, the above description is not a limitation of the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions or substitutions made by ordinary technicians in this technical field within the essential scope of the present invention also fall within the protection scope of the present invention.
Claims
1. A SiC-based VDMOSFET device resistant to single particle gate damage, characterized in that: The invention comprises a substrate (2) and a drain electrode (1) located below the substrate (2); the upper surface of the substrate (2) has an N+ buffer layer (3); the upper surface of the N+ buffer layer (3) is etched with an N-epitaxial layer (12); both sides of the upper surface of the N-epitaxial layer (12) are ion-implanted to form P-type hydrazines (6); each of the P-type hydrazines (6) has a P+ region (7) and an N+ region (4) inside, the P+ region (7) and the side surface of the N+ region (4) are in contact; a first conductive column (12) is embedded between two P-type hydrazines (6) inside the N-epitaxial layer (12); 0), a lightly doped N-type semiconductor region (5) is provided between the first conductive column (10) and the P-type region (6), a gate oxide layer (9) is formed on the upper surfaces of the lightly doped N-type semiconductor region (5), the first conductive column (10), part of the P-type region (6), and part of the N+ region (4), a gate (11) is wrapped on the left and right sides of the gate oxide layer (9), and a source (8) is provided on the left and right sides of the gate oxide layer (9), respectively, and the lower surface of the source (8) is in contact with the N-epitaxial layer (12), the P+ region (7), and the upper side of the P-type region (6).
2. A SiC-based VDMOSFET device resistant to single particle gate damage according to claim 1, characterized in that: The substrate (2) is an N-type doped silicon substrate.
3. A SiC-based VDMOSFET device resistant to single particle gate damage according to claim 1, characterized in that: The thickness of the N+ buffer layer (3) is 0.5 μm.
4. The SiC-based VDMOSFET device resistant to single particle gate damage according to claim 1, characterized in that: The gate oxide layer (9) adopts a composite gate dielectric layer structure, the composite gate dielectric layer is SiO2 and Si3N4, and the thickness of the gate oxide layer (9) is 29-30 nm.
5. The SiC-based VDMOSFET device resistant to single particle gate damage according to claim 1, characterized in that: The N+ region (4) is doped with high concentration of phosphorus ions by ion implantation.
6. The SiC-based VDMOSFET device resistant to single particle gate damage according to claim 1, characterized in that: The P+ region (7) is doped with high concentration of boron ions by ion implantation.
7. The SiC-based VDMOSFET device resistant to single particle gate damage according to claim 1, characterized in that: The lightly doped N-type semiconductor region (5) is an N-type semiconductor region, and the first conductive column (10) is a P-type semiconductor region.
8. The SiC-based VDMOSFET device resistant to single particle gate damage according to claim 1, characterized in that: A PN junction is formed between the P+ region (7) and the N+ region (4).