Semiconductor device

Abstract

A semiconductor device includes a semiconductor substrate, a first fin portion, a second fin portion, and a shallow trench isolation region. The first fin portion is disposed on the semiconductor substrate. The second fin portion is disposed on the semiconductor substrate and adjacent to the first fin portion at a distance. The shallow trench isolation region is arranged between the first fin part and the second fin part, and the shallow trench isolation region comprises a first dielectric layer and a second dielectric layer. The first dielectric layer is disposed over a plurality of top surfaces and a plurality of sidewalls of the first fin portion and the second fin portion, and on the top surface of the semiconductor substrate between the first fin portion and the second fin portion. The second dielectric layer is disposed over the first dielectric layer.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] Semiconductor devices are used in a variety of electronic devices, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are generally manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate and patterning the various material layers using lithography techniques to form circuit components and elements on the semiconductor substrate.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be solved. Utility Model Content

[0004] According to some embodiments of the present disclosure, a semiconductor device includes a semiconductor substrate, a first fin, a second fin, and a shallow trench isolation region. The first fin is disposed on the semiconductor substrate. The second fin is disposed on the semiconductor substrate and is adjacent to the first fin at a distance. The shallow trench isolation region is disposed between the first fin and the second fin, and the shallow trench isolation region includes a first dielectric layer and a second dielectric layer. The first dielectric layer is disposed above multiple top surfaces and multiple sidewalls of the first fin and the second fin, and is located on the top surface of the semiconductor substrate between the first fin and the second fin. The second dielectric layer is disposed above the first dielectric layer.

[0005] According to some embodiments of the present disclosure, a semiconductor device includes a semiconductor substrate, a plurality of fins, and a shallow trench isolation region. A plurality of fins are disposed on the semiconductor substrate, and the fins are disposed adjacent to each other and spaced apart. The shallow trench isolation region is disposed above the semiconductor substrate and between the fins, and the shallow trench isolation region includes a first dielectric layer and a second dielectric layer. The first dielectric layer is disposed above the fins and surrounds the sidewalls of the fins. The second dielectric layer is disposed above the first dielectric layer, and the top surface of the second dielectric layer is lower than the top surface of the fins.

[0006] According to some embodiments of the present disclosure, a semiconductor device includes a plurality of first fins, a shallow trench isolation layer, a gate structure, and a source / drain region. The first fins extend from a substrate. The shallow trench isolation layer is located between adjacent first fins, and the top surface of the shallow trench isolation layer is lower than the top surface of the first fin. The gate structure is located in the adjacent first fins and above the shallow trench isolation layer. The source / drain region is located in the adjacent first fins, and the source / drain region is adjacent to the gate structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In practice, the sizes of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 is an example of a nanostructured field effect transistor (nanoFET) according to some embodiments and depicted in three dimensions;

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 and Fig. 6A is a cross-sectional view of an intermediate stage in the process of a nanoFET according to some embodiments;

[0010] Figure 6B An example of a line showing a change in carbon atomic percentage concentration relative to the depth of a dielectric layer after an annealing process is performed is shown;

[0011] Figure 6C is a cross-sectional view of an intermediate stage in the process of a nanoFET according to some embodiments;

[0012] Fig.6D is a cross-sectional view of an intermediate stage in the process of a nano FET according to another embodiment;

[0013] Figure 7 , Figure 8 , Fig. 9A , Fig. 9B , Fig. 9C , Fig. 10A , Fig. 10B , Fig. 10C , Fig.11A , Fig. 11B , Fig. 11C , Fig. 12A , Fig. 12B , Fig. 12C , Fig.13A , Fig. 13B , Fig. 13C , Fig.14A , Fig. 14B , Fig. 14C , Fig.15A , Fig. 15B , Fig. 15C , Fig.16A , Fig. 16B , Fig. 16C , Fig.17A , Fig. 17B , Fig. 17C , Fig.18A , Fig.18B , Fig.18C , Fig.19A , Fig.19B , Fig.19C , Fig. 20A , Fig. 20B , Fig. 20C , Fig.21A , Fig. 21B , Fig. 21C , Fig.22A , Fig. 22B , Fig. 22C , Fig.23A , Fig. 23B , Fig.23C , Fig.24A , Fig. 24B , Fig.24C , Fig.25A , Fig.25B and Fig.25C is a cross-sectional view of an intermediate stage in the fabrication of a nanoFET according to some embodiments; and

[0014] Fig.26A , Fig.26B and Fig.26C is a cross-sectional view of an intermediate stage in the process of a nanoFET according to another embodiment.

[0015]

Explanation of symbols

[0016] 50:Substrate

[0017] 50N: n-type region

[0018] 50P: p-type region

[0019] 52: Multi-layer stacking

[0020] 54: First semiconductor layer

[0021] 56: Second semiconductor layer

[0022] 58:Mask

[0023] 60: Groove

[0024] 62: semiconductor fin

[0025] 64: Nanostructure

[0026] 66: Nanostructure

[0027] 68: Channel Area

[0028] 70: Dielectric layer

[0029] 70A, 70B: Dielectric layer

[0030] 71: Dielectric layer

[0031] 72: STI area / isolation area / shallow trench isolation area

[0032] 73: Annealing process

[0033] 74: Sacrificial layer

[0034] 75: Line

[0035] 76: Sacrificial spacer

[0036] 78: Filling layer

[0037] 78A: Gasket

[0038] 78B: Filling material

[0039] 80: Dielectric cover layer

[0040] 82: Insulation fins

[0041] 84: Virtual gate layer

[0042] 86: Mask layer

[0043] 94: Virtual Gate

[0044] 96:Mask

[0045] 98: Gate spacer

[0046] 104: Source / drain groove / groove

[0047] 106: Internal spacer

[0048] 108: epitaxial source / drain region / source / drain region

[0049] 108A: cushion layer

[0050] 108B: Main floor

[0051] 108C: Finished layer

[0052] 112: Contact Etch Stop Layer / CESL

[0053] 114: first ILD / first interlayer dielectric layer

[0054] 116: Groove

[0055] 118,120: Opening

[0056] 124: Gate dielectric layer

[0057] 126: Gate electrode layer

[0058] 130: Gate structure

[0059] 131: Gate dielectric layer

[0060] 132: Gate electrode

[0061] 133: Quarantine

[0062] 134: Etch stop layer / ESL

[0063] 136: Second ILD / Second Interlayer Dielectric Layer

[0064] 142: Gate contact

[0065] 144: Source / drain contact

[0066] 152: top surface

[0067] 154: bottom surface

[0068] AA',BB',CC': section line

[0069] D1: Depth

[0070] H1: Height

[0071] W1: Width

[0072] T1, T2, T3, T4: thickness DETAILED DESCRIPTION

[0073] The following disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these specific examples are only examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are directly contacted, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be directly in contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0074] Additionally, for ease of description, spatially relative terms (e.g., "underlying," "beneath," "bottom," "overlying," "upper," and the like) may be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the accompanying figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0075] Various embodiments provide methods for forming high carbon shallow trench isolation (STI) regions. The method includes conformally depositing a first high carbon dielectric layer over and in a trench between two adjacent semiconductor fins. Next, a second dielectric layer is formed over the first dielectric layer to fill the trench between adjacent fins. An annealing process is performed to transform the second dielectric layer into a third high carbon dielectric layer (e.g., oxide). After the annealing process, the carbon atomic percentage concentration of the third dielectric layer is between 0.5% and 4%. Advantageous features of one or more embodiments of the present disclosure can allow the formation of an STI region including a high quality high carbon third dielectric layer, and the third dielectric layer is highly resistant to a subsequently performed etching process (e.g., an etching process using hydrofluoric acid (HF)). In addition, since the carbon atomic percentage concentration of the third dielectric layer is between 0.5% and 4%, a lower annealing temperature can be used during the annealing process to transform the second dielectric layer into the third dielectric layer, thereby allowing thermal budget control in advanced technology nodes that require a lower total thermal budget during device manufacturing. Additionally, the integrity and conversion efficiency of the second dielectric layer to the third dielectric layer can be improved by utilizing lower annealing temperatures and longer durations, such that, even when the trenches have a high aspect ratio, the third dielectric layer can have a more uniform oxide quality and composition (e.g., at the bottom of the trenches) after the conversion process.

[0076] Embodiments of the present disclosure are discussed in the context of forming nanostructure (including nanowires, nanosheets, and gate all around) field effect transistors (NSFETs), etc. However, the methods of the present disclosure may be applicable to other types of devices, such as finfield effect transistor (FinFET) devices. In addition, the methods of the present disclosure are not limited to STI regions, for example, various embodiments may be applicable to the formation of inter-layer dielectrics (ILDs) and low-k dielectrics.

[0077] Figure 1 An example of a nanoFET (eg, a nanowire FET, a nanosheet FET, etc.) is depicted in accordance with some embodiments. Figure 1This is a three-dimensional view, and some features of the nanoFET are omitted for clarity. The nanoFET can be a nanosheet field-effect transistor (NSFET), a nanowire field-effect transistor (NWFET), or a gate-all-around field-effect transistor (GAAFET).

[0078] The nanoFET includes a nanostructure 66 (e.g., a nanosheet, a nanowire, etc.), and the nanostructure 66 is located above a semiconductor fin 62 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructure 66 serves as a channel region of the nanoFET. The nanostructure 66 may include a p-type nanostructure, an n-type nanostructure, or a combination thereof. An isolation region 72 (e.g., a shallow trench isolation (STI) region) is disposed between adjacent semiconductor fins 62, and the semiconductor fins 62 may be above adjacent isolation regions 72 and protrude from between adjacent isolation regions 72. Although the isolation regions 72 are described / illustrated as being separated from the substrate 50, as used in the present disclosure, the term "substrate" may refer to a semiconductor substrate alone or a combination of a semiconductor substrate and one or more additional structures (e.g., isolation regions 72). In addition, although the bottom of the semiconductor fin 62 is illustrated as being separated from the substrate 50, the bottom of the semiconductor fin 62 may be a single and continuous material with the substrate 50. In the present disclosure, the semiconductor fin 62 refers to a portion extending from above and between adjacent isolation regions 72.

[0079] The gate structure 130 is located above the top surface of the semiconductor fin 62 and is disposed along the top surface, sidewalls, and bottom surface of the nanostructure 66. Epitaxial source / drain regions 108 are disposed on the semiconductor fin 62 at opposite sides of the gate structure 130. The epitaxial source / drain regions 108 can be shared between various semiconductor fins 62. For example, adjacent epitaxial source / drain regions 108 can be electrically connected, such as by coupling the epitaxial source / drain regions 108 with the same source / drain contact. The source / drain regions 108 can refer to a source or a drain individually or collectively depending on the context.

[0080] Insulating fins 82 (also referred to as hybrid fins or dielectric fins) are disposed over the isolation regions 72 and between adjacent epitaxial source / drain regions 108. During the formation of the epitaxial source / drain regions 108, the insulating fins 82 block epitaxial growth to prevent adjacent epitaxial source / drain regions 108 from joining. For example, in some embodiments, the insulating fins 82 may be formed to separate the epitaxial source / drain regions 108 of adjacent transistors.

[0081] Figure 1Reference cross-sectional lines used in subsequent figures are further depicted. Cross-sectional line AA' is along the longitudinal axis of semiconductor fin 62 and in the direction of current flow, for example, between epitaxial source / drain regions 108 of the nanoFET. Cross-sectional line BB' is along the longitudinal axis of gate structure 130 and in a direction, for example, perpendicular to the direction of current flow, between epitaxial source / drain regions 108 of the nanoFET. Cross-sectional line CC' is parallel to cross-sectional line BB' and extends through epitaxial source / drain regions 108 of the nanoFET. For clarity, subsequent figures will refer to the above-mentioned reference cross-sectional lines.

[0082] Figures 2 to 6A and FIG. 6C to FIG. 25C is a diagram of an intermediate stage in the fabrication of a nanoFET according to some embodiments. Figure 2 , Figure 3 and Figure 8 is a three-dimensional view. Fig. 9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A , Fig.19A , Fig. 20A , Fig.21A , Fig.22A , Fig.23A , Fig.24A and Fig.25A It is along Figure 1 A similar cross-sectional view is shown along reference section line AA'. Figure 4 , Figure 5 , Fig. 6A , Figure 6C , Fig.6D , Figure 7 , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B , Fig.18B , Fig.19B , Fig. 20B , Fig. 21B , Fig. 22B , Fig. 23B , Fig. 24B and Fig.25B It is along Figure 1 A similar cross-sectional view depicted by reference section line BB'. Fig. 9C , Fig. 10C , Fig. 11C , Fig. 12C , Fig. 13C , Fig. 14C , Fig. 15C , Fig. 16C , Fig. 17C , Fig.18C , Fig.19C , Fig. 20C , Fig. 21C , Fig. 22C , Fig.23C , Fig.24C and Fig.25C It is along Figure 1 A similar cross-sectional view shown by reference section line CC'.

[0083] exist Figure 2 In the invention, a substrate 50 for forming a nano FET is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor or a semiconductor-on-insulator (SOI) substrate, etc. The substrate 50 may be doped (e.g., with p-type or n-type impurities) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Generally speaking, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer or a silicon oxide layer. The insulator layer is disposed on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenic phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenide phosphide; or combinations thereof.

[0084] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor (e.g., an n-type nano FET), and the p-type region 50P can be used to form a p-type device, such as a PMOS transistor (e.g., a p-type nano FET). The n-type region 50N can be physically separated from the p-type region 50P (not separately shown), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be set between the n-type region 50N and the p-type region 50P. Although only one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be set.

[0085] The substrate 50 may be lightly doped with p-type or n-type impurities. An anti-punch-through implant (APT) may be performed on the upper portion of the substrate 50 to form an APT region. During the APT implant, impurities may be implanted into the substrate 50. The impurities may have a conductivity type opposite to the conductivity type of the source / drain regions that will be subsequently formed in the respective n-type regions 50N and p-type regions 50P. The APT region may extend below the source / drain region in the nanoFET. The APT region may be used to reduce leakage from the source / drain region to the substrate 50. In some embodiments, the doping concentration in the APT region is between 10 18 cm -3 Up to 10 19 cm -3 between.

[0086] A multilayer stack 52 is formed over the substrate 50. The multilayer stack 52 includes alternating first semiconductor layers 54 and second semiconductor layers 56. The first semiconductor layers 54 are formed of a first semiconductor material, and the second semiconductor layers 56 are formed of a second semiconductor material. The semiconductor materials can be selected from candidate semiconductor materials of the substrate 50. In the illustrated embodiment, the multilayer stack 52 includes three layers of the first semiconductor layers 54 and three layers of the second semiconductor layers 56. It should be understood that the multilayer stack 52 can include any number of first semiconductor layers 54 and any number of second semiconductor layers 56, for example, the first semiconductor layers 54 of the multilayer stack 52 can include one to ten layers, and the second semiconductor layers 56 of the multilayer stack 52 can include one to ten layers.

[0087] In the illustrated embodiment, and as will be described in more detail later, the first semiconductor layer 54 is removed and the second semiconductor layer 56 is patterned to form a channel region for a nano FET in the n-type region 50N and the p-type region 50P. The first semiconductor layer 54 is a sacrificial layer (or dummy layer) that is removed in a subsequent process to expose the top and bottom surfaces of the second semiconductor layer 56. The first semiconductor material of the first semiconductor layer 54 is a material with a high etching selectivity relative to the etching of the second semiconductor layer 56, such as silicon germanium. In some embodiments, the second semiconductor material of the second semiconductor layer 56 is a material suitable for n-type and p-type devices, such as silicon.

[0088] In some embodiments (not shown separately), the first semiconductor layer 54 will be patterned to form a channel region for the nanoFET in one region (e.g., the p-type region 50P), and the second semiconductor layer 56 will be patterned to form a channel region for the nanoFET in another region (e.g., the n-type region 50N). For example, the first semiconductor material of the first semiconductor layer 54 can be a material suitable for a p-type device, such as silicon germanium (e.g., Si xGe 1-x , where x can be between 0 and 1), pure germanium, III-V compound semiconductors or II-VI compound semiconductors, etc.; and the second semiconductor material of the second semiconductor layer 56 can be a material suitable for n-type devices, such as silicon, silicon carbide, III-V compound semiconductors or II-VI compound semiconductors, etc. The first semiconductor material and the second semiconductor material can have a high etching selectivity relative to each other, so that the first semiconductor layer 54 can be removed without removing the second semiconductor layer 56 in the n-type region 50N. And, the second semiconductor layer 56 can be removed without removing the first semiconductor layer 54 in the p-type region 50P. Each layer can have a small thickness, for example, a thickness between 5nm and 30nm.

[0089] exist Figure 3 , trenches 60 are patterned in substrate 50 and multilayer stack 52 to form semiconductor fins 62, nanostructures 64, and nanostructures 66. Semiconductor fins 62 are semiconductor strips patterned in substrate 50. Nanostructures 64 and nanostructures 66 include remaining portions of first semiconductor layer 54 and second semiconductor layer 56, respectively. Trench 60 may be patterned by any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or a combination thereof. Also, etching may be anisotropic.

[0090] After patterning the trenches 60 in the substrate 50 and the multilayer stack 52, and when viewed from a top view, the total area of ​​the semiconductor fins 62, the nanostructures 64, and the nanostructures 66 may be equal to the first area. When viewed from a top view, the total area of ​​the trenches 60 may be equal to the second area. The percentage of the first area to the second area (also referred to as the pattern density) may be between 5% and 95%. In some embodiments, the width W1 between adjacent semiconductor fins 62, between adjacent nanostructures 64, and between adjacent nanostructures 66 may be between 17nm and 500nm. In some embodiments, each semiconductor fin 62 and the nanostructures 64, 66 perpendicular to the semiconductor fins 62 may have a combined height H1 between 30nm and 400nm. For example, in one embodiment, the height H1 may be greater than 200nm. In addition, each trench 60 may have a depth D1 between 30nm and 400nm. For example, in one embodiment, the depth D1 may be greater than 200nm. Each trench 60 may have an aspect ratio (depth D1 / width W1 ) between 2 and 40.

[0091] The semiconductor fins 62 and nanostructures 64, 66 may be patterned by any suitable method. For example, the semiconductor fins 62 and nanostructures 64, 66 may be patterned using one or more lithography processes, including double patterning or multi-patterning processes. In general, double patterning or multi-patterning processes combine lithography processes with self-alignment processes, thereby allowing the creation of patterns having, for example, smaller pitches than can be obtained using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a lithography process, and spacers are formed along the patterned sacrificial layer using a self-alignment process, and then the sacrificial layer is removed, and the remaining spacers may be used as a mask 58 to pattern the semiconductor fins 62 and nanostructures 64, 66.

[0092] In some embodiments, the semiconductor fins 62 and the nanostructures 64, 66 have a width between 8 nm and 40 nm, respectively. In the illustrated embodiment, the semiconductor fins 62 and the nanostructures 64, 66 have substantially equal widths in the n-type region 50N and the p-type region 50P. In some embodiments, the semiconductor fins 62 and the nanostructures 64, 66 in one region (e.g., the n-type region 50N) are wider or narrower than the semiconductor fins 62 and the nanostructures 64, 66 in another region (e.g., the p-type region 50P). In addition, although each semiconductor fin 62 and the nanostructure 64, 66 are illustrated as having a consistent width throughout, in some embodiments, the semiconductor fins 62 and / or the nanostructures 64, 66 may have tapered sidewalls such that the width of each semiconductor fin 62 and the nanostructure 64, 66 increases continuously in a direction toward the substrate 50. In such embodiments, each layer of the nanostructures 64, 66 may have different widths and be trapezoidal in shape.

[0093] exist Figures 4 to 7 In the embodiment, STI regions 72 are formed over substrate 50 and between adjacent semiconductor fins 62, such as in trench 60. STI regions 72 are disposed around at least a portion of semiconductor fins 62, such that at least a portion of nanostructures 64, 66 protrude from between adjacent STI regions 72. In the illustrated embodiment, the top surface of STI regions 72 is below the top surface of semiconductor fins 62. In some embodiments, the top surface of STI regions 72 is above the top surface of semiconductor fins 62 or coplanar with the top surface of semiconductor fins 62 (within process variations).

[0094] exist Figure 4, a dielectric layer 70 is conformally formed on the mask 58, the semiconductor fin 62, the nanostructures 64, 66, and the sidewalls and bottom surface of the trench 60. For example, the dielectric layer 70 may be formed on the sidewalls of the mask 58, the semiconductor fin 62, and the nanostructures 64, 66. In addition, the dielectric layer 70 may be formed on the top surface of the substrate 50. The dielectric layer 70 may also be referred to as a dielectric liner later. The dielectric layer 70 may have a multi-layer structure and include a dielectric layer 70A and a dielectric layer 70B sequentially formed on the mask 58, the semiconductor fin 62, the nanostructures 64, 66, and the sidewalls and bottom surface of the trench 60. The dielectric layer 70A and the dielectric layer 70B may have different concentrations of carbon. In some embodiments, each dielectric layer 70A and dielectric layer 70B may include SiOCN or the like, and may be deposited by a process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). Each dielectric layer 70A and dielectric layer 70B are deposited at a process temperature between 100° C. and about 800° C. In one embodiment, dielectric layer 70A may have a thickness T1 between 0.5 nm and 10 nm, and dielectric layer 70B may have a thickness T2 between 0.5 nm and 10 nm. Although dielectric layer 70 is illustrated as a double layer including dielectric layer 70A and dielectric layer 70B, in one embodiment, dielectric layer 70 may include any number of dielectric layers (for example, one or more layers may include SiOCN, and each dielectric layer may have a different carbon concentration than the other layers). By conformally depositing the dielectric layer 70 over the mask 58, the semiconductor fins 62, the nanostructures 64, 66, and the sidewalls and bottom surfaces of the trench 60, effective and uniform step coverage of the dielectric layer 70 can be achieved, that is, the dielectric layer 70 can fully cover the components (such as the sidewalls and bottom surfaces of the trench 60).

[0095] The dielectric layer 70A may include SiO x C y N z , where x can be between 0 and 10, y can be between 0 and 10, and z can be between 0 and 10. The composition of dielectric layer 70A can be graded, such that dielectric layer 70A is characterized by a composition that gradually changes with the vertical height of dielectric layer 70A, for example, the x, y, and z values ​​can increase or decrease. For example, the x, y, and z values ​​can gradually increase or gradually decrease as the vertical direction moves away from the underlying substrate 50.

[0096] The dielectric layer 70B may include SiO a C b N c, where a can be between 0 and 10, b can be between 0.1 and 10, and c can be between 0 and 10. The composition of dielectric layer 70B can be graded, such that dielectric layer 70B is characterized by a composition that gradually changes with the vertical height of dielectric layer 70B, for example, the values ​​of a, b, and c can increase or decrease. For example, the values ​​of a, b, and c can gradually increase or decrease as the dielectric layer 70A moves away from the underlying substrate 50 in the vertical direction. In one embodiment, dielectric layer 70A can have a higher carbon content than dielectric layer 70B. For example, a dielectric layer comprising SiO x C y N z The y value of the dielectric layer 70A is higher than that of the SiO a C b N c The b value of dielectric layer 70B is .

[0097] exist Figure 5 In the embodiment, a dielectric layer 71 is formed in the trench 60 and above the dielectric layer 70. The dielectric layer 71 can be formed by a flowable CVD (FCVD) process, for example, in a remote plasma system, by depositing a CVD material and performing post-curing to convert the dielectric layer 71 into another material, such as an oxide. In one embodiment, the dielectric layer 71 is formed to fill the trench 60, and the excess dielectric material in the dielectric layer 71 is disposed above the mask 58, the semiconductor fin 62, the nanostructures 64, 66, and above the topmost surface of the dielectric layer 70. In one embodiment, the dielectric layer 70 is disposed between the dielectric layer 71 and the substrate 50, the mask 58, the semiconductor fin 62, and the nanostructures 64, 66, and isolates the dielectric layer 71 from the substrate 50, the mask 58, the semiconductor fin 62, and the nanostructures 64, 66. Furthermore, dielectric layer 70 physically contacts dielectric layer 71, substrate 50, mask 58, semiconductor fin 62, and nanostructures 64, 66. In an embodiment, dielectric layer 71 may have a thickness T3 between 100 nm and 600 nm in trench 60 (e.g., from the bottommost surface of dielectric layer 71 to the topmost surface of dielectric layer 71).

[0098] The FCVD process for forming the dielectric layer 71 may include exposing the surface of the trench 60 and the dielectric layer 70 to a silicon-containing precursor, a nitrogen-containing precursor, and an oxygen-containing precursor. In some embodiments, the silicon-containing precursor is a silylamine, such as trisilylamine (Si3NH9), etc. One or more carrier gases may also be included in the silicon-containing precursor. The carrier gas may include helium (He), argon (Ar), nitrogen (N2), etc., or a combination thereof.

[0099] The nitrogen-containing precursor may include NH3, etc. In some embodiments, the nitrogen-containing precursor is activated into plasma in a remote plasma system (RPS) outside the deposition chamber. The oxygen-containing precursor may include O2, etc., and the oxygen-containing precursor may also be activated into plasma in the RPS. In some embodiments, the plasma generated in the RPS is brought into the deposition chamber by a carrier gas, and the carrier gas includes He, Ar, N2, etc. or a combination thereof.

[0100] The silicon-containing precursor, the oxygen-containing precursor, and the nitrogen-containing precursor are mixed and reacted to deposit a dielectric layer 71 including silicon, oxygen, and nitrogen in the trench 60 and over the dielectric layer 70. After the dielectric layer 71 is formed, the dielectric layer 71 may be exposed to a temperature between 10° C. and 500° C. to help crosslink and cure the dielectric layer 71.

[0101] Fig. 6AIt is depicted that after exposing the dielectric layer 71 to a temperature between 10° C. and 500° C. to help crosslink and cure the dielectric layer 71, an annealing process 73 is performed to cure or treat the dielectric layer 71, and the dielectric layer 71 is transformed, for example, by an oxidation process. The annealing process 73 may include one or more intermediate annealing steps to transform the dielectric layer 71 into a high carbon oxide. The annealing process 73 may include performing one or more intermediate annealing steps in an oxygen-containing environment. For example, the one or more intermediate annealing steps of the annealing process 73 may be performed while the dielectric layer 71 is exposed to an oxygen-containing environment (e.g., an environment that may include wet steam, H2 and O2 gases, hydrogen peroxide (H2O2), H2 and O2 radicals, O2 radicals, or H2O radicals, etc.). In one embodiment, each intermediate annealing step may be performed by exposing the dielectric layer 71 to an oxygen-containing environment that is different from the oxygen-containing environment to which the dielectric layer 71 is exposed during other intermediate annealing steps. During the annealing process 73, the environment of one or more intermediate annealing steps may also include other gases, such as N2, etc. In some embodiments, the annealing process 73 may be performed at a temperature greater than 300°C and for a duration between 0.1 hours and 24 hours. In some embodiments, the annealing process 73 may be performed at a pressure between about 0.01 atm and 25 atm. The annealing process 73 may transform the dielectric layer 71 so that after the annealing process 73 is performed, the dielectric layer 71 includes silicon and oxygen. During the annealing process 73, carbon from the dielectric layer 70 may be released or diffused into the dielectric layer 71 so that after the annealing process 73, the dielectric layer 71 includes high carbon silicon oxide. Since the dielectric layer 71 is disposed above the dielectric layer 70, carbon may diffuse from the dielectric layer 70 into the dielectric layer 71 and prevent carbon from being degassed from the dielectric layer 70 into the annealing chamber. This is beneficial to the process because it prevents contamination due to outgassing, which could potentially reduce the yield and performance of the manufactured device.

[0102] During the annealing process 73, carbon from the dielectric layer 70 may diffuse or release into the dielectric layer 71, so that the dielectric layer 70 is partially or completely consumed during the annealing process 73. For example, after the annealing process 73, the dielectric layer 70 may be completely consumed, and there is no dielectric layer 70 (as described later). Figure 6C In one embodiment, after the annealing process 73, the dielectric layer 70 may be partially consumed, so that after the annealing process 73, the thickness of the dielectric layer 70 is less than the thickness of the dielectric layer 70 before the annealing process 73 (as shown in FIG. Fig.6D In the embodiment where the dielectric layer 70 includes a dielectric layer 70A and a dielectric layer 70B, after the annealing process 73, one or both of the dielectric layer 70A and the dielectric layer 70B may be partially or completely consumed.

[0103] In some embodiments, the annealing process 73 can help break Si-N and Si-H bonds in the dielectric layer 71 and promote the formation of Si-Si and Si-O bonds. After the annealing process 73, the carbon atomic percentage concentration of the dielectric layer 71 is between 0.5% and 4%. The carbon atomic percentage concentration of the dielectric layer 71 at the topmost surface 152 of the dielectric layer 71 between adjacent semiconductor fins 62 is the smallest (e.g., 0.5%). The carbon atomic percentage concentration of the dielectric layer 71 at the bottommost surface 154 of the dielectric layer 71 between adjacent semiconductor fins 62 is the largest (e.g., 4%). The topmost surface 152 can be vertically above and overlap the bottommost surface 154.

[0104] Figure 6B The dielectric layer 71 is shown along the Fig. 6A The line 75 in FIG. 7 is an example of the change in the carbon atomic percentage concentration. Figure 6B It can be understood that the carbon atomic percentage concentration of the dielectric layer 71 is the largest (e.g., 4%) at the bottommost surface 154 of the dielectric layer 71, and the carbon atomic percentage concentration of the dielectric layer 71 is the smallest (e.g., 0.5%) at the topmost surface 152 of the dielectric layer 71. The carbon atomic percentage concentration of the dielectric layer 71 decreases in the vertical direction moving from the bottommost surface 154 to the topmost surface 152.

[0105] The advantages of the present disclosure can be obtained by forming a dielectric layer 70 including a dielectric layer 70A and a dielectric layer 70B over the mask 58, the semiconductor fins 62, the nanostructures 64, 66, and on the sidewalls and bottom surface of the trench 60. Each of the dielectric layer 70A and the dielectric layer 70B includes SiOCN. Next, a dielectric layer 71 is formed in the trench 60 and over the dielectric layer 70, so that the dielectric layer 71 fills the trench 60. Then, an annealing process 73 is performed to convert the dielectric layer 71 into an oxide, wherein in the annealing process 73, the carbon in the dielectric layer 70 is released or diffused into the dielectric layer 71. After the annealing process 73, the carbon atomic percentage concentration of the dielectric layer 71 is between 0.5% and 4%. The advantageous features of one or more embodiments of the present disclosure can allow the dielectric layer 71 to be converted into a high-quality high-carbon oxide layer, and the dielectric layer 71 is resistant to subsequent etching processes (for example, in Figure 7 The etching process using hydrofluoric acid (HF) described in ) is highly resistant.

[0106] In addition, since the carbon in the dielectric layer 70 is released or diffused into the dielectric layer 71 during the annealing process 73, the carbon atomic percentage concentration of the dielectric layer 71 is between 0.5% and 4% after the annealing process 73, and a lower annealing temperature can be used during the annealing process 73 to convert the dielectric layer 71 into an oxide. In this way, thermal budget control is allowed for advanced technology nodes that require a lower total thermal budget during device manufacturing. In addition, when the dielectric layer 71 has a carbon atomic percentage concentration below 0.5%, if an annealing temperature lower than that used in the annealing process 73 is used, the dielectric layer 71 may not be completely converted into an oxide. In addition, when the dielectric layer 71 has a carbon atomic percentage concentration greater than 4%, the dielectric layer 71 may have a negative impact on a subsequently performed etching process (for example, in Figure 7 ) has too high a resistance to the etching process using hydrofluoric acid (HF) described in , which will negatively affect the formation of STI region 72. In addition, since a lower annealing temperature and a longer duration can be used, dielectric layer 71 can be completely and effectively converted, so that dielectric layer 71 has a more uniform oxide quality and composition (for example, at the bottom of trench 60), so that even when trench 60 has a high aspect ratio, the shape of each trench 60 will not change after the conversion process.

[0107] exist Figure 7 In the embodiment, a removal process is then performed on the dielectric layers 70 and 71 to remove excess material above the nanostructures 64 and 66. In some embodiments, the removal can be performed using a planarization process, such as chemical mechanical polishing (CMP), an etch-back process, or a combination thereof. In some embodiments, the planarization process can expose the mask 58 or remove the mask 58. After the planarization process, the dielectric layers 70 and 71 are coplanar with the top surfaces of the mask 58 or the nanostructures 64 and 66 (within process variations). Therefore, the top surfaces of the mask 58 (if present) or the nanostructures 64 and 66 are exposed to the dielectric layer 70. In the embodiment shown, the mask 58 is retained on the nanostructures 64 and 66.

[0108] Then, the dielectric layers 70 and 71 are recessed to form STI regions 72, which include the remaining portions of the dielectric layers 70 and 71. The dielectric layers 70 and 71 are recessed so that at least a portion of the nanostructures 64, 66 protrude from between adjacent portions of the dielectric layer 70. Further, by appropriate etching, the top surface of the STI region 72 can have a flat surface (as shown), a convex surface, a concave surface (e.g., recessed), or a combination thereof. The dielectric layers 70 and 71 can be recessed using any acceptable etching process, such as an etching process that is selective to the material of the dielectric layers 70 and 71 (e.g., selectively etching the material of the dielectric layers 70 and 71 at a faster etching rate than the material of the semiconductor fins 62 and the nanostructures 64, 66). For example, the oxide removal can be performed using diluted hydrofluoric acid (dHF) as an etchant. In one embodiment, after the dielectric layer 70 and the dielectric layer 71 are recessed to form the STI region 72, the STI region 72 may have a thickness T4 in the trench 60 (e.g., from the bottommost surface of the STI region 72 to the topmost surface of the STI region 72), and the thickness T4 is between 160 nm and 20 nm. In one embodiment, the ratio of the thickness T4 of the STI region 72 to the thickness T3 of the dielectric layer 71 is between 25 and 1.5. In one embodiment, the ratio of the thickness T4 to the combined height H1 of each semiconductor fin 62 and the nanostructures 64 and 66 vertically above the semiconductor fin 62 may be between 15 and 1.2. The dielectric layer 70 may not be drawn in subsequent figures. As shown in FIG. Fig. 6A As shown, the dielectric layer 71 is converted into a high-quality high-carbon oxide layer that is highly resistant to etching processes using hydrofluoric acid (HF), and as such, the advantages of the present disclosure can be achieved. For example, during the recessing of the dielectric layer 70 and the dielectric layer 71 to form the STI region 72, a reduced amount of the dielectric layer 71 is removed (also referred to as oxide loss), thereby allowing the remaining STI region 72 to fully protect the sidewalls of the semiconductor fin 62. For example, during the subsequent process of forming the epitaxial source / drain region 108 (described later), the sidewalls of the semiconductor fin 62 are substantially protected. 18A to 18C ), the epitaxial source / drain regions 108 formed in adjacent semiconductor fins 62 are sufficiently isolated from the semiconductor fins 62 and prevented from merging with each other by the STI regions 72. Therefore, the performance of the device can be improved.

[0109] The aforementioned Figures 2 to 7The process described in is just one example of how the semiconductor fin 62 and the nanostructures 64, 66 can be formed. In some embodiments, the semiconductor fin 62 and / or the nanostructures 64, 66 can be formed using a masking and epitaxial growth process. For example, a dielectric layer can be formed above the top surface of the substrate 50, and a trench can be etched through the dielectric layer to expose the substrate 50 below. Epitaxial growth can be performed in the trench to form the epitaxial structure, and the dielectric layer can be recessed to allow the epitaxial structure to protrude from the dielectric layer to form the semiconductor fin 62 and / or the nanostructure 64, 66. The epitaxial structure can include the aforementioned alternating semiconductor materials, such as a first semiconductor material and a second semiconductor material. In some embodiments where the epitaxial structure is formed by epitaxial growth, the epitaxially grown material can be doped in situ during growth, which can avoid previous and / or subsequent implantation, although in situ doping and implantation doping can also be used together.

[0110] In addition, appropriate wells (not separately shown) may be formed in the nanostructures 64, 66, the semiconductor fins 62, and / or the substrate 50. The wells may have a conductivity type opposite to that of the source / drain regions that will be subsequently formed in each of the n-type region 50N and the p-type region 50P. In some embodiments, a p-type well is formed in the n-type region 50N, and an n-type well is formed in the p-type region 50P. In some embodiments, a p-type well or an n-type well is formed in both the n-type region 50N and the p-type region 50P.

[0111] In embodiments with different well types, different implantation steps for the n-type region 50N and the p-type region 50P may be implemented using a mask such as a photoresist (not shown separately). For example, a photoresist may be formed over the semiconductor fins 62, nanostructures 64, 66, and STI regions 72 in the n-type region 50N. The photoresist may be patterned to expose the p-type region 50P. The photoresist may be formed using a spin coating technique and may be patterned using acceptable lithography techniques. Once the photoresist is patterned, an n-type impurity implantation may be performed in the p-type region 50P, and the photoresist may serve as a mask to substantially prevent the n-type impurity from being implanted into the n-type region 50N. The n-type impurity implanted into the region may be phosphorus, arsenic, or antimony, and the n-type impurity concentration may be between 10 13 cm -3 Up to 10 14 cm -3 After implantation, the photoresist may be removed, for example, by any acceptable ashing process.

[0112] After or before the p-type region 50P is implanted, a mask such as a photoresist (not shown separately) is formed over the semiconductor fins 62, nanostructures 64, 66, and STI regions 72 in the p-type region 50P. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using a spin coating technique and can be patterned using an acceptable lithography technique. Once the photoresist is patterned, a p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can act as a mask to substantially prevent the p-type impurity from being implanted into the p-type region 50P. The p-type impurity implanted into the region can be boron, boron fluoride, or indium, etc., and the p-type impurity concentration is between 10 13 cm -3 Up to 10 14 cm -3 After implantation, the photoresist may be removed, for example, by any acceptable ashing process.

[0113] After implantation of the n-type region 50N and the p-type region 50P, annealing may be performed to repair damage caused by the implantation and to activate the implanted p-type and / or n-type impurities. In some embodiments where the semiconductor fins 62 and / or nanostructures 64, 66 are formed into epitaxial structures by epitaxial growth, the epitaxially grown material may be in-situ doped during growth, thus avoiding previous and / or subsequent implantation, although in-situ doping and implantation doping may also be used together.

[0114] Figure 8 The dielectric layer 70 and the dielectric layer 71 are recessed to form the STI region 72, and Figure 8 for Figure 7 A three-dimensional view of the structure shown.

[0115] FIG. 9A to FIG. 25C Various additional steps in the process of an example device are depicted. FIG. 9A to FIG. 25C Features in either the n-type region 50N or the p-type region 50P are depicted. For example, the structure shown may be applicable to both the n-type region 50N and the p-type region 50P. The differences in the structures of the n-type region 50N and the p-type region 50P, if any, are described in the text accompanying the respective figures. As described in more detail below, the insulating fins 82 will be formed between the semiconductor fins 62. Fig. 9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A , Fig.19A , Fig. 20A , Fig.21A , Fig.22A , Fig.23A , Fig.24A and Fig.25A Semiconductor fins 62 and structures formed on semiconductor fins 62 are depicted. Fig. 9B , Fig. 9C , Fig. 10B , Fig. 10C , Fig. 11B , Fig. 11C , Fig. 12B , Fig. 12C , Fig. 13B , Fig. 13C , Fig. 14B , Fig. 14C , Fig. 15B , Fig. 15C , Fig. 16B , Fig. 16C , Fig. 17B , Fig. 17C , Fig.18B , Fig.18C , Fig.19B , Fig.19C , Fig. 20B , Fig. 20C , Fig. 21B , Fig. 21C , Fig. 22B , Fig. 22C , Fig. 23B , Fig.23C , Fig. 24B , Fig.24C , Fig.25B and Fig.25C Two semiconductor fins 62 and a portion between the insulating fin 82 and the STI region 72 in the corresponding cross-sectional lines are respectively illustrated.

[0116] exist 9A to 9C In the embodiment, the sacrificial layer 74 is conformally formed over the mask 58, the semiconductor fin 62, the nanostructures 64, 66 and the STI region 72. The sacrificial layer 74 may be formed of a semiconductor material (e.g., one of the candidate semiconductor materials selected from the substrate 50), and the sacrificial layer 74 may be grown by a process such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), and may be deposited by a process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). For example, the sacrificial layer 74 may be formed of silicon or silicon germanium.

[0117] exist FIG. 10A to FIG. 10CIn the embodiment of the present invention, the sacrificial layer 74 is patterned using an etching process to form a sacrificial spacer 76, and the etching process is, for example, dry etching, wet etching, or a combination thereof. The etching process can be anisotropic. Due to the etching process, the portion of the sacrificial layer 74 above the mask 58 and the nanostructures 64, 66 is removed, and the STI region 72 between the nanostructures 64, 66 is partially exposed. The sacrificial spacer 76 is disposed above the STI region 72 and further disposed on the sidewalls of the mask 58, the semiconductor fin 62, and the nanostructures 64, 66.

[0118] In subsequent process steps, the dummy gate layer 84 may be deposited over a portion of the sacrificial spacer 76 (as described below). FIG. 15A to FIG. 15C ), and the dummy gate layer 84 may be patterned to provide a dummy gate 94 including a lower portion of the sacrificial spacer 76 (as described later). FIG. 16A to FIG. 16C As described above). These dummy gates 94 (e.g., patterned portions of the dummy gate layer 84 and portions of the sacrificial spacers 76) can then be replaced with functional gate stacks. Specifically, the sacrificial spacers 76 serve as temporary spacers during the process to define the boundaries of the insulating fins 82, and the sacrificial spacers 76 and the nanostructures 64 are subsequently removed and replaced by a gate structure wrapped around the nanostructures 66. The sacrificial spacers 76 are formed of a material having a high etch selectivity relative to the etching of the material of the nanostructures 66. For example, the sacrificial spacers 76 can be formed of the same semiconductor material as the nanostructures 64, so that the sacrificial spacers 76 and the nanostructures 64 can be removed in a single process step. Alternatively, the sacrificial spacers 76 can be formed of a material different from the nanostructures 64.

[0119] FIG. 11A to FIG. 13C The insulating fin 82 (also referred to as a hybrid fin or dielectric fin) is shown formed between the sacrificial spacers 76 adjacent to the semiconductor fin 62 and the nanostructures 64, 66. The insulating fin 82 can allow the subsequently formed source / drain regions (described below) to be 18A to 18C The ) are insulated and physically separated from each other.

[0120] exist FIG. 11A to FIG. 11CIn the embodiment of the present invention, a liner 78A and a fill material 78B are formed over the structure, and the liner 78A and the fill material 78B are collectively referred to as a fill layer 78. As described in more detail below, the liner 78A and the fill material 78B are patterned and collectively form a portion of the insulating fin 82. The liner 78A is conformally deposited on the exposed surfaces of the STI region 72, the mask 58, the semiconductor fin 62, the nanostructures 64, 66, and the sacrificial spacer 76 by an acceptable deposition process (e.g., atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD), etc.). The liner 78A can be formed of one or more dielectric materials that have a high etch selectivity for etching the semiconductor fin 62, the nanostructures 64, 66, and the sacrificial spacer 76, such as nitrides (e.g., silicon nitride, silicon carbonitride, silicon carbon nitride oxide, etc.). The liner 78A may reduce oxidation of the sacrificial spacer 76 during the subsequent formation of the fill material 78B, which is beneficial for the subsequent removal of the sacrificial spacer 76 .

[0121] Next, fill material 78B is formed over liner 78A to fill the remaining area between semiconductor fin 62 and nanostructures 64, 66 that is not filled by sacrificial spacer 76 or liner 78A. Fill material 78B may form the bulk of the lower portion of insulating fin 82 (see FIG. 13A to FIG. 13C ), so that the subsequently formed source / drain regions (see Fig.18C ) are insulated from each other. The filling material 78B may be formed by an acceptable deposition process, such as ALD, CVD, or PVD. The filling material 78B may be formed of one or more dielectric materials, and the dielectric material has a high etching selectivity to the etching of the semiconductor fin 62, the nanostructures 64, 66, the sacrificial spacer 76, and the liner 78A, such as an oxide (e.g., silicon oxide, silicon oxynitride, silicon oxycarbonitride, silicon oxycarbide, or a combination thereof).

[0122] exist FIG. 12A to FIG. 12C In the embodiment of the present invention, one or more acceptable planarization and / or etching processes may be used to remove the upper portion of the liner 78A and the fill material 78B above the top surface of the mask 58. The etching process may be selective to the liner 78A and the fill material 78B (e.g., by selectively etching the liner 78A and the fill material 78B at a faster etching rate than the sacrificial spacer 76 and / or the mask 58). After etching, the top surface of the liner 78A and the fill material 78B may be lower than the top surface of the mask 58. In other embodiments, the fill material 78B may be recessed below the top surface of the mask 58 while the liner 78A remains at the same height as the mask 58.

[0123] FIG. 13A to FIG. 13CA dielectric cap layer 80 is shown formed on the liner 78A and the filling material 78B to form an insulating fin 82. The dielectric cap layer 80 can fill the remaining area above the liner 78A, above the filling material 78B, and between the sidewalls of the mask 58. The dielectric cap layer 80 can be formed by an acceptable deposition process (such as ALD, CVD, or PVD, etc.). The dielectric cap layer 80 can be formed of one or more dielectric materials, and the dielectric material has a high etching selectivity to the etching of the semiconductor fin 62, the nanostructure 64, 66, the sacrificial spacer 76, the liner 78A, and the filling material 78B. For example, the dielectric cap layer 80 can include a high-k material (such as hafnium oxide, zirconium oxide, zirconium oxide aluminum, hafnium aluminum oxide, hafnium silicon oxide, aluminum oxide, or a combination thereof). In this way, the dielectric cap layer 80 can be used as a hard mask to protect the underlying dielectric liner 78A and the filling material 78B from excessive etching in subsequent processes.

[0124] Initially, a dielectric cap layer 80 may be formed to cover the mask 58 and the nanostructures 64, 66. Next, a removal process is performed to remove excess material of the dielectric cap layer 80. In some embodiments, a planarization process such as CMP, an etch-back process, a combination thereof, or the like may be utilized. The planarization process exposes the mask 58 so that the mask 58, the sacrificial spacers 76, and the top surface of the dielectric cap layer 80 are coplanar (within process variations). In the illustrated embodiment, the mask 58 is retained after the planarization process. In some embodiments, part or all of the mask 58 may also be removed by the planarization process.

[0125] Accordingly, the insulating fin 82 is formed between the sacrificial spacers 76 and in contact with the sacrificial spacers 76. The insulating fin 82 includes a liner 78A, a filling material 78B, and a dielectric cap layer 80. The sacrificial spacers 76 separate the insulating fin 82 from the nanostructures 64 and 66, and the size of the insulating fin 82 can be adjusted by adjusting the thickness of the sacrificial spacers 76.

[0126] exist FIG. 14A to FIG. 14C In the embodiment of the present invention, the mask 58 is removed, for example, using an etching process. The etching process may be a wet etch, and the wet etch selectively removes the mask 58 and does not significantly etch the insulating fins 82. The etching process may be anisotropic. In addition, the etching process (or a separate selective etching process) may be used to reduce the height of the sacrificial spacer 76 to a height that is similar to that of the stacked nanostructures 64, 66 (e.g., the same height within process variations). In one or more processes, the topmost surfaces of the stacked nanostructures 64, 66 and the sacrificial spacer 76 may be exposed and may be lower than the topmost surface of the insulating fins 82.

[0127] exist FIG. 15A to FIG. 15CIn the embodiment, a dummy gate layer 84 is formed on the insulating fin 82, the sacrificial spacer 76 and the nanostructures 64, 66. Since the nanostructures 64, 66 and the sacrificial spacer 76 are lower than the insulating fin 82, the dummy gate layer 84 can be arranged along the exposed sidewalls of the insulating fin 82. The dummy gate layer 84 can be deposited and then planarized (e.g., CMP) the dummy gate layer 84. The dummy gate layer 84 can be formed of a conductive or non-conductive material, such as amorphous silicon, polycrystalline silicon, polycrystalline silicon-germanium (poly-SiGe), a metal, a metal nitride, a metal silicide or a metal oxide. The dummy gate layer 84 can be deposited by processes such as PVD or CVD. The dummy gate layer 84 can also be formed of a semiconductor material (e.g., one of the candidate semiconductor materials selected from the substrate 50), and the dummy gate layer 84 can be grown by processes such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), and deposited by processes such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The dummy gate layer 84 may be formed of a material having a high etching selectivity to etching of an insulating material (e.g., the insulating fin 82). A mask layer 86 may be deposited over the dummy gate layer 84. The mask layer 86 may be formed of one or more dielectric material layers, such as silicon nitride or silicon oxynitride. In this example, a single dummy gate layer 84 and a single mask layer 86 are formed across the n-type region 50N and the p-type region 50P.

[0128] exist FIG. 16A to FIG. 16C In the embodiment of the present invention, the mask layer 86 is patterned using acceptable lithography and etching techniques to form a mask 96. The pattern of the mask 96 is then transferred to the dummy gate layer 84 by any acceptable etching technique to form a dummy gate 94. The dummy gate 94 will cover the top surface of the nanostructures 64, 66 that will be used to form the channel region 68. The pattern of the mask 96 can be used to physically separate adjacent dummy gates 94. The dummy gate 94 can also have a longitudinal direction that is substantially perpendicular (within process variations) to the longitudinal direction of the semiconductor fin 62. The mask 96 can be selectively removed after patterning, for example by any acceptable etching technique.

[0129] The sacrificial spacers 76 and the dummy gate 94 collectively extend along the portion of the nanostructures 66 that will be patterned (the portion that will form the channel region 68). The sacrificial spacers 76 and the dummy gate 94 will be replaced by a subsequently formed gate structure.

[0130] As described above, the dummy gate 94 may be formed of a semiconductor material. In such embodiments, the nanostructure 64, the sacrificial spacer 76, and the dummy gate 94 are all formed of a semiconductor material. In some embodiments, the nanostructure 64 and the sacrificial spacer 76 are formed of a first semiconductor material (e.g., silicon germanium), and the dummy gate 94 is formed of a second semiconductor material (e.g., silicon), so that during the replacement gate process, the dummy gate 94 may be removed in a first etching step, and the nanostructure 64 and the sacrificial spacer 76 may be removed together in a second etching step. When the nanostructure 64 and the sacrificial spacer 76 are formed of silicon germanium: the nanostructure 64 and the sacrificial spacer 76 may have similar germanium concentrations, or the nanostructure 64 may have a higher germanium concentration than the sacrificial spacer 76, or the sacrificial spacer 76 may have a higher germanium concentration than the nanostructure 64. In some embodiments, the nanostructure 64 is formed of a first semiconductor material (e.g., silicon germanium), while the sacrificial spacer 76 and the dummy gate 94 are formed of a second semiconductor material (e.g., silicon), such that during the replacement gate process, the sacrificial spacer 76 and the dummy gate 94 can be removed together in a first etching step, while the nanostructure 64 can be removed in a second etching step.

[0131] The gate spacer 98 is formed over the nanostructures 64, 66 and on the exposed sidewalls of the mask 96 (if present) and the dummy gate 94. The gate spacer 98 can be formed by conformally depositing one or more dielectric materials on the dummy gate 94 and then etching the dielectric material. Acceptable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbonitride, etc. Acceptable dielectric materials may be formed by a conformal deposition process, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or plasma-enhanced atomic layer deposition (PEALD). Other insulating materials formed by any acceptable process may be used. Any acceptable etching process (e.g., dry etching, wet etching, etc., or a combination thereof) may be performed to pattern the dielectric material. The etching may be anisotropic. When etching, the dielectric material has a portion that remains on the sidewall of the dummy gate 94 (thus forming the gate spacer 98). After etching, the gate spacers 98 may have curved sidewalls or may have straight sidewalls.

[0132] In addition, implantation may be performed to form lightly doped source / drain (LDD) regions (not shown separately). In embodiments having different device types, similar to the implantation for the well described previously, a mask (not shown separately), such as a photoresist, may be formed over the n-type region 50N, and the p-type region 50P may be exposed, and an appropriate type of impurity (e.g., a p-type impurity) may be implanted into the semiconductor fin 62 and / or nanostructures 64, 66 exposed in the p-type region 50P. The mask may then be removed. Subsequently, a mask (not shown separately), such as a photoresist, may be formed over the p-type region 50P, and the n-type region 50N may be exposed, and an appropriate type of impurity (e.g., an n-type impurity) may be implanted into the semiconductor fin 62 and / or nanostructures 64, 66 exposed in the n-type region 50N. The mask may then be removed. The n-type impurity may be any of the aforementioned n-type impurities, and the p-type impurity may be any of the aforementioned p-type impurities. During the implantation, the channel region 68 remains covered by the dummy gate 94, so that the channel region 68 remains substantially free of the impurities implanted to form the LDD region. The LDD region may have a thickness between 10 15 cm -3 Up to 10 19 cm -3 Annealing can be used to repair damage caused by implantation and activate the implanted impurities.

[0133] It should be noted that the foregoing discloses a process generally describing the formation of spacers and LDD regions. Other processes and sequences may also be used to form spacers and LDD regions, for example, fewer or additional spacers may be used, a different sequence of steps may be used, additional spacers may be formed and removed, etc. Furthermore, n-type devices and p-type devices may be formed using different structures and steps.

[0134] exist 17A to 17C, source / drain recesses 104 are formed in the nanostructures 64, 66 and the sacrificial spacers 76. In the illustrated embodiment, the source / drain recesses 104 extend through the nanostructures 64, 66 and the sacrificial spacers 76 into the semiconductor fins 62. The source / drain recesses 104 may also extend into the substrate 50. In various embodiments, the source / drain recesses 104 may extend to the top surface of the substrate 50 without etching the substrate 50; the semiconductor fins 62 may be etched so that the bottom surface of the source / drain recesses 104 is disposed below the top surface of the STI regions 72; or other similar embodiments. The nanostructures 64, 66 and the sacrificial spacers 76 may be etched using an anisotropic etching process (e.g., RIE or NBE, etc.) to form the source / drain recesses 104. During the etching process for forming the source / drain recesses 104, the gate spacers 98 and the dummy gate 94 together act as a mask to cover the portions of the semiconductor fins 62 and / or nanostructures 64, 66 that will serve as the channel region 68. A single etching process may be used to etch the nanostructures 64, 66 and the sacrificial spacers 76, or multiple etching processes may be used to individually etch the nanostructures 64, 66 and the sacrificial spacers 76. After the source / drain recesses 104 reach the desired depth, a timed etching process may be used to stop the etching of the source / drain recesses 104.

[0135] exist 18A to 18C In the embodiment, the internal spacer 106 is formed on the sidewall of the nanostructure 64, for example, on the sidewall of the nanostructure 64 exposed by the source / drain groove 104, and the epitaxial source / drain region 108 is formed in the source / drain groove 104, as shown in FIG. 18A to 18C As shown. As described in more detail later, source / drain regions will be subsequently formed in source / drain recesses 104, and nanostructures 64 will be subsequently replaced by corresponding gate structures. Internal spacers 106 serve as isolation elements between subsequently formed source / drain regions and subsequently formed gate structures. In addition, internal spacers 106 can be used to substantially prevent subsequently formed source / drain regions from being damaged by an etching process (e.g., an etching process for subsequently removing nanostructures 64).

[0136] As one example of forming the internal spacer 106, the source / drain groove 104 can be expanded laterally. Specifically, the portion of the sidewall of the nanostructure 64 exposed by the source / drain groove 104 can be recessed. Although the sidewall of the nanostructure 64 is depicted as concave, the sidewall can be straight or convex. The sidewall can be recessed by any acceptable etching process, such as an etching process that is selective to the nanostructure 64 (e.g., selectively etching the material of the nanostructure 64 at a faster etching rate than the material of the nanostructure 66). The etching can be isotropic. For example, when the nanostructure 66 is formed of silicon and the nanostructure 64 is formed of silicon germanium, the etching process can be wet etching using tetramethylammonium hydroxide (TMAH) or ammonium hydroxide (NH4OH), etc. In another embodiment, the etching process can be performed using dry etching, such as a fluorine-based gas such as hydrogen fluoride (HF) gas. Then, the internal spacer 106 is formed on the recessed sidewall of the nanostructure 64. The inner spacer 106 may be formed by conformally forming an insulating material and then etching the insulating material. The insulating material may be silicon nitride or silicon oxynitride, but may also be any other suitable material, such as a low-k dielectric material. The insulating material may be deposited by a conformal deposition process, such as ALD or CVD, etc. The etching of the insulating material may be anisotropic. For example, the etching process may be a dry etch, such as RIE or NBE, etc. Although the outer sidewalls of the inner spacer 106 are depicted as being recessed relative to the sidewalls of the gate spacer 98, the outer sidewalls of the inner spacer 106 may extend beyond the sidewalls of the gate spacer 98 or be flush with the sidewalls of the gate spacer 98. In other words, the inner spacer 106 may partially fill, completely fill, or overfill the sidewall recess. In addition, although the sidewalls of the inner spacer 106 are shown as being recessed, the sidewalls of the inner spacer 106 may be straight or convex.

[0137] Epitaxial source / drain regions 108 are formed in recesses 104 so that each dummy gate 94 (and corresponding channel region 68) is disposed between corresponding adjacent pairs of epitaxial source / drain regions 108. In some embodiments, gate spacers 98 and internal spacers 106 are used to separate epitaxial source / drain regions 108 from dummy gates 94 and nanostructures 64, respectively, by appropriate lateral distances so that epitaxial source / drain regions 108 do not short circuit with the gate of a subsequently formed nanoFET. The material of epitaxial source / drain regions 108 may be selected to impart stress in each channel region 68, thereby improving performance.

[0138] The epitaxial source / drain region 108 in the n-type region 50N can be formed by masking the p-type region 50P. Then, the epitaxial source / drain region 108 in the n-type region 50N is epitaxially grown in the source / drain groove 104 in the n-type region 50N. The epitaxial source / drain region 108 may include any acceptable material suitable for an n-type device. For example, if the nanostructure 66 is silicon, the epitaxial source / drain region 108 in the n-type region 50N may include a material that applies tensile strain to the channel region 68, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon arsenide, or silicon phosphide. The epitaxial source / drain region 108 in the n-type region 50N may be referred to as an "n-type source / drain region". The epitaxial source / drain region 108 in the n-type region 50N may have a surface protruding from the corresponding surfaces of the semiconductor fin 62 and the nanostructures 64, 66, and may have a facet.

[0139] The epitaxial source / drain region 108 in the p-type region 50P can be formed by masking the n-type region 50N. Then, epitaxial growth is performed in the source / drain groove 104 in the p-type region 50P to become the epitaxial source / drain region 108 in the p-type region 50P. The epitaxial source / drain region 108 may include any acceptable material suitable for a p-type device. For example, if the nanostructure 66 is silicon, the epitaxial source / drain region 108 in the p-type region 50P may include a material that applies compressive strain to the channel region 68, such as silicon germanium, boron-doped silicon germanium, silicon germanium phosphide, germanium, or germanium tin. The epitaxial source / drain region 108 in the p-type region 50P may be referred to as a "p-type source / drain region". The epitaxial source / drain region 108 in the p-type region 50P may have a surface protruding from the corresponding surfaces of the semiconductor fin 62 and the nanostructures 64, 66, and may have a facet.

[0140] The epitaxial source / drain regions 108, nanostructures 64, 66 and / or semiconductor fins 62 may be implanted with impurities to form source / drain regions, similar to the process used to form the LDD regions described above, followed by an annealing process. The epitaxial source / drain regions 108 may have a thickness between 10 19 cm -3 Up to 10 21 cm -3 The n-type and / or p-type impurities used for the source / drain regions may be any of the impurities previously described. In some embodiments, the epitaxial source / drain regions 108 may be in-situ doped during growth.

[0141] The epitaxial source / drain region 108 may include one or more layers of semiconductor material. For example, the epitaxial source / drain region 108 may each include a liner layer 108A, a main layer 108B, and a finishing layer 108C (or more generally, a first semiconductor material layer, a second semiconductor material layer, and a third semiconductor material layer). Any number of semiconductor material layers may be used for the epitaxial source / drain region 108. The liner layer 108A, the main layer 108B, and the finishing layer 108C of each layer may be formed of different semiconductor materials and may be doped to different impurity concentrations. In some embodiments, the liner layer 108A may have a smaller impurity concentration than the main layer 108B, and the finishing layer 108C may have a greater impurity concentration than the liner layer 108A and a smaller impurity concentration than the main layer 108B. In embodiments where the epitaxial source / drain region 108 includes three semiconductor material layers, a liner layer 108A may be grown in the source / drain recesses 104 , a main layer 108B may be grown on the liner layer 108A, and a finishing layer 108C may be grown on the main layer 108B.

[0142] Due to the epitaxial process for forming epitaxial source / drain regions 108, the upper surface of epitaxial source / drain regions 108 has facets that extend laterally outward and beyond the sidewalls of semiconductor fins 62 and nanostructures 64, 66. However, insulating fins 82 and STI regions 72 block lateral epitaxial growth. Fig. 6A As described above, dielectric layer 71 is converted into a high-quality high-carbon oxide layer that is highly resistant to etching processes using hydrofluoric acid (HF). Therefore, during the recessing of dielectric layer 70 and dielectric layer 71 to form STI region 72, a relatively small amount of dielectric layer 71 is removed (also referred to as oxide loss), thereby allowing the remaining STI region 72 to fully protect the sidewalls of semiconductor fin 62. Fig.18CAs shown, when the epitaxial source / drain regions 108 are formed between adjacent semiconductor fins 62, the epitaxial source / drain regions 108 are fully isolated from each other, and the epitaxial source / drain regions 108 are prevented from merging with each other by the STI region 72 and the insulating fin 82. Therefore, the device performance can be improved. For example, each STI region 72 is arranged between the first sidewalls of adjacent semiconductor fins 62, wherein the STI region 72 extends along each first sidewall, and wherein each first sidewall is located below the corresponding epitaxial source / drain region 108, the STI region 72 is located below the corresponding epitaxial source / drain region 108, and the thickness T4 of the STI region 72 is between 20nm and 160nm. The epitaxial source / drain region 108 contacts the sidewalls of the insulating fin 82. In the illustrated embodiment, the epitaxial source / drain region 108 grows so that the upper surface of the epitaxial source / drain region 108 is located below the top surface of the insulating fin 82. In various embodiments, the upper surface of the epitaxial source / drain region 108 is disposed above the top surface of the insulating fin 82; the upper surface of the epitaxial source / drain region 108 has portions located above and below the top surface of the insulating fin 82; or other similar embodiments.

[0143] exist FIG. 19A to FIG. 19C In the embodiment of the present invention, a first inter-layer dielectric (ILD) 114 is deposited over the epitaxial source / drain regions 108, the gate spacer 98, the mask 96 (if present), or the dummy gate 94. The first ILD 114 may be formed of a dielectric material, and the dielectric material may be deposited by any suitable method, such as CVD, plasma enhanced CVD (PECVD), or FCVD. Acceptable dielectric materials may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), or undoped silicate glass (USG). Other insulating materials formed by any acceptable process may be used.

[0144] In some embodiments, a contact etch stop layer (CESL) 112 is formed over the epitaxial source / drain regions 108, the gate spacers 98, and the mask 96 (if present) or the dummy gate 94, and a first ILD 114 is formed over the CESL 112. The CESL 112 may be formed of a dielectric material, such as silicon nitride, silicon oxide, or silicon oxynitride, and may have a high etching selectivity relative to the etching of the first ILD 114. The CESL 112 may be formed by any suitable method, such as CVD or ALD.

[0145] exist FIG. 20A to FIG. 20C In the process, a removal process is performed to make the top surface of the first ILD 114 flush with the top surface of the mask 96 (if present) or the dummy gate 94. In some embodiments, the planarization process is, for example, chemical mechanical polishing (CMP), an etch-back process, or a combination thereof. The planarization process can also remove the mask 96 on the dummy gate 94 and the portion of the gate spacer 98 along the sidewall of the mask 96. After the planarization process, the top surface of the gate spacer 98, the first ILD 114, the CESL 112, the mask 96 (if present), or the dummy gate 94 are coplanar (within process variations). Therefore, the top surface of the mask 96 (if present) or the dummy gate 94 is exposed to the first ILD 114. In the illustrated embodiment, the mask 96 is retained, and the top surface of the first ILD 114 is made flush with the top surface of the mask 96 by the planarization process.

[0146] exist FIG. 21A to FIG. 21C In the etching process, the mask 96 (if present) and the dummy gate 94 are removed so that the recess 116 is formed, thereby exposing the channel region 68. The portion of the nanostructure 66 that serves as the channel region 68 is disposed between adjacent pairs of epitaxial source / drain regions 108. In some embodiments, the dummy gate 94 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas, and the dry etching process selectively etches the dummy gate 94 at a faster rate than the first ILD 114 or the gate spacer 98.

[0147] Then, the remaining portion of the sacrificial spacer 76 is removed to expand the groove 116 so that the opening 120 is formed in the area between the semiconductor fin 62 and the insulating fin 82, and the remaining portion of the nanostructure 64 is also removed to expand the groove 116. The groove 116 is expanded so that the opening 118 is formed in the area between the nanostructures 66. The remaining portion of the nanostructure 64 and the sacrificial spacer 76 can be removed by any acceptable etching process that selectively etches the material of the nanostructure 64 and the sacrificial spacer 76 at a faster rate than the material of the nanostructure 66. The etching can be isotropic. For example, when the nanostructure 64 and the sacrificial spacer 76 are formed of silicon germanium and the nanostructure 66 is formed of silicon, the etching process can be a wet etch using tetramethylammonium hydroxide (TMAH) or ammonium hydroxide (NH4OH), etc. In some embodiments, a trimming process (not separately shown) is performed to reduce the thickness of the exposed portion of the nanostructure 66.

[0148] exist FIG. 22A to FIG. 22C In the embodiment, a gate dielectric layer 124 is formed in the groove 116, and a gate electrode layer 126 is formed on the gate dielectric layer 124. The gate dielectric layer 124 and the gate electrode layer 126 are used to replace the gate, and each of the gate dielectric layer 124 and the gate electrode layer 126 can surround all sides (for example, four sides) of the nanostructure 66. Therefore, the gate dielectric layer 124 and the gate electrode layer 126 are formed in the opening 118 and the opening 120 (see FIG. 21A to FIG. 21C ).

[0149] The gate dielectric layer 124 is disposed on the sidewalls and / or top surface of the semiconductor fin 62; on the top surface, sidewalls, and bottom surface of the nanostructure 66; on the sidewalls of the internal spacer 106 adjacent to the epitaxial source / drain region 108; on the sidewalls of the gate spacer 98; and, on the top surface and sidewalls of the insulating fin 82. The gate dielectric layer 124 may also be formed on the first ILD 114 and the top surface of the gate spacer 98. The gate dielectric layer 124 may include an oxide (e.g., silicon oxide or a metal oxide), a silicate (e.g., a metal silicate), a combination thereof, or multiple layers thereof, and the like. The gate dielectric layer 124 may include a high-k dielectric material (e.g., a dielectric material having a k value greater than about 7.0), such as a metal oxide of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof, or a silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Although FIG. 22A to FIG. 22C A single layer of gate dielectric layer 124 is shown in FIG. 1 , but the gate dielectric layer 124 may include any number of interfacial layers and any number of main layers.

[0150] The gate electrode layer 126 may include a metal-containing material such as titanium nitride, titanium oxide, tungsten, cobalt, ruthenium, aluminum, combinations thereof, or multiple layers thereof. FIG. 22A to FIG. 22CA single gate electrode layer 126 is shown in FIG. 1 , but the gate electrode layer 126 may include any number of work function adjustment layers, any number of barrier layers, and any number of glue layers and filling materials.

[0151] The gate dielectric layer 124 in the n-type region 50N and the p-type region 50P may be formed simultaneously, so that the gate dielectric layer 124 in each region is formed of the same material, and the gate electrode layer 126 may be formed simultaneously, so that the gate electrode layer 126 in each region is formed of the same material. In some embodiments, the gate dielectric layer 124 in each region may be formed by different processes, so that the gate dielectric layer 124 may be a different material and / or have a different number of layers; and / or the gate electrode layer 126 in each region may be formed by different processes, so that the gate electrode layer 126 may be a different material and / or have a different number of layers. When different processes are used, various masking steps may be used to mask and expose appropriate regions.

[0152] exist FIG. 23A to FIG. 23C 114 and the gate spacer 98, thereby forming the gate structure 130. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. may be used. When planarized, the gate dielectric layer 124 has a portion that remains in the groove 116 (thus, forming the gate dielectric layer 131 of the gate structure 130). When planarized, the gate electrode layer 126 has a portion that remains in the groove 116 (thus, forming the gate electrode 132 of the gate structure 130). The top surfaces of the gate spacer 98, the CESL 112, the first ILD 114, and the gate structure 130 are coplanar (within process variations). The gate structure 130 is a replacement gate for the resulting nanoFET and may be referred to as a "metal gate". The gate structures 130 each extend along the top surface, sidewalls, and bottom surface of the channel region 68 of the nanostructure 66. Gate structure 130 fills the area previously occupied by nanostructures 64 , sacrificial spacers 76 , and dummy gate 94 .

[0153] In some embodiments, an isolation region 133 is formed extending through a portion of the gate structure 130. The isolation region 133 is formed to divide (e.g., cut) the gate structure 130 into a plurality of gate structures 130. The isolation region 133 may be formed of a dielectric material, such as silicon nitride, silicon oxide, or silicon oxynitride, and the dielectric material may be formed by a deposition process such as CVD or ALD. As one example, in order to form the isolation region 133, any acceptable etching process (e.g., dry etching, wet etching, or a combination thereof) may be used to pattern an opening in the desired gate structure 130. The etching may be anisotropic. One or more layers of dielectric material may be deposited in the opening. A removal process may be performed to remove excess portions of the dielectric material above the top surface of the gate structure 130, thereby forming the isolation region 133.

[0154] exist FIG. 24A to FIG. 24C In the embodiment of the present invention, the second ILD 136 is deposited over the gate spacer 98, the CESL 112, the first ILD 114, and the gate structure 130. In some embodiments, the second ILD 136 is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD 136 is formed of a dielectric material such as PSG, BSG, BPSG, or USG, and the second ILD 136 can be deposited by any suitable method such as CVD or PECVD.

[0155] In some embodiments, an etch stop layer (ESL) 134 is formed between the second ILD 136 and the gate spacers 98, the CESL 112, the first ILD 114, and the gate structure 130. The ESL 134 may include a dielectric material such as silicon nitride, silicon oxide, or silicon oxynitride, and the dielectric material has a high etch selectivity to the second ILD 136.

[0156] exist FIG. 25A to FIG. 25C In the embodiment, a gate contact 142 and a source / drain contact 144 are formed to contact the gate structure 130 and the epitaxial source / drain region 108, respectively. The gate contact 142 is physically and electrically coupled to the gate structure 130. The source / drain contact 144 is physically and electrically coupled to the epitaxial source / drain region 108.

[0157] As one example of forming the gate contact 142 and the source / drain contact 144, an opening that will become the gate contact 142 is formed through the second ILD 136 and the ESL 134, and an opening that will become the source / drain contact 144 is formed through the second ILD 136, the ESL 134, the first ILD 114, and the CESL 112. Acceptable lithography and etching techniques can be used to form the opening. A liner (not shown separately) (e.g., a diffusion barrier layer or an adhesion layer, etc.) and a conductive material are formed in the opening. The liner can include titanium, titanium nitride, tantalum, or tantalum nitride, etc. The conductive material can be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, or nickel, etc. A planarization process such as CMP can be performed to remove excess material from the surface of the second ILD 136. The remaining liner and conductive material form the gate contact 142 and the source / drain contact 144 in the opening. The gate contact 142 and the source / drain contact 144 may be formed in different processes or in the same process. Although the gate contact 142 and the source / drain contact 144 are formed in the same cross-sectional view in the drawings, it should be understood that the gate contact 142 and the source / drain contact 144 may be formed in different cross-sectional views, respectively, thereby avoiding contact short circuits.

[0158] Optionally, a metal-semiconductor alloy region 146 is formed at the interface between the epitaxial source / drain region 108 and the source / drain contact 144. The metal-semiconductor alloy region 146 may be a silicide region formed by a silicide region formed by a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), a germanide region formed by a metal germanide (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), a silicon-germanide region formed by both a metal silicide and a metal germanide, or other similar metal-semiconductor alloy region. The metal-semiconductor alloy region 146 may be formed before the metal material of the source / drain contact 144 is deposited in the opening and a subsequent thermal annealing process is performed. The metal may be any metal that can react with the semiconductor material of the epitaxial source / drain region 108 (e.g., silicon, silicon-germanium, germanium, etc.) to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or alloys thereof. The metal may be deposited by a deposition process such as ALD, CVD, or PVD. After the thermal annealing process, a cleaning process such as a wet clean may be performed to remove any residual metal from the openings of the source / drain contacts 144 (e.g., from the surface of the metal-semiconductor alloy region 146). The source / drain contacts 144 may then be formed on the metal-semiconductor alloy region 146.

[0159] FIG. 26A to FIG. 26C Unless otherwise indicated, the same reference numerals in this embodiment refer to the same reference numerals in the embodiment. Figures 1 to 25CFor example, the STI regions 72 disposed on either side of each semiconductor fin 62 are depicted. Therefore, the process steps and applicable materials may not be repeated in this embodiment. FIG. 26A to FIG. 26C The embodiments shown in Figures 1 to 25C The embodiment shown in FIG. 1 differs in that FIG. 26A to FIG. 26C The embodiments in the embodiment describe a fin field effect transistor (FinFET) device rather than a nanostructure field effect transistor (NSFET). The formation of a multilayer stack 52 above the substrate 50 (previously described in Figure 2 ), therefore, a multilayer stack 52 including alternating first semiconductor layers 54 and second semiconductor layers 56 is not formed over the substrate 50.

[0160] FIG. 26A to FIG. 26C A semiconductor fin 62 is shown formed in a substrate 50 by etching a trench in the substrate 50. The etching may be any one or more acceptable etching processes, such as reactive ion etching (RIE), neutral beam etching (NBE), or a combination thereof. The etching may be anisotropic. Although the semiconductor fin 62 is illustrated as having linear edges, the semiconductor fin 62 may have rounded edges or any other suitable shape. Since the multilayer stack 52 is not formed before etching the trench in the substrate 50 to form the semiconductor fin 62, the nanostructure 64 and the nanostructure 66 are not formed above the semiconductor fin 62, and the top area of ​​the semiconductor fin 62 serves as the channel region of the corresponding FinFET device. In one embodiment, the height of each semiconductor fin 62 may be greater than 200 nm. In one embodiment, the ratio between the height H1 of each semiconductor fin 62 and the thickness T4 of the STI region 72 may be between 15 and 1.2.

[0161] The STI region 72 is similar to Figures 4 to 7 In the manner described in the foregoing, a dielectric layer 70 is formed over substrate 50 and between adjacent semiconductor fins 62, for example, in trench 60. STI region 72 is disposed around at least a first portion of semiconductor fin 62, such that at least a second portion of semiconductor fin 62 protrudes from between adjacent STI regions 72. The formation of STI region 72 includes depositing dielectric layer 70 over the top surface of mask 58 and the top surface and sidewalls of semiconductor fin 62. Then, dielectric layer 71 is formed in trench 60, over dielectric layer 70 and over mask 58.

[0162] After forming dielectric layer 71, an annealing process 73 is performed to cure or treat dielectric layer 71, wherein dielectric layer 71 is converted, for example, by an oxidation process. During annealing process 73, carbon from dielectric layer 70 is released or diffused into dielectric layer 71, so that after annealing process 73, dielectric layer 71 includes high carbon silicon oxide. After annealing process 73, dielectric layer 71 has a carbon atomic percentage concentration between 0.5% and 4%. Then, dielectric layer 70 and dielectric layer 71 are recessed to form a dielectric layer 71 by a process similar to that in FIG. Figure 7 STI regions 72 are formed in the manner described in . Dielectric layers 70 and 71 are recessed so that at least a portion of semiconductor fin 62 protrudes from between adjacent portions of dielectric layer 70. In addition, by using appropriate etching, the top surface of STI region 72 can have a flat surface (as shown), a convex surface, a concave surface (e.g., recessed), or a combination thereof. Dielectric layers 70 and 71 can be recessed using any acceptable etching process (e.g., by selectively etching the material of dielectric layers 70 and 71 at a faster rate than the material of semiconductor fin 62). For example, oxide removal can be performed using diluted hydrofluoric acid (dHF) as an etchant.

[0163] The STI regions 72 include high-quality high-carbon oxides and are resistant to etching processes (e.g., etching processes used to form the STI regions 72, such as those described above). Figure 7 ) has high tolerance. Therefore, during the formation of the STI region 72, a smaller amount of high carbon oxide (also referred to as oxide loss) is removed, which allows the remaining STI region 72 to fully protect the sidewalls of the semiconductor fin 62. The epitaxial source / drain regions 108 formed in adjacent semiconductor fins 62 are fully isolated from each other and prevented from merging with each other by the STI region 72. Therefore, the performance of the device can be improved. In addition, the STI region 72 has a carbon atomic percentage concentration between 0.5% and 4%, which indicates that the annealing process for forming the STI region 72 to form a high carbon dielectric layer (e.g., oxide) can be performed at a lower temperature and a longer duration. In this way, thermal budget control is allowed for advanced technology nodes that require a lower total thermal budget during device manufacturing. In addition, due to the lower temperature and longer duration of the annealing process, it can be fully and effectively converted to high carbon oxide, thereby producing a more uniform oxide quality and composition after the conversion process (e.g., at the bottom of a trench with a high aspect ratio).

[0164] After forming the STI region 72, a sacrificial spacer 76 is formed above the STI region 72, on the sidewalls of the mask 58, and on the sidewalls of the semiconductor fin 62. The formation of the sacrificial spacer 76 can use processes and materials similar to those described in Figures 9A to 10C above. Next, an insulating fin 82 (also referred to as a hybrid fin or a dielectric fin) is formed between the sacrificial spacers 76 adjacent to the semiconductor fin 62 using a method similar to that described in Figures 11A to 13C above. The insulating fin 82 can insulate and physically separate the epitaxial source / drain regions 108 formed subsequently from each other.

[0165] After forming the insulating fins 82, a method similar to that described above is used. FIG. 14A to FIG. 14C Then, the mask 58 is removed by using an etching process similar to that described above. FIG. 15A to FIG. 16C A dummy gate structure is formed in a manner similar to that described in . For example, a dummy gate layer 84 is formed on the insulating fin 82, the sacrificial spacer 76, and the semiconductor fin 62. A mask layer 86 can be deposited over the dummy gate layer 84. The mask layer 86 is then patterned using acceptable lithography and etching techniques to form a mask 96. The pattern of the mask 96 is then transferred to the dummy gate layer 84 by any acceptable etching technique to form a dummy gate 94. The dummy gate 94 will cover the top surface of the semiconductor fin 62 that will be used to form the channel region 68. The pattern of the mask 96 can be used to physically separate adjacent dummy gates 94. Optionally, the mask 96 can be removed after patterning, for example by any acceptable etching technique. Gate spacers 98 are then formed over the semiconductor fin 62 and on the exposed sidewalls of the mask 96 (if present) and the dummy gate 94.

[0166] After forming the dummy gate 94 and the gate spacer 98, a similar method as described above is used. FIG. 17A to FIG. 17C , source / drain recesses 104 are formed in the semiconductor fins 62 and the sacrificial spacers 76. For example, the source / drain recesses 104 may extend through the sacrificial spacers 76 and up to the semiconductor fins 62. The source / drain recesses 104 may also extend into the substrate 50.

[0167] Then, use something similar to the above 18A to 18C 1 , epitaxial source / drain regions 108 are formed in recesses 104 using the materials described in the drawings. Each dummy gate 94 (and corresponding channel region 68) is disposed between corresponding adjacent pairs of epitaxial source / drain regions 108. In some embodiments, gate spacers 98 are used to separate the epitaxial source / drain regions 108 from the dummy gates 94 by an appropriate lateral distance. The material of the epitaxial source / drain regions 108 can be selected to apply stress to each channel region 68, thereby improving performance.

[0168] Due to the epitaxial process for forming the epitaxial source / drain regions 108, the upper surface of the epitaxial source / drain regions 108 has facets that extend laterally outward beyond the sidewalls of the semiconductor fins 62. However, the insulating fins 82 and the STI regions 72 block the lateral epitaxial growth. Fig. 6A As described, the dielectric layer 71 is converted into a high-quality high-carbon oxide layer that is highly resistant to etching processes using hydrofluoric acid (HF). Therefore, during the recessing of the dielectric layer 70 and the dielectric layer 71 to form the STI region 72, a relatively small amount of the dielectric layer 71 (also referred to as oxide loss) is removed, which allows the remaining STI region 72 to fully protect the sidewalls of the semiconductor fin 62. Therefore, when the epitaxial source / drain region 108 is formed in the adjacent semiconductor fin 62, the epitaxial source / drain region 108 is fully isolated from each other, and the epitaxial source / drain region 108 is prevented from merging with each other by the STI region 72 and the insulating fin 82. Therefore, the performance of the device is improved. The epitaxial source / drain region 108 contacts the sidewalls of the insulating fin 82. In the illustrated embodiment, the growth of the epitaxial source / drain region 108 causes the upper surface of the epitaxial source / drain region 108 to be disposed below the top surface of the insulating fin 82. In various embodiments, the upper surface of the epitaxial source / drain region 108 is disposed above the top surface of the insulating fin 82; the upper surface of the epitaxial source / drain region 108 has portions located above and below the top surface of the insulating fin 82; or other similar embodiments.

[0169] After forming the epitaxial source / drain regions 108, a similar method as described above is used. FIG. 19A to FIG. 19C A contact etch stop layer (CESL) 112 and a first interlayer dielectric (ILD) 114 are deposited over the epitaxial source / drain regions 108, gate spacers 98, and mask 96 (if present) or dummy gate 94 in the manner described in the previous section. FIG. 20A to FIG. 20C In the manner described in , the removal process is performed to make the top surfaces of the CESL 112 and the first ILD 114 flush with the top surface of the mask 96 (if present) or the dummy gate 94 .

[0170] Then, use something similar to the above FIG. 21A to FIG. 21C The mask 96 (if present) and the dummy gate 94 are removed in the etching process described in , so that the recess 116 is formed, thereby exposing the channel region of the semiconductor fin 62. In some embodiments, the dummy gate 94 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas, and the etching process may selectively etch the dummy gate 94 at a faster rate than the first ILD 114 or the gate spacer 98.

[0171] Alternatively, use a method similar to the one above. FIG. 21A to FIG. 21CIn the manner described in the foregoing, the remaining portion of the sacrificial spacer 76 is removed so that the opening 120 is formed in the region between the semiconductor fin 62 and the insulating fin 82. However, since the nanostructures 64 and 66 are not present, the opening 118 (in the foregoing FIG. 21A to FIG. 21C ). The remaining portion of sacrificial spacer 76 may be removed by any acceptable etching process that may selectively etch the material of sacrificial spacer 76 at a faster rate than the material of semiconductor fin 62. The etching may be isotropic. For example, when sacrificial spacer 76 is formed of silicon germanium and semiconductor fin 62 is formed of silicon, the etching process may be a wet etch using tetramethylammonium hydroxide (TMAH) or ammonium hydroxide (NH4OH), etc.

[0172] After removing the remaining portion of the dummy gate 94 and the sacrificial spacer 76, a gate dielectric layer 124 is formed in the groove 116, and a gate electrode layer 126 is formed on the gate dielectric layer 124 in a manner similar to the aforementioned FIG. 22A to FIG. 22C 1. The gate dielectric layer 124 and the gate electrode layer 126 are used to replace the gate, and each can be formed in the groove 116 and the opening 120. Since there is no opening 118, the gate dielectric layer 124 and the gate electrode layer 126 do not surround all sides (e.g., four sides) of any portion of the semiconductor fin 62. The gate dielectric layer 124 is disposed on the sidewalls and top surface of the semiconductor fin 62; on the sidewalls of the gate spacer 98; and on the top surface and sidewalls of the insulating fin 82.

[0173] After forming the gate dielectric layer 124 and the gate electrode layer 126, a removal process is performed to remove excess portions of the gate dielectric layer 124 and the gate electrode layer 126 to form the gate structure 130, and these excess portions are located above the first ILD 114 and the top surface of the gate spacer 98. The removal process (e.g., planarization process) is similar to the aforementioned FIG. 23A to FIG. 23C When planarized, the gate dielectric layer 124 has a portion remaining in the recess 116 (thus, forming the gate dielectric layer 131 of the gate structure 130). When planarized, the gate electrode layer 126 has a portion remaining in the recess 116 (thus, forming the gate electrode 132 of the gate structure 130).

[0174] After the removal process is performed, a similar method as described above is used. FIG. 24A to FIG. 24CIn the manner described in the above, an etch stop layer (ESL) 134 and a second ILD 136 are deposited over the gate spacers 98, the CESL 112, the first ILD 114, and the gate structure 130. After the ESL 134 and the second ILD 136 are formed, a gate contact 142 and a source / drain contact 144 are formed to contact the gate structure 130 and the epitaxial source / drain region 108, respectively. The gate contact 142 is physically and electrically coupled to the gate structure 130. The source / drain contact 144 is physically and electrically coupled to the epitaxial source / drain region 108. The gate contact 142 and the source / drain contact 144 may be formed using a similar method as described above. FIG. 25A to FIG. 25C It is formed in the manner described in .

[0175] Embodiments of the present disclosure have some advantageous features. Embodiments of the present disclosure include a method for forming a high-carbon shallow trench isolation (STI) region, which is discussed in the context of forming a nanostructure field effect transistor (NSFET), a fin field effect transistor (FinFET) device, and the like. The method includes conformally depositing a first high-carbon dielectric layer over and in a trench between two adjacent semiconductor fins. Next, a second dielectric layer is formed over the first dielectric layer to fill the trench between adjacent fins. An annealing process is performed to convert the second dielectric layer into a third high-carbon dielectric layer (e.g., oxide). After the annealing process, the carbon atomic percentage concentration of the third dielectric layer is between 0.5% and 4%. Thus, an STI region including a high-quality high-carbon third dielectric layer that is highly resistant to a subsequently performed etching process (e.g., an etching process using hydrofluoric acid (HF)) can be formed. In addition, since the carbon atomic percentage concentration of the third dielectric layer is between 0.5% and 4%, a lower annealing temperature can be used during the annealing process to transform the second dielectric layer into the third dielectric layer, thereby allowing thermal budget control for advanced technology nodes that require a lower total thermal budget during device manufacturing. In addition, since a lower annealing temperature and a longer duration can be used, the second dielectric layer can be completely and effectively transformed into the third dielectric layer even if the trench has a high aspect ratio, and after the transformation process, the third dielectric layer has a more uniform oxide quality and composition (e.g., at the bottom of the trench).

[0176] According to one embodiment, a method of manufacturing a semiconductor device includes etching a first trench in a semiconductor substrate to form a first fin and a second fin; and forming a shallow trench isolation (STI) region in the first trench, wherein forming the STI includes: depositing a first dielectric layer over multiple top surfaces of the first fin and the second fin and on multiple sidewalls and a bottom surface of the first trench, wherein the first dielectric layer includes carbon; depositing a second dielectric layer over the first dielectric layer and in the first trench, wherein the second dielectric layer fills the first trench; and performing an annealing process, wherein the annealing process releases carbon from the first dielectric layer into the second dielectric layer. In one embodiment, depositing the first dielectric layer includes: conformally depositing the first dielectric layer over the top surfaces of the first fin and the second fin and on the sidewalls and bottom surface of the first trench, wherein the first dielectric layer includes SiOCN. In one embodiment, the method further comprises: depositing a third dielectric layer over the top surfaces and the sidewalls of the first dielectric layer and in the first trench, wherein the third dielectric layer comprises SiOCN, and wherein the carbon content of the first dielectric layer is different from the carbon content of the third dielectric layer. In one embodiment, after performing the annealing process, the carbon atomic percentage concentration in the second dielectric layer is between 0.5% and 4%. In one embodiment, after performing the annealing process, the carbon atomic percentage concentration in the second dielectric layer at the bottommost surface of the second dielectric layer is the largest, and the carbon atomic percentage concentration in the second dielectric layer at the topmost surface of the second dielectric layer is the smallest. In one embodiment, the first dielectric layer comprises SiO x C y N z , wherein the y value varies in a vertical direction from the bottom surface of the first dielectric layer to the top surface of the first dielectric layer. In one embodiment, the annealing process includes: performing a first annealing process while exposing the second dielectric layer to a first oxygen-containing environment; and performing a second annealing process while exposing the second dielectric layer to a second oxygen-containing environment, wherein the first oxygen-containing environment is different from the second oxygen-containing environment.

[0177] According to one embodiment, a method for manufacturing a semiconductor device includes: etching a semiconductor substrate to form a plurality of first fins and first trenches, wherein the first fins protrude from the semiconductor substrate, and the first trenches are spaced between adjacent first fins; and forming a shallow trench isolation (STI) region in the first trench, wherein forming the STI region includes: conformally depositing a first dielectric layer over the first fins and on a plurality of sidewalls and a bottom surface of the first trench, wherein the first dielectric layer includes carbon; forming a second dielectric layer over the first dielectric layer and in the first trench, wherein the second dielectric layer fills the first trench; and oxidizing the second dielectric layer, wherein during oxidation of the second dielectric layer, carbon in the first dielectric layer diffuses into the second dielectric layer. In one embodiment, oxidizing the second dielectric layer includes performing an annealing process while exposing the second dielectric layer to an oxygen-containing environment. In one embodiment, after oxidation of the second dielectric layer, the first dielectric layer is completely consumed. In one embodiment, after oxidation of the second dielectric layer, the first dielectric layer is partially consumed. In one embodiment, conformally depositing the first dielectric layer includes: depositing a third dielectric layer above the first fin and on the sidewalls and bottom surface of the first trench; and depositing a fourth dielectric layer on multiple top surfaces and multiple sidewalls of the third dielectric layer, wherein the carbon content of the third dielectric layer is different from the carbon content of the fourth dielectric layer. In one embodiment, the third dielectric layer and the fourth dielectric layer include SiOCN. In one embodiment, after oxidizing the second dielectric layer, the carbon atomic percentage concentration in the second dielectric layer is between 0.5% and 4%. In one embodiment, the method further includes: forming an epitaxial source / drain region on the first fin, wherein the shallow trench isolation region extends along multiple sidewalls of the first fin, and wherein the ratio between the height of the first fin and the thickness of the shallow trench isolation region is between 15 and 1.2.

[0178] According to one embodiment, a semiconductor device includes: a plurality of first fins extending from a substrate; a shallow trench isolation (STI) layer located between adjacent first fins, wherein the carbon atomic percentage concentration of the STI layer is between 0.5% and 4%; a gate structure located in adjacent first fins and above the STI layer; a source / drain region located in adjacent first fins, each source / drain region being adjacent to the gate structure. In one embodiment, the STI layer also includes a first dielectric liner and a first dielectric layer, and the first dielectric layer is located above the first dielectric liner, wherein the first dielectric liner is disposed between the first fin and the first dielectric layer, and between the top surface of the substrate and the first dielectric layer, wherein the first dielectric liner includes SiOCN. In one embodiment, the STI layer also includes a second dielectric liner, the second dielectric liner is disposed between the first dielectric liner and the first dielectric layer, wherein the second dielectric liner includes SiOCN, and wherein the carbon concentration of the first dielectric liner is different from the carbon concentration of the second dielectric liner. In one embodiment, a carbon atomic percentage concentration at a first point in the STI layer is greater than a carbon atomic percentage concentration at a second point in the STI layer, wherein the first point is vertically below and overlaps the second point. In one embodiment, a ratio of a height of the first fin to a thickness of the STI layer is between 15 and 1.2.

[0179] According to one embodiment, a semiconductor device includes a semiconductor substrate, a first fin, a second fin, and a shallow trench isolation region. The first fin is disposed on the semiconductor substrate. The second fin is disposed on the semiconductor substrate and is adjacent to the first fin at a distance. The shallow trench isolation region is disposed between the first fin and the second fin, and the shallow trench isolation region includes a first dielectric layer and a second dielectric layer. The first dielectric layer is disposed above multiple top surfaces and multiple sidewalls of the first fin and the second fin, and is located on the top surface of the semiconductor substrate between the first fin and the second fin. The second dielectric layer is disposed above the first dielectric layer. In one embodiment, the shallow trench isolation region further includes a third dielectric layer disposed above multiple top surfaces and multiple sidewalls of the first dielectric layer. In one embodiment, the thickness of the first dielectric layer is the same as the thickness of the third dielectric layer. In one embodiment, the thickness of the first dielectric layer is different from the thickness of the third dielectric layer. In one embodiment, the top surface of the second dielectric layer is lower than the top surface of the first fin.

[0180] According to one embodiment, a semiconductor device includes a semiconductor substrate, a plurality of fins and a shallow trench isolation region. A plurality of fins are disposed on the semiconductor substrate, and the fins are disposed adjacent to each other and spaced apart. The shallow trench isolation region is disposed above the semiconductor substrate and between the fins, and the shallow trench isolation region includes a first dielectric layer and a second dielectric layer. The first dielectric layer is disposed above the fins and surrounds the sidewalls of the fins. The second dielectric layer is disposed above the first dielectric layer. In one embodiment, the first dielectric layer has a double-layer structure or a multi-layer structure. In one embodiment, the ratio between the height of the fins and the thickness of the shallow trench isolation region is between 15 and 1.2.

[0181] According to one embodiment, a semiconductor device includes: a plurality of first fins extending from a substrate; a shallow trench isolation (STI) layer located between adjacent first fins, wherein a top surface of the STI layer is lower than a top surface of the first fins; a gate structure located in adjacent first fins and above the STI layer; a source / drain region located in adjacent first fins, each source / drain region being adjacent to the gate structure. In one embodiment, the shallow trench isolation layer includes a first dielectric layer and a second dielectric layer; the first dielectric layer surrounds the lower sidewalls of the first fins and is located on the top surface of the substrate between the first fins; and the second dielectric layer is disposed on the first dielectric layer.

[0182] The present disclosure summarizes various embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and those skilled in the art can make various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: include: a semiconductor substrate; a first fin disposed on the semiconductor substrate; a second fin portion, disposed on the semiconductor substrate and adjacent to the first fin portion at a distance; as well as A shallow trench isolation region is disposed between the first fin and the second fin, and the shallow trench isolation region includes: a first dielectric layer disposed above the top surfaces and sidewalls of the first fin and the second fin, and located on the top surface of the semiconductor substrate between the first fin and the second fin; as well as A second dielectric layer is disposed above the first dielectric layer.

2. The semiconductor device according to claim 1, wherein The shallow trench isolation region further comprises: A third dielectric layer is disposed above the top surfaces and sidewalls of the first dielectric layer.

3. The semiconductor device according to claim 2, wherein: The thickness of the first dielectric layer is the same as the thickness of the third dielectric layer.

4. The semiconductor device according to claim 2, wherein: The thickness of the first dielectric layer is different from the thickness of the third dielectric layer.

5. The semiconductor device according to claim 1, wherein: The top surface of the second dielectric layer is lower than the top surface of the first fin.

6. A semiconductor device, characterized in that: include: a semiconductor substrate; A plurality of fins are disposed on the semiconductor substrate, wherein the fins are disposed adjacent to each other and spaced apart; as well as A shallow trench isolation region is disposed above the semiconductor substrate and between the fins, and the shallow trench isolation region includes: a first dielectric layer disposed above the plurality of fins and surrounding a lower portion of a sidewall of each of the fins; as well as A second dielectric layer is disposed on the first dielectric layer, wherein a top surface of the second dielectric layer is lower than a top surface of each of the fins.

7. The semiconductor device according to claim 6, wherein: The first dielectric layer has a double-layer structure or a multi-layer structure.

8. The semiconductor device according to claim 6, wherein: The ratio between the height of each fin and the thickness of the shallow trench isolation region is between 1.2 and 15.

9. A semiconductor device, characterized in that: include: A plurality of first fins extending from a substrate; a shallow trench isolation layer, located between the adjacent first fins, wherein a top surface of the shallow trench isolation layer is lower than a top surface of each of the first fins; a gate structure located in the adjacent first fins and above the shallow trench isolation layer; as well as A source / drain region is located in the adjacent first fins, and the source / drain region is adjacent to the gate structure.

10. The semiconductor device according to claim 9, wherein: The shallow trench isolation layer comprises: a first dielectric layer surrounding the lower sidewalls of each of the first fins and on the top surface of the substrate between the first fins; and A second dielectric layer is located on the first dielectric layer.

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