Thin film type flip LED chip

Abstract

The utility model relates to the technical field of LED chips, and specifically provides a film type flip LED chip. A metal layer is thickened on a P / N bonding pad of a flip LED chip, and the periphery of the bonding pad is filled with a stress buffer layer, such as organic resin or silicon-based oxide, so that stress generated in the process of laser stripping of a sapphire substrate and die bonding is buffered. The design effectively prevents the epitaxial layer from cracking and lamp failure, and improves the overall reliability and yield of the flip film chip.

Description

Technical Field

[0001] The utility model relates to the technical field of LED chips, in particular to a thin-film flip-chip LED chip. Background Art

[0002] In recent years, with the advancement of science and technology and the enhancement of environmental awareness, the optoelectronics industry has witnessed a technological revolution in energy saving, environmental protection, safety and durability. In this revolution, LED (light emitting diode) has become a leading light source solution with its excellent energy-saving efficiency, environmental protection characteristics, long life, low energy consumption and safe and reliable performance. These advantages of LED technology enable it to be widely used in various fields such as various signs, display screens, decorative lighting, backlight sources and general lighting, thus greatly promoting the development of lighting technology.

[0003] Despite the many advantages of LED technology, in practical applications, especially in the pursuit of higher luminous efficiency and more sophisticated light control, traditional top-mounted and flip-chip LED chip technologies still face some technical challenges. One of the main problems is that these traditional chips emit light at too wide an angle, resulting in scattered light sources and difficulty in achieving highly concentrated light output. To overcome this problem, the industry has proposed vertical chip technology as a potential solution. Vertical chip technology aims to achieve a smaller light-emitting angle and more concentrated light output by optimizing the chip structure design to meet the strict requirements of light quality and light efficiency in specific application areas.

[0004] However, although vertical chip technology has many potential advantages in theory, its production process is relatively complex and the yield rate during the preparation process is relatively low, which constitutes a major obstacle to its widespread application. Figure 1 As shown in the figure, when using traditional flip-chip LED chips to peel off the substrate to prepare thin-film chips, there are two main technical challenges: first, during the crystal bonding process, the contact between the two pads may lead to uneven force, which can easily cause the chip to break; second, when the substrate is peeled off after the crystal bonding, due to the contact between the two pads and the lack of support in the middle and around, the stress is released unevenly, further increasing the risk of chip breakage and leakage.

[0005] Therefore, developing a new type of LED chip technology aimed at addressing the defects and challenges of these existing technologies is of great significance for promoting the further development and application of LED technology. Utility Model Content

[0006] The utility model aims to develop a thin-film flip-chip LED chip to solve the problem of stress generated during laser stripping of sapphire substrate and crystal bonding, thereby improving the reliability of the chip.

[0007] The technical solution of the utility model is:

[0008] A thin-film flip-chip LED chip includes the following structural components:

[0009] The epitaxial layers, including N-type gallium nitride (N-GaN), a quantum well structure, and P-type gallium nitride (P-GaN), were originally placed on a sapphire substrate, which was removed in subsequent processing;

[0010] The first protective layer, with a thickness of 50-500nm, is selected from SiO2 or SiN x , covering the N-GaN epitaxial layer and forming a desired pattern;

[0011] An ITO transparent conductive layer is disposed on the first protective layer and is used to provide a transparent conductive path and connect to the P-type gallium nitride of the epitaxial layer, and its thickness is controlled between 10nm and 300nm;

[0012] The first metal electrode layer (PAD1) is formed on the ITO transparent conductive layer and the N-type gallium nitride of the epitaxial layer by physical vapor deposition, and the material is Cr, Ti, Al, Ag, Ni, Pt or Au, and the total thickness is controlled at 1-2.5um, preferably 2um;

[0013] A Bragg reflector (DBR), which is composed of a stack of SiO2 / TiO materials, is used to enhance light reflectivity and is etched through PAD1 to achieve the connection between the first layer electrode and the second layer electrode;

[0014] The second metal electrode layer (PAD2) covers the DBR and is made of Cr, Ti, Al, Ag, Ni, Pt or Au. The total thickness is controlled at 2-4um, preferably 3um. It passes through the DBR layer and is connected to the first metal electrode layer.

[0015] The second protective layer is selected from SiO2 or SiN x , covering the second metal electrode layer and passing through the second metal electrode layer to connect with the DBR;

[0016] The third metal electrode layer (PAD3), i.e., the P / N pad, is disposed on the second protective layer and is connected to the second metal electrode layer through the second protective layer. The material is Cr, Ti, Al, Ag, Ni, Pt, Au, AuSn or Sn, and the total thickness is controlled at 2-10um, and is used to provide the final electrical connection;

[0017] The P / N pad thickening layer is connected to the third metal electrode layer and is thickened to 20-100um by chemical plating, electroplating or printing;

[0018] The stress buffer layer is filled around the P / N pad and is made of organic resin or SOG insulating material. It is designed to buffer the stress generated during the laser lift-off process or the die bonding process to prevent the epitaxial layer from cracking.

[0019] Preferably, the total thickness of the first metal electrode layer is controlled at 2 um.

[0020] Preferably, the total thickness of the second metal electrode layer is controlled at 3 um.

[0021] The thickness of the transparent conductive layer is controlled between 10nm and 300nm.

[0022] The thickness of the stress buffer layer is equal to the height of the thickened P / N pad.

[0023] The technical solution of the utility model effectively alleviates the stress generated during the laser stripping of the sapphire substrate and the solid crystal process by thickening the metal layer and filling the stress buffer layer on the P / N pads of the flip-chip LED chip, thereby significantly improving the reliability of the chip. In addition, the solution can also prevent the phenomenon of dead lights due to cracking of the epitaxial layer, significantly improving the overall reliability and yield rate of the flip-chip thin-film chip. The thin-film flip-chip LED chip and its preparation method of the utility model, by virtue of sophisticated material selection and process control, effectively solve the main challenges faced by traditional LED chips in high-performance applications, and promote the further development of LED lighting and display technology. The development of this new type of LED chip not only promotes the advancement of LED technology, but also makes important contributions to environmental protection and energy conservation, and has far-reaching social and economic value. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is a cross-sectional structure diagram of a conventional flip-chip LED chip.

[0025] Figure 2 It is a cross-sectional structural diagram of a flip-chip LED chip with a substrate prepared by the utility model.

[0026] Figure 3 It is a cross-sectional structural diagram of a thin-film flip-chip LED chip of the utility model. DETAILED DESCRIPTION

[0027] The preferred embodiments of the present invention are given below in conjunction with the accompanying drawings to illustrate the technical solution of the present invention in detail.

[0028] Embodiment 1:

[0029] like Figure 2 and 3 As shown, the thin-film flip-chip LED chip of the utility model includes the following structural components:

[0030] The epitaxial layers, including N-type gallium nitride (N-GaN), a quantum well structure, and P-type gallium nitride (P-GaN), were originally placed on a sapphire substrate, which was removed in subsequent processing;

[0031] The first protective layer 1, with a thickness of 50-500nm, is selected from SiO2 or SiN x , covering the N-GaN epitaxial layer and forming a desired pattern;

[0032] The ITO transparent conductive layer 2 is disposed on the first protective layer and is used to provide a transparent conductive path and connect to the P-type gallium nitride of the epitaxial layer. The thickness of the ITO transparent conductive layer 2 is controlled between 10nm and 300nm.

[0033] The first metal electrode layer (PAD1) 3 is formed on the ITO transparent conductive layer and the N-type gallium nitride of the epitaxial layer by physical vapor deposition, and the material is Cr, Ti, Al, Ag, Ni, Pt or Au, and the total thickness is controlled at 1-2.5um, preferably 2um;

[0034] A Bragg reflector (DBR) 4, which is composed of a stack of SiO2 / TiO materials, is used to enhance light reflectivity and is engraved through PAD1 to achieve connection between the first layer electrode and the second layer electrode;

[0035] The second metal electrode layer (PAD2) 5, covering the DBR, is made of Cr, Ti, Al, Ag, Ni, Pt or Au, has a total thickness of 2-4 um, preferably 3 um, and passes through the DBR layer to connect with the first metal electrode layer;

[0036] The second protective layer 6 is selected from SiO2 or SiN x , covering the second metal electrode layer and passing through the second metal electrode layer to connect with the DBR;

[0037] The third metal electrode layer (PAD3) 7, i.e., the P / N pad, is disposed on the second protective layer and passes through the second protective layer to be connected to the second metal electrode layer, and is made of Cr, Ti, Al, Ag, Ni, Pt, Au, AuSn or Sn, with a total thickness controlled at 2-10 um, for providing a final electrical connection;

[0038] The P / N pad thickening layer 8 is connected to the third metal electrode layer and is thickened to 20-100 um by chemical plating, electroplating or printing;

[0039] The stress buffer layer 9 is filled around the P / N pad and is made of organic resin or SOG insulating material to buffer the stress generated during the laser lift-off process or the solid crystal process to prevent the epitaxial layer from cracking. The thickness of the stress buffer layer is equal to the height of the P / N pad after thickening.

[0040] The preparation process is as follows:

[0041] 1. Substrate preparation and etching: The N-GaN epitaxial layer is grown on the sapphire substrate using conventional processes. Using fine photolithography and ICP etching, the N-GaN area is precisely etched to expose the metal negative electrode production area, and cutting paths are formed to determine the chip size.

[0042] 2. Protective layer and patterning: A 50-500nm layer of SiO2 or SiNx is deposited on the entire epitaxial wafer surface as a protective layer 1. The desired protective layer pattern is formed by photolithography and wet etching technology again.

[0043] 3. Deposition of ITO transparent conductive layer 2: Using magnetron sputtering or electron beam evaporation technology, a layer of ITO transparent conductive layer 2 is deposited on the protective layer, and the thickness is controlled between 10nm and 300nm. The excess part is removed by photolithography and wet etching to form a transparent conductive path.

[0044] 4. The required pattern of PAD1 is opened by photolithography, and the first metal electrode evaporation is performed. The material of metal electrode 3 is Cr, Ti, Al, Ag, Ni, Pt or Au, and the total thickness is controlled at about 2um; 1-2.5um can be selected. For the subsequent DBR coverage, the thickness is usually controlled at 2um or less;

[0045] 5. Through plasma assisted deposition, SiO2 / TiO stacking is plated on the surface to make a Bragg reflector 4, namely DBR. Through photolithography and ICP process, DBR is etched to PAD1 for subsequent metal connection;

[0046] 6. The required pattern of PAD2 is opened by photolithography, and the second metal electrode evaporation is performed. The material of metal electrode 5 is Cr, Ti, Al, Ag, Ni, Pt or Au, and the total thickness is controlled at about 3um; 2-4um is optional;

[0047] 7. SiO2 or SiN on the surface x Deposition, make P / N-bond pad through hole 6 by photolithography and ICP;

[0048] 8. The required pattern of PAD3 is opened by photolithography, and the third metal electrode evaporation is performed. The material of the metal electrode 7 is Cr, Ti, Al, Ag, Ni, Pt, Au, AuSn or Sn, with a total thickness of 2-10um;

[0049] like Figure 1-3 As shown, the above steps are a conventional method for preparing a flip-chip LED chip;

[0050] 9. The pad 8 is thickened and the stress buffer layer 9 is filled as follows Figure 2As shown: the pad is thickened to 20-100um by chemical plating, electroplating or printing. Cu, Ni or Au is used to ensure the reliability of the electrode. Subsequently, an organic resin or SOG insulating material is filled around the pad as a stress buffer layer 9, which is level with the pad height to buffer the stress generated during laser stripping or die bonding.

[0051] 10. Thin film chip preparation: Select appropriate substrate materials, such as sapphire, Si or glass, and apply UV glue on its surface. Attach the processed wafer to the substrate, and use laser stripping technology to remove the sapphire substrate of the original wafer to form a thin film chip. Through UV debonding, transfer the thin film chip to an appropriate carrier for subsequent spot measurement and sorting. The obtained thin film flip-chip LED chip is as follows: Figure 3 shown.

[0052] Example 2: Conventional flip chip packaging with substrate peeling after die bonding

[0053] This embodiment uses steps 1 to 9 in embodiment 1 to prepare a flip-chip LED chip with a thickened pad and a stress buffer layer. After encapsulation and die bonding, the chip is stripped from the substrate using a physical or chemical method to reduce stress in the chip and improve its reliability. Next, the processing steps after substrate stripping are described in detail:

[0054] 1. Grinding and thinning: The packaged die-bonded LED chip is thinned by mechanical grinding or chemical mechanical polishing (CMP) to reduce the thickness of the entire chip, improve the light emission efficiency and the thermal management performance of the chip.

[0055] 2. Substrate peeling: Use laser peeling technology or chemical solution treatment to carefully remove the chip substrate after die bonding. This step must ensure that the underlying circuit and structural layers are not damaged.

[0056] 3. Surface treatment: After stripping the substrate, organic matter may remain on the chip surface, the roughness may increase, and other problems may occur. It needs to be cleaned and planarized by plasma cleaning, chemical immersion or other surface treatment technologies to ensure good optical properties and the accuracy of subsequent processing.

[0057] 4. Secondary packaging: After substrate stripping and surface treatment, the LED chip will undergo secondary packaging, which includes the formation of a reflective cavity, filling packaging materials (such as silicone) to improve light extraction efficiency, and wire bonding or flip-chip bonding to achieve electrical connection.

[0058] 5. Final testing and sorting: After the above processing, the LED chips need to undergo comprehensive electro-optical performance testing, including brightness, wavelength, current-voltage (IV) characteristics, etc., to ensure that each chip meets the predetermined performance standards. Qualified chips will be sorted according to performance parameters to meet the needs of different applications.

[0059] The utility model significantly improves the chip's reliability and stress resistance during substrate stripping and die bonding by thickening the metal layer on the P / N pad of the flip-chip LED chip and introducing a stress buffer layer, effectively avoiding problems such as epitaxial layer cracking and dead light, and significantly improving the overall performance and reliability of the thin-film flip-chip LED chip. In addition, the preparation method described in the utility model simplifies the production process, helps to improve production efficiency and yield rate, and reduces costs, providing a solid technical foundation for the widespread application of LED light sources.

Claims

1. A thin film flip-chip LED chip, characterized in that: Includes the following structural components: The epitaxial layers, including N-type GaN, a quantum well structure, and P-type GaN, were originally disposed on a sapphire substrate, which was removed in subsequent processing; The first protective layer, with a thickness of 50-500nm, is selected from SiO2 or SiN x , covering the N-type gallium nitride epitaxial layer and forming a desired pattern; An ITO transparent conductive layer is disposed on the first protective layer and is used to provide a transparent conductive path and connect to the P-type gallium nitride of the epitaxial layer, and its thickness is controlled between 10nm and 300nm; The first metal electrode layer is formed on the ITO transparent conductive layer and the N-type gallium nitride of the epitaxial layer by physical vapor deposition, and the material is Cr, Ti, Al, Ag, Ni, Pt or Au, and the total thickness is controlled at 1-2.5um; The Bragg reflector is composed of a stack of SiO2 / TiO materials, used to enhance light reflectivity, and is engraved through the first metal electrode layer to achieve connection between the first electrode layer and the second electrode layer; The second metal electrode layer covers the Bragg reflector and is made of Cr, Ti, Al, Ag, Ni, Pt or Au, with a total thickness of 2-4 um, and passes through the Bragg reflector to connect with the first metal electrode layer; The second protective layer is selected from SiO2 or SiN x , covering the second metal electrode layer and passing through the second metal electrode layer to connect with the Bragg reflector; The third metal electrode layer, i.e., the P / N pad, is disposed on the second protective layer and is connected to the second metal electrode layer through the second protective layer. The material is Cr, Ti, Al, Ag, Ni, Pt, Au, AuSn or Sn, and the total thickness is controlled at 2-10 um, for providing the final electrical connection; The P / N pad thickening layer is connected to the third metal electrode layer and is thickened to 20-100um by chemical plating, electroplating or printing; The stress buffer layer is filled around the P / N pad and is made of organic resin or SOG insulating material. It is designed to buffer the stress generated during the laser lift-off process or the die bonding process to prevent the epitaxial layer from cracking.

2. The thin film flip-chip LED chip according to claim 1, characterized in that: The total thickness of the first metal electrode layer is controlled at 2 um.

3. The thin film flip-chip LED chip according to claim 1, characterized in that: The total thickness of the second metal electrode layer is controlled at 3 um.

4. The thin film flip-chip LED chip according to claim 1, characterized in that: The thickness of the transparent conductive layer is controlled between 10nm and 300nm. 5 . The thin-film flip-chip LED chip according to claim 1 , wherein the thickness of the stress buffer layer is equal to the height of the thickened P / N pad.

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