Navigation computer circuit core board

Abstract

The utility model provides a navigation computer circuit core board which comprises a core board, a micro control unit MCU and a field programmable gate array FPGA, the micro control unit MCU and the field programmable gate array FPGA are embedded in the core board, the core board is connected with a bottom board through a board connector, and the MCU is connected with a FLASH memory through an SDIO and performs read-write operation on the FLASH memory; the crystal oscillator is connected with the MCU and the FPGA and provides a frequency source; the linear voltage regulator LDO converts an external power supply into an internal power supply to supply power to each component; the number of the programming interfaces is two, and the programming interfaces are used for programming MCU and FPGA software; the MCU accesses the FPGA through an EXMC parallel bus; and the data acquisition interface and the external communication interface are arranged on pins of the inter-board connector. According to the utility model, the most complicated core part of the navigation computer circuit can be solidified, and the navigation computer circuit has the advantages of high performance, low cost, low power consumption, small size, abundant interfaces, simplicity and convenience in development and the like.

Description

Technical Field

[0001] The utility model patent provides a core board used in a navigation computer circuit, belonging to the technical field of navigation circuits. Background Art

[0002] The inertial navigation device is installed in the vehicle, does not rely on external information, and measures the instantaneous speed and position of the vehicle by collecting the acceleration and angular velocity information of the inertial sensitive device in real time. In the inertial navigation device, the navigation computer circuit is generally used to collect and solve the inertial sensitive device in real time, and output the navigation information. The inertial navigation device has high requirements on the computing power of the navigation computer circuit. Prior art such as "Chen Bin et al. Encrypted Navigation Computer Circuit: CN109255258B[P]. 2020-07-14" mostly uses a digital signal processor (DSP) as the core processor to complete the navigation solution. Since the inertial navigation device is installed in different vehicles, the navigation computer circuit needs to adapt to different installation sizes and communication interfaces. Therefore, for different vehicles, it is often necessary to customize and design different navigation computer circuits to meet the requirements of the vehicle.

[0003] In summary, the existing technology has the following disadvantages in terms of navigation computer circuits: 1. The traditional DSP processor platform is old, and the development environment does not support the existing operating system. The processor has high power consumption, high price, insufficient interfaces, and is generally large in size, which no longer meets the current development trend of navigation computer circuits. 2. Navigation computer circuits need to adapt to different installation environments and communication interface requirements, and often need to be customized and redesigned. However, the core functions of the actual navigation computer circuit are relatively fixed, requiring a field programmable logic chip (FPGA) to complete data acquisition and establish a communication interface, as well as a processor chip to complete inertial information solution. Moreover, the design process of this part is the most cumbersome and time-consuming. Each custom design requires re-completing the principle design, printed circuit board design, and developing the corresponding underlying driver, resulting in a large waste of design resources. Utility Model Content

[0004] In view of the deficiencies in the prior art, this utility model patent adopts a core board solution, independently designs the core part of the navigation computer circuit with relatively fixed functions but complex circuits, and electrically connects it to the base plate through the inter-board connector, and expands the function according to different customized requirements. In this way, the most core and complex core part of the navigation computer circuit is solidified, shortening the development cycle and reducing development costs and risks. In addition, this utility model patent adopts a domestically produced high-performance microcontroller unit (MCU) as the core processor, thereby achieving the purpose of replacing the DSP chip, and has the advantages of high performance, low cost, low power consumption, small size, rich interfaces, and easy development.

[0005] The technical solution adopted to achieve the above-mentioned purpose of the utility model is:

[0006] A navigation computer circuit core board, comprising at least a core board and a microcontroller unit MCU and a field programmable gate array FPGA embedded in the core board, wherein the core board is connected to a base board through a board connector;

[0007] The microcontroller unit MCU uses a 32-bit domestic H7 series processor, and the field programmable gate array FPGA uses a domestic GW1N-9C series FPGA chip; the microcontroller unit MCU accesses the field programmable gate array FPGA through the external memory controller EXMC parallel bus, and the field programmable gate array FPGA is internally provided with RAM or registers for the microcontroller unit MCU to read and write at any time through the EXMC bus;

[0008] The core board also includes:

[0009] FLASH memory, the microcontroller unit MCU is connected to the FLASH memory through the secure data input and output interface SDIO and performs read and write operations on the FLASH memory;

[0010] The crystal oscillator is connected to the microcontroller unit MCU and the field programmable gate array FPGA and provides a frequency source;

[0011] The linear regulator LDO converts the external +5V power supply into an internal +3.3V power supply to power the microcontroller unit MCU, field programmable gate array FPGA, FLASH memory, and crystal oscillator;

[0012] Two programming interfaces are provided, and the two programming interfaces are respectively connected to the microcontroller unit MCU and the field programmable gate array FPGA, and are used for programming the software of the microcontroller unit MCU and the field programmable gate array FPGA;

[0013] The data acquisition interface is arranged on the pins of the inter-board connector, including a gyroscope data interface, a meter pulse acquisition interface, a satellite navigation data interface, a second pulse acquisition interface, an odometer acquisition interface, and a temperature sensor communication interface. The above data acquisition interface is electrically connected to the microcontroller unit MCU or the field programmable gate array FPGA;

[0014] The external communication interface is arranged on the pins of the inter-board connector, including the serial peripheral interface SPI, the controller area network bus CAN, the universal asynchronous serial transceiver UART, and the universal serial bus USB. The above external communication interface is electrically connected to the microcontroller unit MCU or the field programmable gate array FPGA and is used to communicate with external devices.

[0015] Furthermore, the microcontroller unit MCU adopts a domestic H7 series processor, a BGA176 package, a size of 10mm×10mm, a power consumption of no more than 1.2W, and integrates 1MB of SRAM storage space and 2MB of FLASH storage space.

[0016] Furthermore, the field programmable gate array FPGA adopts the domestic GW1N-9C series chips, has 9K programmable logic resources, and has a size of 11mm×11mm.

[0017] Furthermore, an A / D acquisition interface is also provided on the pins of the inter-board connector, which is connected to the microcontroller unit MCU for collecting analog signals as a function expansion.

[0018] Furthermore, the pins of the inter-board connector are also provided with I / O interfaces, which are connected to the field programmable gate array FPGA for inputting or outputting digital signals as function expansion.

[0019] Compared with the prior art, the navigation computer circuit core board provided by the utility model has the following advantages: 1. After adopting the navigation computer core board proposed by the utility model, when designing a new navigation computer circuit, there is no need to redesign the core part of the navigation computer. It is only necessary to install the inter-board connector on the base plate and install the navigation computer core board on the base plate. According to the actual functional requirements, the required electrical functions or extended functions can be brought out on the base plate, saving the design work of the core part. The inter-board connector adopts a detachable installation form, which is convenient for later maintenance or replacement.

[0020] 2. The navigation computer core board proposed by the utility model has multiple electrical interfaces to meet the collection and processing of various navigation information, including fiber optic gyro data interface, meter pulse collection, satellite navigation data collection, odometer collection, second pulse collection, inertial data collection of temperature sensor data collection, and various communication interfaces such as SPI, CAN, UART, USB, etc. for data transmission, as well as A / D analog quantity collection, configurable I / O and other function expansion interfaces.

[0021] 3. This utility model adopts the embedded computer architecture of domestic H7 series microcontroller unit (MCU) + field programmable gate array (FPGA). The domestic H7 series microcontroller unit (MCU) adopted is the microprocessor with the highest performance among the domestic MCU chips in China. It has the advantages of high performance, low power consumption, low cost, small size, and localization. It is newer than the traditional digital signal processor (DSP) technology, has higher performance, lower power consumption, and richer interfaces. At the same time, all components used in the navigation computer core board in this patent are domestic components, which can meet the national localization requirements. And the cost is low, with broad application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram of the connection and installation of the navigation computer circuit core board provided by the utility model;

[0023] Figure 2 A module connection block diagram of the navigation computer circuit core board provided by the utility model;

[0024] In the figure: 1-core board, 2-inter-board connector, 3-base board. DETAILED DESCRIPTION

[0025] The present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments, but the protection scope of the present invention is not limited to the following embodiments.

[0026] The connection and installation method of the navigation computer circuit core board provided in this embodiment is as follows Figure 1 As shown, the core board 1 is connected to the base board 3 via the board connector 2, and the board connector 2 adopts a detachable installation form to facilitate later maintenance or replacement.

[0027] The principle block diagram of the navigation computer circuit core board is as follows: Figure 2 As shown, refer to Figure 2 The core board adopts the embedded computer architecture of microcontroller unit (MCU) + field programmable gate array (FPGA), and also includes memory chip, power conversion chip, crystal oscillator, software burning interface, inter-board connector, etc.

[0028] The microcontroller unit (MCU) uses a 32-bit domestic H7 series processor with a main frequency of up to 600MHz and rich interface resources. The MCU chip uses a BGA176 package with a size of 10mm×10mm. The power consumption is no more than 1.2W, and the chip integrates 1MB of SRAM storage space and 2MB of FLASH storage space. It has certain advantages over traditional DSP chips in terms of computing power, size, power consumption, cost, interface resources, storage space, etc.

[0029] As a semi-customized chip in the field of application-specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) not only solve the problems of high cost and long development cycle of customized chips, but also have the advantages of flexibility and scalability. The functions of the chip can be semi-customized through behavioral hardware description languages. Since MCU chips have richer interface resources than traditional DSP chips, many standard interface functions can be completed in the MCU, which greatly reduces the demand for FPGA logic resources of the navigation computer core board. The utility model adopts the GW1N-9C series of domestic FPGA chips, which have about 9K programmable logic resources and a size of 11mm×11mm. The FPGA chip mainly completes the establishment of some non-standard interfaces on the periphery of the navigation computer core board, and the configurable input / output (I / O) interface led to the outside of the core board can improve the scalability of the core board.

[0030] After the navigation computer core board is powered on, the FPGA chip resets the MCU chip. The MCU chip accesses the FPGA chip through the external memory controller (EXMC) parallel bus to complete the high-speed communication between the MCU chip and the FPGA chip. The FPGA chip establishes internal RAM or registers according to the asynchronous timing requirements of the EXMC bus, which can be read and written at any time by the MCU chip through the EXMC bus to realize data interaction.

[0031] The navigation computer core board contains a large-capacity FLASH memory. The MCU chip reads and writes the memory through the secure data input and output (SDIO) interface to store system calibration parameters, historical navigation data, etc. It also contains a crystal oscillator to provide a frequency source for the MCU chip and FPGA chip; and a linear regulator (LDO) to convert the external +5V power supply into an internal +3.3V power supply to power the MCU chip, FPGA chip, memory, crystal oscillator, etc. The core board also contains two burning interfaces, which are used to burn the software of the MCU chip and FPGA chip respectively.

[0032] Various data acquisition interfaces and communication interfaces established by the MCU chip and the FPGA chip are electrically connected to the pins of the inter-board connector, including: a) gyro data interface, used to collect fiber optic gyro measurement data and obtain angular velocity information; b) meter pulse acquisition interface, used to collect meter pulse signals and obtain acceleration information; c) satellite navigation data interface, used to collect satellite navigation data and obtain satellite navigation information; d) second pulse acquisition interface, used to collect second pulse signals sent by Beidou satellites to obtain time reference; e) odometer acquisition interface, used to collect odometer data and obtain mileage information; f) temperature sensor communication interface, used to communicate with temperature sensors to obtain temperature information; g) A / D acquisition interface, used to collect analog signals, which can be used as function expansion; h) configurable I / O interface, the specific functions of which can be flexibly configured by the FPGA chip, which can be used as function expansion. In addition to the above acquisition interfaces, external communication interfaces are also set up, including serial peripheral interface (SPI), controller area network bus (CAN), universal asynchronous serial transceiver (UART), and universal serial bus (USB), which are used to communicate with external devices.

[0033] The present invention proposes a solution of using a core board, and arranges the above functions on a very small core board, which is only 48mm×32mm in size. The core board is connected to the base board through an inter-board connector, and function selection and function expansion can be performed on the base board according to actual design requirements.

Claims

1. A navigation computer circuit core board, comprising at least a core board and a microcontroller unit MCU and a field programmable gate array FPGA embedded in the core board, wherein the core board is connected to a base board through a board connector, and characterized in that: The microcontroller unit MCU uses a 32-bit domestic H7 series processor, and the field programmable gate array FPGA uses a domestic GW1N-9C series FPGA chip; the microcontroller unit MCU accesses the field programmable gate array FPGA through the external memory controller EXMC parallel bus, and the field programmable gate array FPGA is internally provided with RAM or registers for the microcontroller unit MCU to read and write at any time through the EXMC bus; The core board also includes: FLASH memory, the microcontroller unit MCU is connected to the FLASH memory through the secure data input and output interface SDIO and performs read and write operations on the FLASH memory; The crystal oscillator is connected to the microcontroller unit MCU and the field programmable gate array FPGA and provides a frequency source; The linear regulator LDO converts the external +5V power supply into an internal +3.3V power supply to power the microcontroller unit MCU, field programmable gate array FPGA, FLASH memory, and crystal oscillator; Two programming interfaces are provided, and the two programming interfaces are respectively connected to the microcontroller unit MCU and the field programmable gate array FPGA, and are used for programming the software of the microcontroller unit MCU and the field programmable gate array FPGA; The data acquisition interface is arranged on the pins of the inter-board connector, including a gyroscope data interface, a meter pulse acquisition interface, a satellite navigation data interface, a second pulse acquisition interface, an odometer acquisition interface, and a temperature sensor communication interface. The above data acquisition interface is electrically connected to the microcontroller unit MCU or the field programmable gate array FPGA; The external communication interface is arranged on the pins of the inter-board connector, including the serial peripheral interface SPI, the controller area network bus CAN, the universal asynchronous serial transceiver UART, and the universal serial bus USB. The above external communication interface is electrically connected to the microcontroller unit MCU or the field programmable gate array FPGA and is used to communicate with external devices.

2. The navigation computer circuit core board according to claim 1, characterized in that: The microcontroller unit MCU adopts a domestic H7 series processor, a BGA176 package, a size of 10mm×10mm, a power consumption of no more than 1.2W, and integrates 1MB of SRAM storage space and 2MB of FLASH storage space.

3. The navigation computer circuit core board according to claim 1, characterized in that: The field programmable gate array FPGA adopts the domestic GW1N-9C series chips, has 9K programmable logic resources, and has a size of 11mm×11mm.

4. The navigation computer circuit core board according to claim 1, characterized in that: The pins of the inter-board connector are also provided with an A / D acquisition interface, which is connected to the microcontroller unit MCU for collecting analog signals as a function expansion.

5. The navigation computer circuit core board according to claim 1, characterized in that: The pins of the inter-board connector are also provided with a configurable I / O interface, which is connected to a field programmable gate array FPGA for inputting or outputting digital signals as a function expansion.

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