Accurate power consumption testing device for memory

Abstract

The utility model belongs to the field of memory testing, and discloses a memory accurate power consumption testing device which comprises a memory testing mainboard, the memory testing mainboard comprises a memory slot and a power supply module, and the output end of the power supply module is electrically connected with the power supply input end of the memory slot; the sampling end of the current acquisition module is connected in series in a power supply loop between the output end of the power supply module and the power supply input end of the memory slot, and the current acquisition module is used for acquiring the working current of the to-be-tested memory after the to-be-tested memory is inserted into the memory slot; the signal input end of the controller is connected with the signal output end of the current acquisition module, and the controller is used for outputting the total power consumption of the memory to be tested after the working current, acquired by the current acquisition module, of the memory to be tested is input. According to the utility model, the power consumption test accuracy of the memory to be tested is improved.

Description

Technical Field

[0001] The utility model belongs to the field of memory testing, and specifically relates to a memory precise power consumption testing device. Background Art

[0002] RDIMM (Registered DIMM) is a type of memory module. RDIMM is designed to provide lower access latency and is widely used in server and workstation environments that require large amounts of memory and high data integrity.

[0003] Power consumption testing of RDIMM memory is an important process used to evaluate the energy efficiency and performance of memory modules, which can help manufacturers and users understand the energy consumption of memory modules under actual working conditions.

[0004] The mainstream method in the industry is to determine the power consumption by reading the registers of the output voltage and current values ​​of the PMIC such as VDD, VDDQ, and VPP on the RDIMM. However, this power consumption test is restricted by the following factors:

[0005] 1. The output current register of the PMIC feeds back a range value with a step size of 125mA, which is not very accurate;

[0006] 2. Since the PMIC register can only feedback the output power consumption of the PMIC, it is impossible to measure the loss of the PMIC itself.

[0007] 3. The PMIC itself cannot measure the power consumption of another 3.3V power supply on the RDIMM.

[0008] Therefore, the existing power consumption test is restricted by at least the above three factors, resulting in inaccurate power consumption. Utility Model Content

[0009] The utility model aims to provide a memory accurate power consumption test device to solve the problem that the existing power consumption test is restricted by factors and thus causes inaccurate power consumption.

[0010] In order to achieve the above purpose, the utility model adopts the following technical solution: a memory precise power consumption test device, the device comprising:

[0011] A memory test mainboard, the memory test mainboard comprising: a memory slot and a power module, the output end of the power module being electrically connected to the power input end of the memory slot;

[0012] A current acquisition module, wherein a sampling end of the current acquisition module is connected in series in a power supply circuit between an output end of the power module and a power input end of the memory slot, and is used to collect a working current of the memory to be tested after the memory to be tested is inserted into the memory slot;

[0013] A controller, wherein the signal input end of the controller is connected to the signal output end of the current acquisition module, and the controller is used to output the total power consumption of the memory to be tested after the working current of the memory to be tested collected by the current acquisition module is input.

[0014] Preferably, the memory to be tested is an RDIMM memory, the memory slot includes two power input terminals, and there are two power supply loops between the output terminal of the power module and the power input terminal of the memory slot;

[0015] The current acquisition module includes: a first current acquisition submodule and a second current acquisition submodule, wherein the sampling end of the first current acquisition submodule is connected in series in one of the power supply circuits; the sampling end of the second current acquisition submodule is connected in series in another power supply circuit; the signal output end of the first current acquisition submodule and the signal output end of the second current acquisition submodule are both connected to the signal input end of the controller.

[0016] Preferably, the first current acquisition submodule includes: an acquisition chip U1 and a first sampling circuit, with two input ends of the first sampling circuit being connected in series in one of the power supply circuits as sampling ends, the first sampling circuit being used to convert the working current of one of the power supply circuits into a first voltage signal, the first sampling circuit inputs the first voltage signal to the acquisition chip U1, and the communication port of the acquisition chip U1 serves as the signal output end of the first current acquisition submodule.

[0017] Preferably, a first electronic protector is connected in series between the output end of the power module and the sampling end of the first sampling circuit, and a controlled end of the first electronic protector is connected to a first control end of the controller.

[0018] Preferably, the first sampling circuit comprises: a sampling resistor R10, a resistor R11, a resistor R12, a capacitor C10 and a capacitor C11;

[0019] The two ends of the sampling resistor R10 are respectively two input ends of the first sampling circuit, the two ends of the sampling resistor R10 are connected in series in one of the power supply loops, the first end of the sampling resistor R10 is respectively connected to the first end of the capacitor C10 and the first end of the resistor R11, and the second end of the resistor R11 is respectively connected to the first end of the capacitor C11 and the first input end of the acquisition chip U1;

[0020] The second end of the sampling resistor R10 is respectively connected to the power supply input end of the acquisition chip U1 and the first end of the resistor R12, and the second end of the resistor R12 is respectively connected to the second end of the capacitor C11 and the second input end of the acquisition chip U1;

[0021] A second terminal of the capacitor C10 is grounded.

[0022] Preferably, the second current acquisition submodule includes: an acquisition chip U2 and a second sampling circuit, with two input ends of the second sampling circuit being connected in series in another power supply circuit as sampling ends, the second sampling circuit being used to convert the working current of the other power supply circuit into a second voltage signal, the second sampling circuit inputting the second voltage signal to the acquisition chip U2, and the communication port of the acquisition chip U2 being used as the signal output end of the second current acquisition submodule.

[0023] Preferably, a second electronic protector is connected in series between the output end of the power module and the sampling end of the second sampling circuit, and a controlled end of the second electronic protector is connected to a second control end of the controller.

[0024] Preferably, the second sampling circuit comprises: a sampling resistor R20, a resistor R21, a resistor R22, a capacitor C20 and a capacitor C21;

[0025] The two ends of the sampling resistor R20 are respectively two input ends of the second sampling circuit, the two ends of the sampling resistor R20 are connected in series in another power supply loop, the first end of the sampling resistor R20 is respectively connected to the first end of the capacitor C20 and the first end of the resistor R21, and the second end of the resistor R21 is respectively connected to the first end of the capacitor C21 and the first input end of the acquisition chip U2;

[0026] The second end of the sampling resistor R20 is respectively connected to the power supply input end of the acquisition chip U2 and the first end of the resistor R22, and the second end of the resistor R22 is respectively connected to the second end of the capacitor C21 and the second input end of the acquisition chip U2;

[0027] A second terminal of the capacitor C20 is grounded.

[0028] Preferably, the memory test mainboard also includes:

[0029] A processor, wherein a plurality of IO ports of the processor are respectively connected to a corresponding signal output end of the controller and a plurality of signal ports of a memory slot.

[0030] Preferably, the controller is a BMC controller.

[0031] Beneficial effects:

[0032] During the power consumption test of the memory to be tested, the utility model collects the working current in the power supply circuit between the output end of the power supply module and the power input end of the memory slot through the current acquisition module, and the current acquisition module uploads the working current to the controller. The controller can calculate the total power consumption of the memory to be tested according to the working current value, and the total power consumption includes the self-loss of the memory to be tested, so as to improve the accuracy of the power consumption test of the memory to be tested. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings are used to provide a further understanding of the embodiments of the present utility model and constitute a part of the specification. Together with the following specific implementations, they are used to explain the embodiments of the present utility model, but do not constitute a limitation on the embodiments of the present utility model. In the accompanying drawings:

[0034] Figure 1 It is a block diagram of a memory precise power consumption test device provided by one embodiment of the utility model;

[0035] Figure 2 This is a schematic diagram of a first current acquisition submodule provided in one embodiment of the utility model;

[0036] Figure 3 It is a schematic diagram of a second current acquisition submodule provided in one embodiment of the utility model. DETAILED DESCRIPTION

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the utility model or the prior art, the utility model will be briefly introduced below in combination with the drawings and the description of the embodiments or the prior art. Obviously, the following description of the structure of the drawings is only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. It should be noted that the description of these embodiments is used to help understand the utility model, but does not constitute a limitation of the utility model.

[0038] Figure 1 is a block diagram of a memory precise power consumption test device provided by an embodiment of the utility model, such as Figure 1 As shown, this embodiment provides a memory precise power consumption test device, the device comprising: a memory test mainboard, a current acquisition module and a controller;

[0039] The memory test mainboard comprises: a memory slot and a power module, wherein the output end of the power module is electrically connected to the power input end of the memory slot;

[0040] The sampling end of the current acquisition module is connected in series in the power supply circuit between the output end of the power module and the power input end of the memory slot, and is used to collect the working current of the memory to be tested after the memory to be tested is inserted into the memory slot;

[0041] The signal input end of the controller is connected to the signal output end of the current acquisition module. The controller is used to output the total power consumption of the memory to be tested after inputting the working current of the memory to be tested acquired by the current acquisition module.

[0042] In this embodiment, the controller is a BMC controller (Baseboard Management Controller). The BMC controller reads the working current of the memory to be tested collected by the current collection module through the I²C bus. The BMC controller can calculate the total power consumption of the memory to be tested according to the working current.

[0043] Therefore, during the power consumption test of the memory to be tested, the utility model collects the working current in the power supply circuit between the output end of the power supply module and the power input end of the memory slot through the current acquisition module, and the current acquisition module uploads the working current to the controller. The controller can calculate the total power consumption of the memory to be tested based on the working current value, and the total power consumption includes the self-loss of the memory to be tested, so as to improve the accuracy of the power consumption test of the memory to be tested.

[0044] As a further optimization of this embodiment, the memory to be tested is RDIMM memory, such as DDR5_RDIMM memory, or other models of DDR5 memory, and the memory slot includes two power input terminals, and there are two power supply circuits between the output terminal of the power module and the power input terminal of the memory slot; in this embodiment, DDR5_RDIMM memory is a memory of the DDR5 memory standard, and DDR5_RDIMM memory has two voltage inputs, namely +12V DC voltage input and +3.3V DC voltage; therefore, the power module has two power output terminals, one of which outputs a voltage of +12V, and the other outputs a voltage of +3.3V. At this time, there are two power supply circuits between the memory slot and the power module, one of which has a voltage of +12V, and the other has a voltage of +3.3V.

[0045] Since there are two power supply circuits, the current acquisition module includes: a first current acquisition submodule and a second current acquisition submodule, the sampling end of the first current acquisition submodule is connected in series in one of the power supply circuits; the sampling end of the second current acquisition submodule is connected in series in the other power supply circuit; the signal output end of the first current acquisition submodule and the signal output end of the second current acquisition submodule are both connected to the signal input end of the controller, and the first current acquisition submodule and the second current acquisition submodule are used to respectively acquire the working currents in the two power supply circuits.

[0046] As a further optimization of this embodiment, Figure 2As shown, the first current acquisition submodule includes: an acquisition chip U1 and a first sampling circuit, with two input terminals of the first sampling circuit being connected in series in one of the power supply circuits as sampling terminals, the first sampling circuit being used to convert the working current of one of the power supply circuits into a first voltage signal, the first sampling circuit inputting the first voltage signal to the acquisition chip U1, and the communication port of the acquisition chip U1 being used as the signal output terminal of the first current acquisition submodule.

[0047] Specifically, the first sampling circuit includes: a sampling resistor R10, a resistor R11, a resistor R12, a capacitor C10 and a capacitor C11;

[0048] The two ends of the sampling resistor R10 are respectively two input ends of the first sampling circuit, the two ends of the sampling resistor R10 are connected in series in one of the power supply loops, the first end of the sampling resistor R10 is respectively connected to the first end of the capacitor C10 and the first end of the resistor R11, and the second end of the resistor R11 is respectively connected to the first end of the capacitor C11 and the first input end of the acquisition chip U1;

[0049] The second end of the sampling resistor R10 is respectively connected to the power supply input end of the acquisition chip U1 and the first end of the resistor R12, and the second end of the resistor R12 is respectively connected to the second end of the capacitor C11 and the second input end of the acquisition chip U1;

[0050] A second terminal of the capacitor C10 is grounded.

[0051] In this embodiment, the acquisition chip U1 adopts the INA226AIDGSR chip. The resolution of the INA226AIDGSR chip is 1 mA, which can improve the test accuracy of the current and further improve the power consumption test accuracy of the memory to be tested.

[0052] In this embodiment, the sampling resistor R10 is connected in series to the +12V power supply circuit. At this time, the sampling resistor R10 converts the working current into a first voltage signal. After the acquisition chip U1 receives the first voltage signal, the working current of the +12V power supply circuit can be calculated according to the resistance value of the sampling resistor R10. The acquisition chip U1 uploads the collected working current to the controller, and then the controller can calculate the power consumption of the +12V power supply circuit; wherein, the capacitor C10 and the capacitor C11 play a filtering role to improve the test accuracy of the working current.

[0053] In this embodiment, in order to improve the safety of the +12V power supply circuit, a first electronic protector is connected in series between the output end of the power module and the sampling end of the first sampling circuit, and the controlled end of the first electronic protector is connected to the first control end of the controller; wherein the first electronic protector adopts an electronic fuse (Efuse IC), when the working current of the +12V power supply circuit uploaded by the acquisition chip U1 of the first sampling circuit exceeds the threshold value, the controller outputs a control signal to control the electronic fuse to cut off the +12V power supply circuit.

[0054] As a further optimization of this embodiment, Figure 3 As shown, the second current acquisition submodule includes: an acquisition chip U2 and a second sampling circuit, with two input ends of the second sampling circuit being connected in series in another power supply circuit as sampling ends, the second sampling circuit being used to convert the working current of the other power supply circuit into a second voltage signal, the second sampling circuit inputting the second voltage signal to the acquisition chip U2, and the communication port of the acquisition chip U2 being used as the signal output end of the second current acquisition submodule.

[0055] The second sampling circuit includes: a sampling resistor R20, a resistor R21, a resistor R22, a capacitor C20 and a capacitor C21;

[0056] The two ends of the sampling resistor R20 are respectively two input ends of the second sampling circuit, the two ends of the sampling resistor R20 are connected in series in another power supply loop, the first end of the sampling resistor R20 is respectively connected to the first end of the capacitor C20 and the first end of the resistor R21, and the second end of the resistor R21 is respectively connected to the first end of the capacitor C21 and the first input end of the acquisition chip U2;

[0057] The second end of the sampling resistor R20 is respectively connected to the power supply input end of the acquisition chip U2 and the first end of the resistor R22, and the second end of the resistor R22 is respectively connected to the second end of the capacitor C21 and the second input end of the acquisition chip U2;

[0058] A second terminal of the capacitor C20 is grounded.

[0059] In this embodiment, the acquisition chip U2 adopts the INA226AIDGSR chip. The resolution of the INA226AIDGSR chip is 1 mA, which can improve the test accuracy of the current and further improve the power consumption test accuracy of the memory to be tested.

[0060] In this embodiment, the sampling resistor R20 is connected in series to the +3.3V power supply circuit. At this time, the sampling resistor R20 converts the working current into a second voltage signal. After the acquisition chip U2 receives the second voltage signal, the working current of the +3.3V power supply circuit can be calculated according to the resistance value of the sampling resistor R20. The acquisition chip U2 uploads the collected working current to the controller, and then the controller can calculate the power consumption of the +3.3V power supply circuit; wherein, the capacitor C20 and the capacitor C21 play a filtering role to improve the test accuracy of the working current.

[0061] The controller can obtain the total power consumption of the memory to be tested by adding the power consumption of the +12V power supply circuit calculated and the power consumption of the +3.3V power supply circuit calculated.

[0062] Secondly, the controller can also compare the actual working current measured at different stages with the calibrated current value to identify whether the memory may have hardware problems caused by devices or welding. For example, if the working current is much larger than the calibrated value, there is a short circuit problem; if the working current is much smaller than the calibrated value or approaches 0, there is an open circuit problem; if the working current is greater than or less than ±20% of the calibrated value at different stages of the operation of specific test software, a memory particle in the memory stick is not working properly.

[0063] Since the utility model samples and analyzes both input voltages on the DDR5_RDIMM memory, it is easy to distinguish which power supply has failed.

[0064] In this embodiment, in order to improve the safety of the +3.3V power supply circuit, a second electronic protector is connected in series between the output end of the power module and the sampling end of the second sampling circuit, and the controlled end of the second electronic protector is connected to the second control end of the controller; wherein the second electronic protector adopts an electronic fuse (Efuse IC), when the working current of the +3.3V power supply circuit uploaded by the acquisition chip U2 of the second sampling circuit exceeds the threshold value, the controller outputs a control signal to control the electronic fuse to cut off the +3.3V power supply circuit.

[0065] As a further optimization of this embodiment, the memory test mainboard further includes:

[0066] A processor, wherein the multiple IO ports of the processor are respectively connected to the corresponding signal output end of the controller and the multiple signal ports of the memory slot. The processor can adopt a single-chip microcomputer of the STM32 series, and the single-chip microcomputer is used to perform a comprehensive test on the entire memory to be tested.

[0067] The testing device of the utility model can accurately measure the overall power consumption of the memory stick, and can also determine the memory stick with an open short circuit fault according to the working current, and specifically locate which of the two power supply sources the fault point is, and actively provide overcurrent protection through the first electronic protector and the second electronic protector.

[0068] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A memory precise power consumption test device, characterized in that: The device comprises: A memory test mainboard, the memory test mainboard comprising: a memory slot and a power module, the output end of the power module being electrically connected to the power input end of the memory slot; A current acquisition module, wherein a sampling end of the current acquisition module is connected in series in a power supply circuit between an output end of the power module and a power input end of the memory slot, and is used to collect a working current of the memory to be tested after the memory to be tested is inserted into the memory slot; A controller, wherein the signal input end of the controller is connected to the signal output end of the current acquisition module, and the controller is used to output the total power consumption of the memory to be tested after the working current of the memory to be tested collected by the current acquisition module is input.

2. The memory precise power consumption test device according to claim 1, characterized in that: The memory to be tested is an RDIMM memory, the memory slot includes two power input terminals, and there are two power supply circuits between the output terminal of the power module and the power input terminal of the memory slot; The current acquisition module includes: a first current acquisition submodule and a second current acquisition submodule, wherein the sampling end of the first current acquisition submodule is connected in series in one of the power supply circuits; the sampling end of the second current acquisition submodule is connected in series in another power supply circuit; the signal output end of the first current acquisition submodule and the signal output end of the second current acquisition submodule are both connected to the signal input end of the controller.

3. The memory precise power consumption test device according to claim 2, characterized in that: The first current acquisition submodule includes: an acquisition chip U1 and a first sampling circuit, with two input ends of the first sampling circuit being connected in series in one of the power supply circuits as sampling ends, the first sampling circuit being used to convert the working current of one of the power supply circuits into a first voltage signal, the first sampling circuit inputting the first voltage signal to the acquisition chip U1, and the communication port of the acquisition chip U1 being used as a signal output end of the first current acquisition submodule.

4. The memory precise power consumption test device according to claim 3, characterized in that: A first electronic protector is connected in series between the output end of the power module and the sampling end of the first sampling circuit, and a controlled end of the first electronic protector is connected to a first control end of the controller.

5. The memory precise power consumption test device according to claim 3, characterized in that: The first sampling circuit includes: a sampling resistor R10, a resistor R11, a resistor R12, a capacitor C10 and a capacitor C11; The two ends of the sampling resistor R10 are respectively two input ends of the first sampling circuit, the two ends of the sampling resistor R10 are connected in series in one of the power supply loops, the first end of the sampling resistor R10 is respectively connected to the first end of the capacitor C10 and the first end of the resistor R11, and the second end of the resistor R11 is respectively connected to the first end of the capacitor C11 and the first input end of the acquisition chip U1; The second end of the sampling resistor R10 is respectively connected to the power supply input end of the acquisition chip U1 and the first end of the resistor R12, and the second end of the resistor R12 is respectively connected to the second end of the capacitor C11 and the second input end of the acquisition chip U1; A second terminal of the capacitor C10 is grounded.

6. The memory precise power consumption test device according to claim 2, characterized in that: The second current acquisition submodule includes: an acquisition chip U2 and a second sampling circuit, with two input ends of the second sampling circuit being connected in series in another power supply circuit as sampling ends, and the second sampling circuit being used to convert the working current of the other power supply circuit into a second voltage signal, and the second sampling circuit inputs the second voltage signal to the acquisition chip U2, and the communication port of the acquisition chip U2 is used as the signal output end of the second current acquisition submodule.

7. The memory precise power consumption test device according to claim 6, characterized in that: A second electronic protector is connected in series between the output end of the power module and the sampling end of the second sampling circuit, and a controlled end of the second electronic protector is connected to a second control end of the controller.

8. The memory precise power consumption test device according to claim 6, characterized in that: The second sampling circuit includes: a sampling resistor R20, a resistor R21, a resistor R22, a capacitor C20 and a capacitor C21; The two ends of the sampling resistor R20 are respectively two input ends of the second sampling circuit, the two ends of the sampling resistor R20 are connected in series in another power supply loop, the first end of the sampling resistor R20 is respectively connected to the first end of the capacitor C20 and the first end of the resistor R21, and the second end of the resistor R21 is respectively connected to the first end of the capacitor C21 and the first input end of the acquisition chip U2; The second end of the sampling resistor R20 is respectively connected to the power supply input end of the acquisition chip U2 and the first end of the resistor R22, and the second end of the resistor R22 is respectively connected to the second end of the capacitor C21 and the second input end of the acquisition chip U2; A second terminal of the capacitor C20 is grounded.

9. The memory precise power consumption test device according to claim 1, characterized in that: The memory test mainboard also includes: A processor, wherein a plurality of IO ports of the processor are respectively connected to a corresponding signal output end of the controller and a plurality of signal ports of a memory slot.

10. The memory precise power consumption test device according to any one of claims 1 to 9, characterized in that: The controller is a BMC controller.

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