Semiconductor structure
By forming multi-layer doped regions and metal silicides in silicon carbide devices, the problem of insufficient performance and reliability of existing devices is solved, and higher performance and reliability are achieved.
Patent Information
- Application Number
- CN202421624271.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-09
- Publication Date
- 2025-05-02
- Estimated Expiration
- 2034-07-09
AI Technical Summary
The structure of existing silicon carbide devices (SiC MOSFETs) has problems with insufficient performance and reliability.
By forming multi-layer doped regions on the semiconductor substrate and forming metal silicides at specific locations, the contact area and electrical connectivity of the metal silicides are increased while optimizing the electric field distribution.
It improves the performance and reliability of the device, enhances the alignment accuracy and electrical connectivity of metal silicides, and improves the electric field distribution.
Smart Images
Figure CN222827574U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure. Background Art
[0002] Silicon carbide devices (SiC MOSFET) are semiconductor devices that are different from traditional silicon substrates. The structure of current silicon carbide devices still has defects, resulting in the inability to guarantee device performance and reliability.
[0003] Therefore, it is necessary to provide more effective and reliable technical solutions. Utility Model Content
[0004] The present application provides a semiconductor structure and a method for forming the same, which can form a first metal silicide by self-alignment, thereby improving the alignment accuracy of the first metal silicide; after etching a portion of the third doped region, the first metal silicide and the second metal silicide are formed, thereby increasing the contact area between the first metal silicide and the second metal silicide, and improving the electrical connectivity between the first metal silicide and the second metal silicide; and forming a second doped region transition between the first doped region and between the third doped region, thereby improving the electric field distribution and improving the device performance and reliability.
[0005] One aspect of the present application provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate, wherein an epitaxial layer is formed on the surface of the semiconductor substrate, wherein a first doped region, a second doped region located in the first doped region, and a third doped region located in the second doped region are formed in the epitaxial layer; forming a gate oxide layer and a gate layer on the surface of the epitaxial layer to expose a portion of the third doped region; etching the exposed third doped region to form a first opening; forming a first metal silicide in the first opening and forming a first metal layer on the surface of the gate layer; and forming an interlayer dielectric layer on the surfaces of the first metal silicide and the first metal layer.
[0006] In some embodiments of the present application, the material of the semiconductor substrate includes silicon carbide, the material of the epitaxial layer includes doped silicon carbide, and the material of the gate layer includes doped polysilicon.
[0007] In some embodiments of the present application, the doping type of the first doping region is opposite to the doping type of the epitaxial layer, the doping type of the second doping region is the same as the doping type of the first doping region, the doping type of the third doping region is opposite to the doping type of the second doping region, and the doping type of the gate layer is the same as the doping type of the epitaxial layer.
[0008] In some embodiments of the present application, the depth of the epitaxial layer is 4 to 40 microns, the depth of the first doping region is 0.6 to 2 microns, the depth of the second doping region is 0.8 to 2.4 microns, and the depth of the third doping region is 0.2 to 0.4 microns.
[0009] In some embodiments of the present application, the length of the gate oxide layer is greater than the length of the gate layer.
[0010] In some embodiments of the present application, a surface area of the gate layer is greater than a surface area of the third doping region at the bottom of the first opening.
[0011] In some embodiments of the present application, the depth of the first opening is 0.1 to 0.2 microns.
[0012] In some embodiments of the present application, a depth of the first metal silicide in the first opening is 0.1 to 1 micrometer.
[0013] In some embodiments of the present application, a top surface of the first metal silicide in the first opening is higher than a bottom surface of the gate oxide layer and lower than a top surface of the gate oxide layer.
[0014] In some embodiments of the present application, the semiconductor substrate includes a first region and a second region, and after forming the interlayer dielectric layer, it also includes: etching a portion of the interlayer dielectric layer and the first metal silicide in the second region to form a second opening exposing the third doped region; forming a second metal silicide in the second opening, and the second metal silicide is connected to the second doped region below the third doped region.
[0015] Another aspect of the present application also provides a semiconductor structure, including: a semiconductor substrate, an epitaxial layer formed on the surface of the semiconductor substrate, a first doped region, a second doped region located in the first doped region, and a third doped region located in the second doped region formed in the epitaxial layer, a gate oxide layer and a gate layer exposing a portion of the third doped region formed on the surface of the epitaxial layer; a first opening located in the exposed third doped region; a first metal silicide located in the first opening; and an interlayer dielectric layer located on the surface of the first metal silicide.
[0016] In some embodiments of the present application, the material of the semiconductor substrate includes silicon carbide, the material of the epitaxial layer includes doped silicon carbide, and the material of the gate layer includes doped polysilicon.
[0017] In some embodiments of the present application, the doping type of the first doping region is opposite to the doping type of the epitaxial layer, the doping type of the second doping region is the same as the doping type of the first doping region, the doping type of the third doping region is opposite to the doping type of the second doping region, and the doping type of the gate layer is the same as the doping type of the epitaxial layer.
[0018] In some embodiments of the present application, the depth of the epitaxial layer is 4 to 40 microns, the depth of the first doping region is 0.6 to 2 microns, the depth of the second doping region is 0.8 to 2.4 microns, and the depth of the third doping region is 0.2 to 0.4 microns.
[0019] In some embodiments of the present application, the length of the gate oxide layer is greater than the length of the gate layer.
[0020] In some embodiments of the present application, a surface area of the gate layer is greater than a surface area of the third doping region at the bottom of the first opening.
[0021] In some embodiments of the present application, the depth of the first opening is 0.1 to 0.2 microns.
[0022] In some embodiments of the present application, a depth of the first metal silicide in the first opening is 0.1 to 1 micrometer.
[0023] In some embodiments of the present application, a top surface of the first metal silicide in the first opening is higher than a bottom surface of the gate oxide layer and lower than a top surface of the gate oxide layer.
[0024] In some embodiments of the present application, the semiconductor substrate includes a first region and a second region, and a second opening exposing the third doped region is formed in the interlayer dielectric layer and the first metal silicide of the second region; a second metal silicide is formed in the second opening, and the second metal silicide is connected to a second doped region below the third doped region.
[0025] The present application provides a semiconductor structure and a method for forming the same, which can form a first metal silicide by self-alignment, thereby improving the alignment accuracy of the first metal silicide; after etching a portion of the third doped region, the first metal silicide and the second metal silicide are formed, thereby increasing the contact area between the first metal silicide and the second metal silicide, and improving the electrical connectivity between the first metal silicide and the second metal silicide; and forming a second doped region transition between the first doped region and between the third doped region, thereby improving the electric field distribution and improving the device performance and reliability. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] The following drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals represent similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are only for the purpose of illustration and description, and are not intended to limit the scope of this application. Other embodiments may also accomplish the utility model intention in this application. It should be understood that the drawings are not drawn to scale. Among them:
[0027] Figures 1 to 14 It is a structural schematic diagram of each step in the method for forming a semiconductor structure described in an embodiment of the present application;
[0028] Fig.15 Schematic diagram of the semiconductor structure described in some other embodiments of the present application. DETAILED DESCRIPTION
[0029] The following description provides specific application scenarios and requirements of the present application, with the purpose of enabling those skilled in the art to make and use the content in the present application. It will be apparent to those skilled in the art that various local modifications to the disclosed embodiments are apparent, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present application. Therefore, the present application is not limited to the embodiments shown, but to the widest scope consistent with the claims.
[0030] The technical solution of the utility model is described in detail below in conjunction with the embodiments and drawings.
[0031] Figures 1 to 14 The following is a schematic diagram of the structure of each step in the method for forming a semiconductor structure according to an embodiment of the present application. The method for forming a semiconductor structure according to an embodiment of the present application is described in detail in conjunction with the accompanying drawings.
[0032] refer to Figures 1 to 6 As shown, a semiconductor substrate 100 is provided, an epitaxial layer 110 is formed on the surface of the semiconductor substrate 100, and a first doping region 111, a second doping region 112 located in the first doping region 111, and a third doping region 113 located in the second doping region 112 are formed in the epitaxial layer 110.
[0033] refer to Figure 1 and Figure 2 As shown, Figure 1 is a top view, Figure 2 For along Figure 1A longitudinal cross-sectional view at the dotted line AA is provided. A semiconductor substrate 100 is provided. An epitaxial layer 110 is formed on the surface of the semiconductor substrate 100. The semiconductor substrate 100 includes a first region 101 and a second region 102. The first region 101 and the second region 102 are used to form different metal silicides, respectively.
[0034] In some embodiments of the present application, the semiconductor structure described in the embodiments of the present application is, for example, a silicon carbide MOSFET.
[0035] In some embodiments of the present application, the material of the semiconductor substrate 100 includes silicon carbide, and the material of the epitaxial layer 110 includes doped silicon carbide. The doping type of the epitaxial layer 110 is, for example, N-type. The depth H1 of the epitaxial layer 110 is 4 to 40 microns. The doping concentration of the epitaxial layer 110 is 2E15 atom / cm 3 To 3E16 atom / cm 3 .
[0036] refer to Figure 3 As shown, a hard mask layer 120 is formed on the surface of the epitaxial layer 110, and the hard mask layer 120 exposes a portion of the epitaxial layer 110. An ion implantation process is performed on the epitaxial layer 110 using the hard mask layer 120 as a mask to form a first doped region 111.
[0037] In some embodiments of the present application, the material of the hard mask layer 120 includes silicon oxide, silicon nitride, titanium nitride, etc.
[0038] In some embodiments of the present application, the first doping region 111 is PBase. The doping type of the first doping region 111 is opposite to the doping type of the epitaxial layer 110, for example, P type. The depth H2 of the first doping region 111 can be adjusted according to the required gate voltage, for example, 0.6 microns to 2 microns. The doping concentration of the first doping region 111 is, for example, 5E17atom / cm 3 To 3E19atom / cm 3 The first doping region 111 is used to control the threshold voltage and form a depletion region to isolate the N-type of the second doping region 112 and share part of the electric field.
[0039] refer to Figure 4 As shown, a sidewall spacer 121 is formed on the sidewall of the hard mask layer 120 . An ion implantation process is performed on the epitaxial layer 110 using the sidewall spacer 121 and the hard mask layer 120 as masks to form a second doping region 112 in the first doping region 111 .
[0040] In some embodiments of the present application, the material of the sidewall spacer 121 includes silicon oxide, silicon nitride, titanium nitride, or the like.
[0041] In some embodiments of the present application, the doping type of the second doping region 112 is the same as the doping type of the first doping region 111, for example, P-type. The depth H3 of the second doping region 112 can be deeper or shallower than the first doping region 111, generally 0.8 microns to 2.4 microns. The doping concentration of the second doping region 112 is, for example, 1E19atom / cm 3 To 1E21atom / cm 3 The function of the second doping region 112 is to make the P type form a better ohmic contact with the metal, and at the same time reduce the P type film resistance, reduce the voltage value of the parasitic diode, and reduce the conduction loss of the device.
[0042] refer to Figure 5 As shown, an ion implantation process is performed on the epitaxial layer 110 using the spacer 121 and the hard mask layer 120 as masks to form a third doping region 113 in the second doping region 112 .
[0043] In some embodiments of the present application, the doping type of the third doping region 113 is opposite to the doping type of the second doping region 112, for example, N-type. The depth H3 of the third doping region 113 is 0.2 to 0.4 microns. The doping concentration of the third doping region 113 is, for example, 1E19atom / cm 3 To 1E21atom / cm 3 The function of the third doping region 113 is to make the P-type and the metal form a better ohmic contact, reduce the RDSON value when the MOSFET is switched, and reduce the conduction loss of the device.
[0044] In the technical solution of the present application, the second doped region 112 makes the p-type junction shallower, reduces the width restriction, shortens the distance from the metal contact position to the first doped region 111, thereby reducing the sheet resistance, and the deeper p-type contact allows better current diffusion.
[0045] refer to Figure 6 As shown, the hard mask layer 120 and the spacer 121 are removed.
[0046] refer to Figure 7 As shown, a gate oxide layer 130 and a gate layer 140 are formed on the surface of the epitaxial layer 110 to expose a portion of the third doping region 113 .
[0047] In some embodiments of the present application, the material of the gate oxide layer 130 includes silicon oxide. The material of the gate layer 140 includes doped polysilicon. In some embodiments of the present application, the doping type of the gate layer 140 is the same as the doping type of the epitaxial layer 119, for example, N-type.
[0048] In some embodiments of the present application, the length of the gate oxide layer 130 is greater than the length of the gate layer 140 (lateral dimension in the drawings), so that a stepped structure can be formed at the boundary between the gate oxide layer 130 and the gate layer 140 near the third doping region 113 .
[0049] In some embodiments of the present application, the method for forming the gate oxide layer 130 and the gate layer 140 includes: depositing a gate oxide material layer and a gate material layer on the surface of the epitaxial layer 110; etching the gate material layer to form the gate layer 140; and etching the gate oxide material layer to form the gate oxide layer 130.
[0050] refer to Figure 8 As shown, the exposed third doping region 113 is etched to form a first opening 151 .
[0051] In some embodiments of the present application, the depth of the first opening 151 is 0.1 to 0.2 micrometers.
[0052] In some embodiments of the present application, the surface area of the gate layer 140 exposed is greater than the surface area of the third doping region 113 exposed at the bottom of the first opening 151 .
[0053] In some embodiments of the present application, an insulating layer (not shown) is formed on the surface of the gate layer 140 to insulate and isolate the subsequently formed first metal layer from the gate layer 140. The insulating layer includes insulating dielectric materials such as silicon oxide, BPSG or silicon nitride.
[0054] refer to Fig. 9 and Fig.10 As shown, a first metal silicide 150 is formed in the first opening 151 and a first metal layer 150 a is formed on the surface of the gate layer 140 .
[0055] refer to Fig. 9 As shown, a first metal layer 150 a is formed on the surface of the third doping region 113 and the surface of the gate layer 140 .
[0056] refer to Fig.10 As shown, a first annealing process is performed to react the metal material in the first metal layer 150a with the silicon material in the third doping region 113 to generate a first metal silicide 150. Part of the third doping region 113 is consumed. Since the first metal layer 150a and the gate layer 140 are isolated by an insulating layer, the first metal layer 150a on the gate layer 140 is not converted into a metal silicide.
[0057] In some embodiments of the present application, a depth H5 of the first metal silicide 150 in the first opening is 0.1 to 1 micrometer.
[0058] In some embodiments of the present application, a top surface of the first metal silicide 150 in the first opening is higher than a bottom surface of the gate oxide layer 130 and lower than a top surface of the gate oxide layer 130 .
[0059] In some embodiments of the present application, different metal silicide processes are used for P-type or N-type contacts. For example, for the first metal silicide 150 that mainly contacts the N-type third doping region 113, the material of the first metal layer 150a includes nickel. The temperature of the first annealing process is greater than 1100 degrees Celsius.
[0060] In the technical solution of the present application, the first metal silicide 150 has a deeper depth and a larger contact area, which can reduce the on-resistance.
[0061] refer to Fig.11 As shown, an interlayer dielectric layer 160 is formed on the surface of the first metal silicide 150 and the first metal layer 150a. The interlayer dielectric layer 160 in the technical solution of the present application can be thicker or the cell spacing can be narrowed, so the probability of hot and cold cycle cracks in the cell is reduced.
[0062] In some embodiments of the present application, the material of the interlayer dielectric layer 160 includes silicon oxide.
[0063] refer to Fig.12 As shown, Fig.12 for Figure 1 A schematic longitudinal cross-sectional view at the middle dashed line BB is shown. Part of the interlayer dielectric layer 160 and the first metal silicide 150 in the second region 102 is etched to form a second opening 152 exposing the third doped region 113 .
[0064] refer to Fig.13 and Fig.14 As shown, a second metal silicide 170 is formed in the second opening 152 , and the second metal silicide 170 is connected to the second doping region 112 below the third doping region 113 .
[0065] refer to Fig.13 As shown, a second metal layer 171 is formed on the surface of the third doping region 113 and the surface of the interlayer dielectric layer 160 .
[0066] refer to Fig.14As shown, a second annealing process is performed to react the metal material in the portion of the second metal layer 171 in contact with the third doping region 113 with the silicon material in the third doping region 113 to generate a second metal silicide 170. The portion of the second metal layer 171 not in contact with the third doping region 113 is still retained. The top surface of the second metal silicide 170 is higher than the bottom surface of the first metal silicide 150 in the first opening and lower than the top surface of the first metal silicide 150 in the first opening.
[0067] In some embodiments of the present application, different metal silicide processes are used for P-type or N-type contacts. For example, for the second metal silicide that mainly contacts the P-type second doping region 112, the material of the second metal layer 171 includes titanium or titanium nitride. The temperature of the second annealing process is 700 to 800 degrees Celsius.
[0068] Fig.15 Schematic diagram of the semiconductor structure described in some other embodiments of the present application.
[0069] refer to Fig.15 As shown, the semiconductor structures described in other embodiments of the present application are Fig.14 The difference is that the depth of the second doping region is greater than the depth of the first doping region 111, and the second doping region is divided into left and right parts. The depth of the first part 112a of the second doping region is greater than the depth of the second part 112b, and the depth of the first doping region 111 is greater than the depth of the first doping region 111.
[0070] In some other embodiments of the present application, the material of the first metal layer 150a and the second metal layer 171 may be the same, for example, NI, TI, TIN, MO, etc.
[0071] The present application provides a method for forming a semiconductor structure, which can form a first metal silicide by self-alignment, thereby improving the alignment accuracy of the first metal silicide; after etching a portion of the third doped region, the first metal silicide and the second metal silicide are formed, the contact area between the first metal silicide and the second metal silicide is increased, and the electrical connectivity between the first metal silicide and the second metal silicide is improved; a second doped region transition is formed between the first doped region and between the third doped region, thereby improving the electric field distribution and improving the device performance and reliability.
[0072] The embodiment of the present application also provides a semiconductor structure, referring to Fig.14As shown, it includes: a semiconductor substrate 100, an epitaxial layer 110 is formed on the surface of the semiconductor substrate 100, a first doping region 111, a second doping region 112 located in the first doping region 111 and a third doping region 113 located in the second doping region 112 are formed in the epitaxial layer 110, a gate oxide layer 130 and a gate layer 140 are formed on the surface of the epitaxial layer 110 to expose a portion of the third doping region 113; a first opening 151 is located in the exposed third doping region 113; a first metal silicide 150 is located in the first opening 151; and an interlayer dielectric layer 160 is located on the surface of the first metal silicide 150.
[0073] refer to Figure 1 As shown, in some embodiments of the present application, the semiconductor substrate 100 includes a first region 101 and a second region 102. The first region 101 and the second region 102 are respectively used to form different metal silicides.
[0074] In some embodiments of the present application, the semiconductor structure described in the embodiments of the present application is, for example, a silicon carbide MOSFET.
[0075] In some embodiments of the present application, the material of the semiconductor substrate 100 includes silicon carbide, and the material of the epitaxial layer 110 includes doped silicon carbide. The doping type of the epitaxial layer 110 is, for example, N-type. The depth H1 of the epitaxial layer 110 is 4 to 40 microns. The doping concentration of the epitaxial layer 110 is 2E15 atom / cm 3 To 3E16 atom / cm 3 .
[0076] In some embodiments of the present application, the first doping region 111 is PBase. The doping type of the first doping region 111 is opposite to the doping type of the epitaxial layer 110, for example, P type. The depth H2 of the first doping region 111 can be adjusted according to the required gate voltage, for example, 0.6 microns to 2 microns. The doping concentration of the first doping region 111 is, for example, 5E17atom / cm 3 To 3E19atom / cm 3 The first doping region 111 is used to control the threshold voltage and form a depletion region to isolate the N-type of the second doping region 112 and share part of the electric field.
[0077] In some embodiments of the present application, the doping type of the second doping region 112 is the same as the doping type of the first doping region 111, for example, P-type. The depth H3 of the second doping region 112 can be deeper or shallower than the first doping region 111, generally 0.8 microns to 2.4 microns. The doping concentration of the second doping region 112 is, for example, 1E19atom / cm3 To 1E21atom / cm 3 The function of the second doping region 112 is to make the P type form a better ohmic contact with the metal, and at the same time reduce the P type film resistance, reduce the voltage value of the parasitic diode, and reduce the conduction loss of the device.
[0078] In some embodiments of the present application, the doping type of the third doping region 113 is opposite to the doping type of the second doping region 112, for example, N-type. The depth H3 of the third doping region 113 is 0.2 to 0.4 microns. The doping concentration of the third doping region 113 is, for example, 1E19atom / cm 3 To 1E21atom / cm 3 The function of the third doping region 113 is to make the P-type and the metal form a better ohmic contact, reduce the RDSON value when the MOSFET is switched, and reduce the conduction loss of the device.
[0079] In the technical solution of the present application, the second doped region 112 makes the p-type junction shallower, reduces the width restriction, shortens the distance from the metal contact position to the first doped region 111, thereby reducing the sheet resistance, and the deeper p-type contact allows better current diffusion.
[0080] In some embodiments of the present application, the material of the gate oxide layer 130 includes silicon oxide. The material of the gate layer 140 includes doped polysilicon. In some embodiments of the present application, the doping type of the gate layer 140 is the same as the doping type of the epitaxial layer 119, for example, N-type.
[0081] In some embodiments of the present application, the length of the gate oxide layer 130 is greater than the length of the gate layer 140 (lateral dimension in the drawings), so that a stepped structure can be formed at the boundary between the gate oxide layer 130 and the gate layer 140 near the third doping region 113 .
[0082] In some embodiments of the present application, the depth of the first opening 151 is 0.1 to 0.2 micrometers.
[0083] In some embodiments of the present application, the surface area of the gate layer 140 exposed is greater than the surface area of the third doping region 113 exposed at the bottom of the first opening 151 .
[0084] In some embodiments of the present application, an insulating layer (not shown in the figure) and a first metal layer 150a are sequentially formed on the surface of the gate layer 140 .
[0085] In some embodiments of the present application, a depth H5 of the first metal silicide 150 in the first opening is 0.1 to 1 micrometer.
[0086] In some embodiments of the present application, a top surface of the first metal silicide 150 in the first opening is higher than a bottom surface of the gate oxide layer 130 and lower than a top surface of the gate oxide layer 130 .
[0087] In some embodiments of the present application, different metal silicides are used for P-type or N-type contacts. For example, for the first metal silicide 150 that mainly contacts the N-type third doping region 113, its metal portion is nickel.
[0088] In the technical solution of the present application, the first metal silicide 150 has a deeper depth and a larger contact area, which can reduce the on-resistance.
[0089] The interlayer dielectric layer 160 in the technical solution of the present application can be thicker or the unit spacing can be narrower, so the probability of hot and cold cycle cracks in the unit is reduced.
[0090] In some embodiments of the present application, the material of the interlayer dielectric layer 160 includes silicon oxide.
[0091] Continue to refer Fig.14 As shown, in some embodiments of the present application, a second opening exposing the third doped region 113 is further formed in the interlayer dielectric layer 160 and the first metal silicide 150 of the second region 102; a second metal silicide 170 is formed in the second opening, and the second metal silicide 170 is connected to the second doped region 112 below the third doped region 113. A second metal layer 171 is formed on the surface of the portion of the interlayer dielectric layer 160 that is not in contact with the third doped region 113. The top surface of the second metal silicide 170 is higher than the bottom surface of the first metal silicide 150 in the first opening and lower than the top surface of the first metal silicide 150 in the first opening.
[0092] In some embodiments of the present application, different metal silicide processes are used for P-type or N-type contacts. For example, the metal material of the second metal silicide 170 that mainly contacts the P-type second doping region 112 includes titanium.
[0093] refer to Fig.15 As shown, the semiconductor structures described in other embodiments of the present application are Fig.14 The difference is that the depth of the second doping region is greater than the depth of the first doping region 111, and the second doping region is divided into left and right parts. The depth of the first part 112a of the second doping region is greater than the depth of the second part 112b, and the depth of the first doping region 111 is greater than the depth of the first doping region 111.
[0094] In some other embodiments of the present application, the material of the first metal layer 150a and the second metal layer 171 may be the same, for example, NI, TI, TIN, MO, etc.
[0095] The present application provides a semiconductor structure and a method for forming the same, which can form a first metal silicide by self-alignment, thereby improving the alignment accuracy of the first metal silicide; after etching a portion of the third doped region, the first metal silicide and the second metal silicide are formed, thereby increasing the contact area between the first metal silicide and the second metal silicide, and improving the electrical connectivity between the first metal silicide and the second metal silicide; and forming a second doped region transition between the first doped region and between the third doped region, thereby improving the electric field distribution and improving the device performance and reliability.
[0096] In summary, after reading the contents of this application, those skilled in the art will appreciate that the aforementioned application contents may be presented only in an exemplary manner and may not be restrictive. Although not explicitly stated herein, those skilled in the art will appreciate that this application is intended to encompass various reasonable changes, improvements and modifications to the embodiments. These changes, improvements and modifications are within the spirit and scope of the exemplary embodiments of this application.
[0097] It should be understood that the term "and / or" used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to another element, or there can also be intermediate elements.
[0098] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element or there can be intervening elements. In contrast, the term "directly" means that there are no intervening elements. It should also be understood that the terms "comprising," "containing," "including," or "comprising," when used in this application document, indicate the presence of the recited features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof.
[0099] It should also be understood that although the terms first, second, third, etc. can be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present application, the first element in some embodiments can be referred to as the second element in other embodiments. The same reference numerals or the same reference signs represent the same elements throughout the specification.
[0100] In addition, the present specification describes exemplary embodiments by reference to idealized exemplary cross-sectional views and / or plan views and / or stereograms. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are foreseeable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but should include deviations in shapes caused by, for example, manufacturing. For example, an etched region shown as a rectangle will typically have circular or curved features. Therefore, the region shown in the figure is schematic in nature, and its shape is not intended to illustrate the actual shape of the region of the device nor to limit the scope of the exemplary embodiments.
Claims
1. A semiconductor structure, characterized in that: include: A semiconductor substrate, wherein an epitaxial layer is formed on a surface of the semiconductor substrate, wherein a first doping region, a second doping region located in the first doping region, and a third doping region located in the second doping region are formed in the epitaxial layer, and a gate oxide layer and a gate layer exposing a portion of the third doping region are formed on the surface of the epitaxial layer; A first opening located in the exposed third doped region; A first metal silicide is located in the first opening; The interlayer dielectric layer is located on the surface of the first metal silicide.
2. The semiconductor structure according to claim 1, wherein: The material of the semiconductor substrate includes silicon carbide, the material of the epitaxial layer includes doped silicon carbide, and the material of the gate layer includes doped polysilicon.
3. The semiconductor structure according to claim 1, wherein: The doping type of the first doping region is opposite to the doping type of the epitaxial layer, the doping type of the second doping region is the same as the doping type of the first doping region, the doping type of the third doping region is opposite to the doping type of the second doping region, and the doping type of the gate layer is the same as the doping type of the epitaxial layer.
4. The semiconductor structure according to claim 1, wherein: The depth of the epitaxial layer is 4 to 40 micrometers, the depth of the first doping region is 0.6 to 2 micrometers, the depth of the second doping region is 0.8 to 2.4 micrometers, and the depth of the third doping region is 0.2 to 0.4 micrometers.
5. The semiconductor structure according to claim 1, wherein: The length of the gate oxide layer is greater than the length of the gate layer.
6. The semiconductor structure according to claim 1, wherein: The surface area of the gate layer is greater than the surface area of the third doping region at the bottom of the first opening.
7. The semiconductor structure according to claim 1, wherein: The depth of the first opening is 0.1 to 0.2 micrometers.
8. The semiconductor structure according to claim 1, wherein: The depth of the first metal silicide in the first opening is 0.1 to 1 micrometer.
9. The semiconductor structure according to claim 1, wherein: The top surface of the first metal silicide in the first opening is higher than the bottom surface of the gate oxide layer and lower than the top surface of the gate oxide layer.
10. The semiconductor structure according to claim 1, wherein: The semiconductor substrate includes a first region and a second region, and a second opening exposing the third doped region is formed in the interlayer dielectric layer and the first metal silicide in the second region; a second metal silicide is formed in the second opening, and the second metal silicide is connected to the second doped region below the third doped region.