Integrated circuit device

Abstract

An integrated circuit device is provided. The utility model discloses an integrated circuit device. The problem is solved by introducing a buried layer of a second dielectric composition into a gate dielectric of a first dielectric composition to provide a transistor that can be manufactured to have any specified threshold voltage within a wide threshold voltage range without causing leakage problems, capacitance problems, or process compatibility problems. The second dielectric composition is selected relative to the first dielectric composition such that a dipole is formed around the interface of the two dielectric substances. The dipole generates an electric field, and the electric field enables the threshold voltage to shift. The buried layer has a dielectric constant higher than that of the gate dielectric, is thinner than that of the gate dielectric, and is close to the channel.

Description

Technical Field

[0001] The utility model relates to an integrated circuit device. Background Art

[0002] Over the past few decades, the integrated circuit (IC) manufacturing industry has experienced exponential growth. As integrated circuits have evolved, functional density (i.e., the number of interconnected devices per unit chip area) has generally increased, while geometry (i.e., the smallest component that can be produced) has generally decreased. Another development is BCD technology, which is a combination of bipolar junction transistor (BJT) technology, complementary metal-oxide-semiconductor (CMOS) technology, and double-diffused metal-oxide-semiconductor (DMOS) technology. BCD technology allows logic devices, analog devices, and power devices to be formed on a single semiconductor chip. BCD technology poses challenges in terms of the need for process compatibility and the need to limit the surge in process steps. Utility Model Content

[0003] In some embodiments of the present invention, there is an integrated circuit device. The integrated circuit device includes a transistor and a second dielectric layer. The transistor has a gate electrode, a gate dielectric and a semiconductor channel, wherein the gate dielectric is located between the gate electrode and the semiconductor channel. The second dielectric layer is embedded in the gate dielectric, wherein the second dielectric layer has a higher dielectric constant than the gate dielectric.

[0004] In some embodiments of the utility model, there is an integrated circuit device. The integrated circuit device includes a transistor. The transistor has a gate electrode, a gate dielectric structure and a semiconductor channel. The gate dielectric structure includes a first dielectric layer and a second dielectric layer. The first dielectric layer is at least half the thickness of the gate dielectric structure and is located between the second dielectric layer and the gate electrode. The second dielectric layer has a higher dielectric constant than the first dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0006] Figure 1 to Figure 2 A cross-sectional side view of a bottom gate transistor according to some embodiments of the present disclosure is shown.

[0007] Figure 3 supply Figure 2 An enlarged view of a portion shown.

[0008] Figures 4 to 6 A cross-sectional side view of a bottom gate transistor is shown according to some other embodiments.

[0009] Figures 7 and 8 A cross-sectional side view of a top gate transistor according to some embodiments of the present disclosure is shown.

[0010] Fig. 9 supply Figure 8 An enlarged view of a portion is shown.

[0011] Figures 10 to 12 A cross-sectional side view of a bottom gate transistor is shown according to some other embodiments.

[0012] Figure 13 to Figure 14 A cross-sectional side view of an integrated circuit (IC) device according to some embodiments of the present disclosure is shown.

[0013] Figures 15 to 30 It is an example of forming according to the present disclosure, for example Fig.13 A series of cross-sectional views of the method of the device and the like shown.

[0014] Figures 31 to 41 It is an example of forming according to the present disclosure, for example Fig.14 A series of cross-sectional views of the method of the device and the like shown.

[0015] Figure 42 to Figure 43 Flowcharts are provided that illustrate some methods according to the present disclosure of forming IC devices according to the present disclosure.

[0016] [Explanation of Reference Numerals]

[0017] 100, 200, 400, 500, 600: transistors

[0018] 101, 701: Source region

[0019] 103, 715, 1311: interlayer dielectric (ILD) layer

[0020] 105, 703: drain region

[0021] 107, 107A, 107B, 107C, 1607, 1807, 2007: Channel layer

[0022] 109, 109B: buried layer

[0023] 109C, 1606, 1806, 3106, 3306: first buried layer

[0024] 110: Thin layer

[0025] 110C: First thin layer

[0026] 111, 111A, 111B, 111C: Gate dielectric

[0027] 113, 113A, 113B, 113C: bottom gate electrode

[0028] 115A, 115B, 115C, 115D, 115E, 115F: Gate dielectric structure

[0029] 117A: First interface

[0030] 117B: Second interface

[0031] 209, 209C, 1604, 3104: second buried layer

[0032] 210, 210C: Second thin layer

[0033] 217A: Third Interface

[0034] 217B: The fourth interface

[0035] 300, 900: Area

[0036] 517: Interface

[0037] 700, 800, 1000, 1100, 1200, 1404A, 1404B, 1404C: top gate transistors 705, 1307: sidewall spacers

[0038] 707: Semiconductor substrate

[0039] 707A, 707B, 707C, 1302A, 1302B, 1302C: substrate area

[0040] 713: Gate electrode

[0041] 1300, 1400: Integrated Circuit (IC) Devices

[0042] 1301: Substrate

[0043] 1303: Interlayer dielectric

[0044] 1304A, 1304B, 1304C: bottom gate transistors

[0045] 1305, 1305B, 1305C, 1314: Metal wire

[0046] 1309:Through hole

[0047] 1500、1600、1700、1800、1900、2000、2100、2200、2300、2400、2500、2600、2700、2800、2900、3000、3100、3200、3300、3400、3500、3600、3700、3800、3900、4000、4100: Sectional view

[0048] 1601, 1801, 2001, 3101, 3301, 3501: Gate stack

[0049] 1603, 1803, 2003, 3103, 3303, 3503: electrode layer

[0050] 1605, 1805, 2005, 3105, 3305, 3505: Gate dielectric layer

[0051] 1608, 3108: second thin gate dielectric layer

[0052] 1609, 1809, 2009, 3109, 3309, 3509: Hard mask layer

[0053] 1610, 1810, 3110, 3310: first thin gate dielectric layer

[0054] 1701, 1901, 2101, 2209, 2301, 2901, 3201, 3401, 3701: Mask

[0055] 2501: Anti-reflective coating (ARC)

[0056] 2903: Opening

[0057] 4200, 4300: Technology

[0058] 4201, 4203, 4205, 4207, 4209, 4211, 4213, 4215, 4217, 4219, 4221, 4223, 4225, 4227, 4229, 4231, 4233, 4235, 4237, 4239, 4241, 4301, 4303, 4305, 4307, 4309, 4311, 4313, 4315, 4317, 4319, 4321, 4323, 4325, 4327, 4329, 4331, 4333, 4335, 4337: Action

[0059] D 1 , D 2 :distance

[0060] M X 、MX+1 :Metalization layer

[0061] T 1 :thickness DETAILED DESCRIPTION

[0062] The present disclosure provides many different embodiments or examples to implement the different features of the present disclosure. The following describes specific examples of components and arrangements to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, the following description of forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than indicating the relationship between the various embodiments and / or configurations discussed.

[0063] Additionally, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and the like may be used herein to describe the relationship of one component or feature to another (other) component or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0064] The problem of providing a transistor that can be fabricated to have any given threshold voltage within a wide range of threshold voltages without leakage problems, capacitance problems, or process compatibility problems is solved by introducing a buried layer of a second dielectric composition into the gate dielectric of a first dielectric composition. The second dielectric composition is selected relative to the first dielectric composition so that a dipole is formed around the interface between the two dielectric compositions. The dipole generates an electric field that shifts the threshold voltage. Depending on the orientation of the dipole and whether the semiconductor channel is p-type or n-type, the threshold voltage shift can be positive or negative.

[0065] The influence of the dipoles increases as they are closer to the semiconductor channel. In some embodiments, the buried layer is closer to the semiconductor channel than the buried layer is to the gate electrode. In some embodiments, half or more of the gate dielectric structure is between the buried layer and the gate electrode. In some embodiments, the distance between the buried layer and the gate electrode is greater than the thickness of the buried layer.

[0066] In some embodiments, the buried layer has a higher dielectric constant than the gate dielectric. In some embodiments, the gate dielectric is silicon dioxide or a similar material. In some embodiments, the buried layer is a high-κ dielectric. Materials with higher dielectric constants are more suitable for the buried layer. The thickness of the buried layer is limited because the effect of the buried layer on the gate capacitance is also limited.

[0067] In some embodiments, both the gate dielectric and the buried layer are oxides, and the buried layer has an electronegativity different from that of the gate dielectric. The large difference in electronegativity between the dielectric compositions facilitates the formation of dipoles. In some embodiments, the difference in electronegativity is at least equal to that of silicon dioxide (SiO 2 ) and hafnium oxide (HfO 2 In some embodiments, the electronegativity difference is greater than that of silicon dioxide (SiO 2 ) and hafnium oxide (HfO 2 ) have a negative charge difference.

[0068] In some embodiments, both the gate dielectric and the buried layer are oxides, and the buried layer has an oxygen areal density that is different from the oxygen areal density of the gate dielectric. The large difference in oxygen areal density between the dielectric compositions is favorable for forming dipoles. In some embodiments, the oxygen areal density difference is at least as great as that of silicon dioxide (SiO 2 ) and hafnium oxide (HfO 2 ). In some embodiments, the oxygen surface density difference is greater than that of silicon dioxide (SiO 2 ) and hafnium oxide (HfO 2 ) is the oxygen surface density difference between .

[0069] In some embodiments, the buried layer comprises a mixture of two or more dielectrics. Mixing two or more dielectrics allows for fine tuning of the threshold voltage. In some embodiments, the buried layer comprises a mixture of two dielectrics, both of which have a higher oxygen surface density than the gate dielectric. For example, if the gate dielectric is silicon dioxide (SiO 2 ), the buried layer can be gallium oxide (Ga 2 O 3 ), indium oxide (In 2 O 3 )、ZnO、Al2O3 2 O 3 ), titanium oxide (TiO 2 ), hafnium oxide (HfO 2) or a mixture of two or more of the like. In some embodiments, the buried layer comprises a mixture of two dielectrics, both of which have a lower oxygen surface density than the gate dielectric. For example, if the gate dielectric is silicon dioxide (SiO 2 ), the buried layer can be yttrium oxide (Y 2 O 3 ), strontium oxide (SrO), lanthanum oxide (La 2 O 3 ) or a mixture of two or more of the like materials. The threshold voltage is increased or decreased depending on whether the oxygen surface density of the buried layer is higher or lower than that of the gate dielectric. Making both oxygen surface densities of the dielectric in the buried layer higher than that of the gate dielectric or making both oxygen surface densities of the dielectric lower than that of the gate dielectric ensures that the two dielectrics operate in synergy.

[0070] In some embodiments, a second buried layer is buried in the gate dielectric. In some embodiments, the second buried layer is adjacent to the first buried layer. In some embodiments, the second buried layer is separated from the first buried layer by a thin layer of gate dielectric. Two buried layers provide a larger threshold voltage shift than one buried layer. In addition, the inventors have discovered that two buried layers of different compositions can provide a threshold voltage shift that is larger than the threshold voltage shift that can be achieved using a single buried layer composition.

[0071] In some embodiments, the transistor is a top gate device. A top gate device may have a channel provided by a crystalline substrate (e.g., a silicon crystalline substrate). In the fabrication process disclosed herein, a thin layer of gate dielectric is first deposited, followed by a buried layer, followed by the remainder of the gate dielectric, the gate electrode, the formation of spacers, and the doping of the source / drain regions. The thin layer of gate dielectric prevents undesirable interactions between the buried layer and the substrate. Using a buried layer to control the threshold voltage prevents undesirable changes in transistor height and increases compatibility with other device structures formed on the same semiconductor substrate.

[0072] In some embodiments, the transistor is a bottom gate device. The bottom gate device may have a channel provided by a deposited layer such as amorphous silicon, polycrystalline silicon, or a metal oxide semiconductor. In the manufacturing process disclosed herein, a gate dielectric is first deposited, followed by a buried layer and a channel layer. The gate stack is patterned, followed by the formation of spacers, the deposition of an interlayer dielectric layer, and the formation of source and drain regions within the interlayer dielectric. A thin layer of the gate dielectric layer may be deposited over the buried layer to prevent interaction with the semiconductor channel. Using a buried layer to control the threshold voltage prevents undesirable changes in the transistor height and facilitates the integration of the transistor into a metal interconnect structure.

[0073] Figure 1 1 is a cross-sectional view of a transistor 100 according to some embodiments. The transistor 100 includes a gate dielectric structure 115A between a bottom gate electrode 113 and a channel layer 107. A source region 101 and a drain region 105 as conductive structures within an interlevel dielectric (ILD) layer 103 may be disposed above the channel layer 107. The gate dielectric structure 115A includes a buried layer 109 within a gate dielectric 111. A thin layer 110 of the gate dielectric 111 separates the buried layer 109 from the channel layer 107.

[0074] The buried layer 109 is embedded within the gate dielectric 111 such that a first interface 117A is formed between the buried layer 109 and the thin layer 110 and a second interface 117B is formed between the buried layer 109 and the bulk region of the gate dielectric 111. The interaction of the buried layer 109 and the gate dielectric 111 at the first interface 117A and at the second interface 117B shifts the threshold voltage of the transistor 100 to a much greater extent than can be explained by the thickness and dielectric constant of the buried layer 109. The primary mechanism for this shift may be the formation of dipoles around the first interface 117A and around the second interface 117B.

[0075] The buried layer 109 is closer to the channel layer 107 than the buried layer 109 is to the bottom gate electrode 113. The buried layer 109 is separated from the channel layer 107 by a distance D 1 (See Figure 3 ), distance D 1 is the thickness of the thin layer 110. In some embodiments, the distance D 1 is approximately equal to the thickness of the buried layer 109. In some embodiments, the distance D 1 Less than the thickness of the buried layer 109. In some embodiments, the distance D 1 In some embodiments, the distance D 1 From about 1 angstrom to about 5 angstroms.

[0076] In some embodiments, the thickness T of the gate dielectric structure 115A is 1 The thickness of the buried layer 109 is less than the thickness T 1 In some embodiments, the thickness of the buried layer 109 plus the thickness of the thin layer 110 is less than the thickness T 1 In some embodiments, the thickness of the buried layer 109 is about the thickness T 1 In some embodiments, the buried layer 109 has a thickness ranging from about 1 angstrom to about 10 angstroms.

[0077] The buried layer 109 has a higher dielectric constant than the gate dielectric 111. In some embodiments, the buried layer 109 is a high-κ dielectric. In some embodiments, the buried layer 109 is or includes an oxide. The buried layer 109 may be, for example, aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), hafnium oxide (HfO 2 )、ZnO、Yttrium Oxide (Y 2 O 3 ), lanthanum oxide (La 2 O 3 ), gallium oxide (Ga 2 O 3 ), indium oxide (In 2 O 3 ), combinations thereof or similar materials, or materials including, for example, aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), hafnium oxide (HfO 2 )、ZnO、Yttrium Oxide (Y 2 O 3 ), lanthanum oxide (La 2 O 3 ), gallium oxide (Ga 2 O 3 ), indium oxide (In 2 O 3 ), combinations thereof, or similar materials. In some embodiments, buried layer 109 has a single dielectric composition. In some embodiments, buried layer 109 is a mixture of two or more dielectrics. Mixing two or more dielectrics in buried layer 109 allows for fine tuning of the threshold voltage.

[0078] The gate dielectric 111 may have any suitable composition. In some embodiments, the gate dielectric 111 is or includes an oxide. The gate dielectric 111 may be, for example, silicon oxide (SiO 2 ), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), lanthanum oxide (La 2 O 3 ), strontium oxide (SrO), combinations thereof or similar materials, or materials including, for example, silicon oxide (SiO 2 ), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), lanthanum oxide (La2 O 3 ), strontium oxide (SrO), combinations thereof, or similar materials. In the case where the gate dielectric 111 is a mixture of two or more oxides, the oxides may be uniformly mixed or may be arranged in alternating layers. If the oxides are arranged in alternating layers, the individual layers are thinner than the buried layer 109. In some embodiments, the gate dielectric 111 is silicon oxide (SiO 2 ) or similar materials.

[0079] Figure 2 is a cross-sectional view of a transistor 200 according to some embodiments. Figure 3 supply Figure 2 1 is an enlarged view of region 300 in FIG. Transistor 200 is similar to transistor 200 except that transistor 200 has gate dielectric structure 115B. Figure 1 The transistor 100 is shown. The gate dielectric structure 115B is similar to the gate dielectric structure 115B except that the gate dielectric structure 115B has a second buried layer 209. Figure 1 The gate dielectric structure 115A is shown. The second thin layer 210 of the gate dielectric 111 separates the second buried layer 209 from the buried layer 109 .

[0080] The second buried layer 209 is embedded in the gate dielectric 111, so that a third interface 217A is formed between the second buried layer 209 and the second thin layer 210 and a fourth interface 217B is formed between the second buried layer 209 and the bulk region of the gate dielectric 111. The interaction between the second buried layer 209 and the gate dielectric 111 at the third interface 217A and at the fourth interface 217B shifts the threshold voltage of the transistor 100 to a much greater extent than can be explained with respect to the thickness and dielectric constant of the second buried layer 209.

[0081] Compared to the second buried layer 209 being closer to the bottom gate electrode 113, the second buried layer 209 is closer to the channel layer 107. The second buried layer 209 is separated from the buried layer 109 by a distance D 2 (See Figure 3 ), distance D 2 is the thickness of the second thin layer 210. In some embodiments, the distance D 2 is approximately equal to the thickness of the second buried layer 209. In some embodiments, the distance D 2 is less than the thickness of the second buried layer 209. In some embodiments, the distance D 2 In some embodiments, the distance D 2 From about 1 angstrom to about 5 angstroms.

[0082] The thickness and composition of the second buried layer 209 are the same as those of the buried layer 109. In some embodiments, the second buried layer 209 has a different composition than the buried layer 109. In some embodiments, the combined thickness of the thin layer 110, the buried layer 109, the second thin layer 210, and the second buried layer 209 is less than the thickness T of the gate dielectric structure 115B. 1 half.

[0083] The channel layer 107 is a semiconductor and may have any suitable composition. Examples of possible suitable compositions include amorphous silicon, polycrystalline silicon, metal oxide semiconductors, or similar materials. Examples of metal oxide semiconductors that may be used include, but are not limited to, indium zinc oxide (IZO), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), indium tungsten oxide (IWO), indium tungsten zinc oxide (IWZO), indium gallium zinc tin oxide (IGZTO), zinc oxide (ZnO), indium tin oxide (InSnO or ITO), combinations thereof, or similar materials.

[0084] In some embodiments, channel layer 107 is a metal oxide semiconductor. Thin layer 110 can be used to prevent undesired interactions between channel layer 107, which is silicon, and buried layer 109, which is a high-κ dielectric. Selecting a suitable metal oxide semiconductor for channel layer 107 is an alternative way to prevent such undesired interactions.

[0085] Figure 4 1 is a cross-sectional view of a transistor 400 according to another embodiment. The transistor 400 is similar to the transistor 200 except that the transistor 200 has a gate dielectric structure 115C. Figure 1 The transistor 100 is shown. In addition to the absence of the thin layer 110 in the gate dielectric structure 115C (see Figure 1 ) and the buried layer 109 is adjacent to the channel layer 107, the gate dielectric structure 115C is similar to Figure 1 The gate dielectric structure 115A is shown. The gate dielectric structure 115C has a second interface 117B but does not have a first interface 117A (see Figure 1 ).

[0086] Figure 5 1 is a cross-sectional view of a transistor 500 according to another embodiment. The transistor 500 is similar to the transistor 500 except that the transistor 500 has a gate dielectric structure 115D. Figure 2 The gate dielectric structure 115D is similar to the gate dielectric structure 115D except that the second thin layer 210 is not present in the gate dielectric structure 115D and the buried layer 109 is adjacent to the second buried layer 209 to form an interface 517. Figure 2 The gate dielectric structure 115B is shown. In the transistor 500, the buried layer 109 and the second buried layer 209 have different compositions and there are three interfaces that can form dipoles: the first interface 117A, the interface 517 and the fourth interface 217B.

[0087] Figure 6 1 is a cross-sectional view of a transistor 600 according to another embodiment. The transistor 600 is similar to the transistor 500 except that the transistor 500 has a gate dielectric structure 115E. Figure 5 The gate dielectric structure 115E is similar to the transistor 500 shown in FIG. 1 except that the thin layer 110 separating the buried layer 109 from the channel layer 107 is not present in the gate dielectric structure 115E. Figure 5 The gate dielectric structure 115D is shown. In transistor 600, the buried layer 109 may be similar to Figure 1 The thin layer 110 in the gate dielectric structure 115A is shown to function as such. Figure 1 to Figure 2 and Figures 4 to 6 Each of the illustrated gate dielectric structures 115A- 115E may provide unique advantages in varying the threshold voltage while maintaining the capacitance within a desired range.

[0088] Figures 7 to 12 is corresponding to Figures 1 to 6 A cross-sectional view of a bottom gate transistor and a top gate transistor using the same gate dielectric structure is shown. Figure 7 A top gate transistor 700 using a gate dielectric structure 115A is shown. For the top gate transistor 700, the gate dielectric structure 115A is inverted so that the buried layer 109 is close to the semiconductor substrate 707 providing the channel. The gate electrode 713 is located above the gate dielectric structure 115A. The source region 701 and the drain region 703 are provided by regions of the semiconductor substrate 707 having opposite doping types and are aligned with the sidewall spacers 705.

[0089] The semiconductor substrate 707 may be of any suitable type. The semiconductor substrate 707 may be, for example, a bulk substrate (e.g., a bulk silicon substrate) or a silicon-on-insulator (SOI) substrate. The semiconductor may be silicon (Si), a III-V group or some other binary semiconductor, a ternary semiconductor (e.g., AlGaAs), a higher order semiconductor, or the like. The semiconductor may be a single crystal structure or an epitaxially grown structure.

[0090] Figure 8 Show use Figure 2 A top gate transistor 800 is shown with a gate dielectric structure 115B. Fig. 9 Show Figure 8 The area shown is 900. Fig. 9 As shown in FIG. , the size of the gate dielectric structure 115B is Figure 3 The only difference is that for the top gate transistor 800, the gate dielectric structure 115B is inverted.

[0091] Fig.10 Show use Figure 4 The top gate transistor 1000 of the gate dielectric structure 115C is shown. As shown in this example, the thin layer 110 (see Figure 7 ) is optional, but makes the material selection of the removable thin layer 110 more likely to be suitable for bottom gate transistors. Fig.11 Show use Figure 5 The top gate transistor 1100 is shown with a gate dielectric structure 115D, and Fig.12 Show use Figure 6 A top gate transistor 1200 is shown with a gate dielectric structure 115E.

[0092] Fig.13 A cross-sectional view of an integrated circuit (IC) device 1300 is provided that includes a bottom gate transistor 1304A, a bottom gate transistor 1304B, and a bottom gate transistor 1304C. The bottom gate transistors 1304A-1304C are formed on substrate regions 1302A-1302C, respectively. The substrate regions 1302A-1302C may be regions of three different substrates or may be different regions on a single substrate 1301. The substrate 1301 may include a semiconductor substrate and may include one or more metal interconnect layers formed on the semiconductor substrate. The bottom gate transistors 1304A-1304C are shown as all formed on the metallization layer M of the metal interconnect structure. X With metallization layer M X+1 between.

[0093] The bottom gate transistors 1304A to 1304C have gate dielectric structures 115F, Figure 1 The gate dielectric structure 115A and Figure 21 and 13. The gate dielectric structure 115B is shown. The gate dielectric structure 115F is similar to the gate dielectric structures 115A and 115B, but does not include any buried layers. The gate dielectric structures 115F, 115A, and 115B may all have approximately the same height. The bottom gate transistors 1304A to 1304C may all have approximately the same capacitance and approximately the same footprint with very different threshold voltages. In some embodiments, the threshold voltage is in a range from about 0.1 volt to about 20 volts. In some embodiments, the threshold voltage is in a range from about 1 volt to about 5 volts. As shown in IC device 1300, the buried layers of the present disclosure provide design flexibility and modularity by allowing the threshold voltage to be varied without simultaneously varying the transistor width, thickness, or capacitance.

[0094] In some embodiments, the threshold voltage of one of the bottom gate transistors 1304A-1304C is about 25% or more greater than the threshold voltage of another of the bottom gate transistors 1304A-1304C. In some embodiments, the threshold voltage of one of the bottom gate transistors 1304A-1304C is about 50% or more greater than the threshold voltage of another of the bottom gate transistors 1304A-1304C. In some embodiments, the threshold voltage of one of the bottom gate transistors 1304A-1304C is two times or more than the threshold voltage of another of the bottom gate transistors 1304A-1304C.

[0095] Fig.14 A cross-sectional view of an integrated circuit (IC) device 1400 including a top gate transistor 1404A, a top gate transistor 1404B, and a top gate transistor 1404C is provided. Top gate transistors 1404A to 1404C are formed on substrate regions 707A to 707C, respectively. Substrate regions 707A to 707C may be regions of three different substrates or may be different regions on a single semiconductor substrate 707. In the case where the substrates are different, IC device 1400 may represent three different devices produced in one foundry under a set of process constraints. In some embodiments, semiconductor substrate 707 is a P-type substrate. In some embodiments, semiconductor substrate 707 is an N-type substrate.

[0096] The top gate transistors 1404A to 1404C have gate dielectric structures 115F, Figure 7 The gate dielectric structure 115A and Figure 81400. The gate dielectric structure 115B is shown. The gate dielectric structure 115F is similar to the gate dielectric structures 115A and 115B, but does not include any buried layers. The top gate transistors 1404A to 1404C may all have approximately the same capacitance and approximately the same footprint, but with very different threshold voltages. In some embodiments, the voltage is in the range from about 0.1 volt to about 20 volts. In some embodiments, the voltage is in the range from about 1 volt to about 5 volts. As shown in the IC device 1400, the buried layers disclosed herein create design flexibility and modularity for top gate transistors and bottom gate transistors. The direction of the change in threshold voltage caused by the insertion of one or both of the buried layer 109 and the second buried layer 209 will vary depending on the doping type of the semiconductor substrate 707.

[0097] In some embodiments, the threshold voltage of one of the top gate transistors 1404A-1404C is about 25% or more greater than the threshold voltage of another of the top gate transistors 1404A-1404C. In some embodiments, the threshold voltage of one of the top gate transistors 1404A-1404C is about 50% or more greater than the threshold voltage of another of the top gate transistors 1404A-1404C. In some embodiments, the threshold voltage of one of the top gate transistors 1404A-1404C is two times or more than the threshold voltage of another of the top gate transistors 1404A-1404C.

[0098] Figures 15 to 30 is a cross-sectional view illustrating a method of forming an IC device having a transistor according to the present disclosure. Although various embodiments of the method are described with reference to Figures 15 to 30 , but it should be understood that Figures 15 to 30 The structure shown in is not limited to the method, but can exist independently of the method. Figures 15 to 30 The sequence of actions may be described as a series of actions. In other embodiments, the sequence of the actions may be changed. Figures 15 to 30 A particular set of actions is shown and described, but some actions may be omitted in other embodiments. In addition, actions not shown and / or described may be included in other embodiments. Fig.13 The IC device 1300 or similar device is described in detail. Figures 15 to 30 The method is shown, but the method and its variations can be used to form other IC devices.

[0099] like Fig.15 As shown in the cross-sectional view 1500 of FIG. 1501 , the method may first form a metallization layer M on the substrate 1301. X X is a number greater than or equal to 1 and the substrate 1301 is on the metallization layer M X There are X-1 metallization layers below. Metallization layer M XThe metal lines 1305, 1305B and 1305C are respectively located on the substrate regions 1302A to 1302C. The metal lines 1305, 1305B and 1305C are surrounded by the interlayer dielectric 1303 and are used to contact the bottom electrode. Alternatively, bottom electrode vias can be formed and used to make the contacts.

[0100] like Fig.16 As shown in the cross-sectional view 1600 of FIG. 1 , a gate stack 1601 may be formed on the substrate regions 1302A, 1302B, and 1302C. The gate stack 1601 includes Figure 2 16. The layers of transistor 200 are shown. Gate stack 1601 includes electrode layer 1603, gate dielectric layer 1605, second buried layer 1604, second thin gate dielectric layer 1608, first buried layer 1606, first thin gate dielectric layer 1610, channel layer 1607, and hard mask layer 1609. The deposition process may be atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), the like, or a combination thereof. In some embodiments, second buried layer 1604, second thin gate dielectric layer 1608, first buried layer 1606, and first thin gate dielectric layer 1610 are formed by ALD. ALD precisely controls the thickness of these layers.

[0101] like Fig.17 As shown in the cross-sectional view 1700 of FIG. 1 , a mask 1701 is formed while etching away the gate stack 1601 from the substrate regions 1302A and 1302B and the mask 1701 is used to cover the substrate region 1302C. After etching, the mask 1701 is stripped off.

[0102] like Fig.18 As shown in the cross-sectional view 1800, Fig.17 A gate stack 1801 is formed on the structure shown in the cross-sectional view 1700 of FIG. The gate stack 1801 is formed on the gate stack 1601 in the substrate region 1302C. The gate stack 1801 includes Figure 1 The layers of the transistor 100 are shown. The gate stack 1801 includes an electrode layer 1803 , a gate dielectric layer 1805 , a first buried layer 1806 , a first thin gate dielectric layer 1810 , a channel layer 1807 , and a hard mask layer 1809 .

[0103] like Fig.19As shown in the cross-sectional view 1900 of , a mask 1901 is formed while etching away the gate stack 1801 from the substrate regions 1302A and 1302C and the mask 1901 is used to cover the substrate region 1302B. Above the substrate region 1302C, the etching stops on the hard mask layer 1609. After etching, the mask 1901 is stripped off.

[0104] like Fig. 20 As shown in the cross-sectional view 2000, Fig.19 A gate stack 2001 is formed on the structure shown in the cross-sectional view 1900 of FIG. The gate stack 2001 includes an electrode layer 2003 , a gate dielectric layer 2005 , a channel layer 2007 and a hard mask layer 2009 .

[0105] like Fig.21 As shown in the cross-sectional view 2100 of , a mask 2101 is formed while etching away the gate stack 2001 from the substrate regions 1302B and 1302C and the mask 2101 is used to pattern a bottom gate transistor 1304A from the gate stack 2001 in the substrate region 1302A. Above the substrate region 1302B, the etching stops on the hard mask layer 1809. Above the substrate region 1302C, the etching stops on the hard mask layer 1609. Patterning the bottom gate transistor 1304A includes patterning a bottom gate electrode 113A from the electrode layer 2003, patterning a gate dielectric 111A from the gate dielectric layer 2005, and patterning a channel layer 107A from the channel layer 2007.

[0106] like Fig. 22 As shown in the cross-sectional view 2200 of , a mask 2209 is formed and the gate stack 1801 is patterned in the substrate region 1302B while covering the substrate regions 1302A and 1302C using the mask 2209. In the substrate region 1302B, etching defines the bottom gate transistor 1304B, which includes patterning a bottom gate electrode 113B from the electrode layer 1803, patterning a gate dielectric 111B from the gate dielectric layer 1805, patterning a buried layer 109B from the first buried layer 1806, patterning a thin layer 110 from the first thin gate dielectric layer 1810, and patterning a channel layer 107B from the channel layer 1807.

[0107] like Fig.23As shown in the cross-sectional view 2300 of , a mask 2301 is formed and the mask 2301 is used to pattern the gate stack 1601 in the substrate region 1302C while covering the substrate regions 1302A and 1302B. In the substrate region 1302C, etching defines a bottom gate transistor 1304C, which includes patterning a bottom gate electrode 113C from the electrode layer 1603, patterning a gate dielectric 111C from the gate dielectric layer 1605, patterning a second buried layer 209C from the second buried layer 1604, patterning a second thin layer 210C from the second thin gate dielectric layer 1608, patterning a first buried layer 109C from the first buried layer 1606, patterning a first thin layer 110C from the first thin gate dielectric layer 1610, and patterning a channel layer 107C from the channel layer 1607. In view of the similarity between gate stack 1801 and gate stack 1601, Fig. 22 Etching and Fig.23 The etching is combined into a single patterning process.

[0108] like Fig.24 As shown in the cross-sectional view 2400 of FIG. 24, sidewall spacers 1307 may be formed around the bottom gate transistors 1304A, 1304B, and 1304C. The sidewall spacers 1307 may be nitrides, carbides, oxides, similar materials, combinations thereof, or any other suitable dielectric structure. The sidewall spacers 1307 may be formed by deposition followed by etching. The spacer material may be deposited by CVD, PVD, or a similar process.

[0109] like Fig.25 As shown in the cross-sectional view 2500, Fig.24 An anti-reflective coating (ARC) 2501 or other suitable filling material is deposited on the structure shown in the cross-sectional view 2400 of FIG. ARC 2501 fills the gaps between the bottom gate transistors 1304A, 1304B, and 1304C. Fig.26 As shown in the cross-sectional view 2600 of FIG. 26, planarization may then be performed. The planarization process may be chemical mechanical polishing (CMP) or a similar process. Planarization removes the hard mask layers 1609, 1809, and 2009. Fig. 27 As shown in the cross-sectional view 2700, after planarization, ARC 2501 is peeled off.

[0110] like Fig.28As shown in the cross-sectional view 2800 of FIG. 28 , an ILD layer 103 may then be deposited. The ILD layer 103 may be silicon oxide (SiO), a low-κ dielectric, a similar material, or any other suitable dielectric. The ILD layer 103 may be formed by CVD, PVD, or any other suitable process. Fig.29 As shown in the cross-sectional view 2900 of FIG. 29, a mask 2901 may be formed and an opening 2903 may be etched in the ILD layer 103 using the mask 2901. Fig.30 As shown in the cross-sectional view 3000 of , the opening 2903 may be filled with a conductive material to form the source region 101 and the drain region 105. The conductive material may be a metal, a similar material, or any other suitable conductive material.

[0111] Available in Fig.30 An interlayer dielectric layer 1311, a through hole 1309 and a metallization layer M are formed on the structure shown in the cross-sectional view 3000 of FIG. X+1 , to produce something like Fig.13 The IC device 1300 is shown as an IC device. The via 1309 couples the source region 101 and the drain region 105 to the metallization layer M. X+1 The metal wire 1314 in.

[0112] Figures 31 to 41 is a cross-sectional view illustrating a method of forming an IC device having a top gate transistor according to the present disclosure. Although various embodiments of the method are described with reference to Figures 31 to 41 , but it should be understood that Figures 31 to 41 The structure shown in is not limited to the method, but can exist independently of the method. Figures 31 to 41 The sequence of actions may be described as a series of actions. In other embodiments, the sequence of the actions may be changed. Figures 31 to 41 A particular set of actions is shown and described, but some actions may be omitted in other embodiments. In addition, actions not shown and / or described may be included in other embodiments. Fig.14 IC device 1400 or similar device is shown to illustrate Figures 31 to 41 The method is not limited to the method of FIG. 1 , but the method and its variations can be used to form other IC devices.

[0113] like Fig.31 As shown in the cross-sectional view 3100 of FIG. 1 , the process first forms a gate stack 3101 on the semiconductor substrate 707. The gate stack 3101 includes Figure 83 and 4. The layers of the top gate transistor 800 are shown. The gate stack 3101 includes a first thin gate dielectric layer 3110, a first buried layer 3106, a second thin gate dielectric layer 3108, a second buried layer 3104, a gate dielectric layer 3105, an electrode layer 3103, and a hard mask layer 3109. These layers may be produced by PVD, CVD, ALD, similar processes, or any other suitable process.

[0114] like Fig.32 As shown in the cross-sectional view 3200 of , the mask 3201 can be used to cover the substrate region 707C while etching away the gate stack 3101 from the substrate region 707A and the substrate region 707B. After etching, the mask 3201 is stripped off.

[0115] like Fig.33 As shown in the cross-sectional view 3300, Fig.32 A gate stack 3301 is formed on the structure shown in the cross-sectional view 3200 of FIG. The gate stack 3301 includes a gate stack 3301 corresponding to Figure 7 The layers of the top gate transistor 700 are shown. The gate stack 3301 includes a first thin gate dielectric layer 3310 , a first buried layer 3306 , a gate dielectric layer 3305 , an electrode layer 3303 , and a hard mask layer 3309 .

[0116] like Fig.34 As shown in the cross-sectional view 3400 of , the mask 3401 can be used to cover the substrate region 707B while etching away the gate stack 3301 from the substrate region 707A and the substrate region 707C. After etching, the mask 3401 is stripped off.

[0117] like Fig.35 As shown in the cross-sectional view 3500, Fig.32 A gate stack 3501 is formed on the structure shown in the cross-sectional view 3200 of FIG. The gate stack 3501 includes a gate stack 3501 corresponding to Figure 7 The layers of the top gate transistor 700 are shown. The gate stack 3501 includes a gate dielectric layer 3505, an electrode layer 3503, and a hard mask layer 3509.

[0118] like Fig.36 As shown in the cross-sectional view 3600 of , while etching away the gate stack 3501 from the substrate regions 707B and 707C, the mask 3601 is used to pattern the top gate transistor 1404A from the gate stack 3501 in the substrate region 707A. After etching, the mask 3601 is stripped off.

[0119] like Fig.37As shown in the cross-sectional view 3700 of , mask 3701 is used to cover top gate transistor 1404A in substrate region 707A while patterning transistor 1404B from gate stack 3301 in substrate region 707B and transistor 1404C from gate stack 3101 in substrate region 707C. After patterning, mask 3701 is stripped.

[0120] like Fig.38 As shown in the cross-sectional view 3800 of FIG. 38A , sidewall spacers 705 may be formed around the top gate transistors 1404A, 1404B, and 1404C. The sidewall spacers 705 are nitrides, carbides, oxides, similar materials, combinations thereof, or any other suitable dielectric. The sidewall spacers 705 may be formed by deposition followed by etching. The spacer material may be deposited by CVD, PVD, or a similar process.

[0121] like Fig.39 As shown in the cross-sectional view 3900 of FIG. 39 , the source region 701 and the drain region 703 may be formed by doping the semiconductor substrate 707 in a manner aligned with the sidewall spacers 705. The doping may include ion implantation followed by annealing.

[0122] like Fig.40 As shown in the cross-sectional view 4000, Fig.39 An ILD layer 715 is deposited on the structure shown in the cross-sectional view 3900. Fig.41 As shown in cross-sectional view 4100 of , planarization may then be used to remove hard mask layers 3109 , 3309 , and 3509 .

[0123] Fig.42 A flow chart of a process 4200 that may be used to form an IC device having bottom gate transistors according to the present disclosure is presented. Fig.42 The process 4200 is shown and described herein as a series of actions or events, but it should be understood that the order in which these actions or events are shown should not be interpreted as having a limiting meaning. For example, some actions may occur in a different order and / or occur simultaneously with other actions or events other than those shown and / or described herein. In addition, not all of the actions shown are required when implementing one or more aspects or embodiments described herein, and one or more of the actions depicted herein may be performed in one or more separate actions and / or stages.

[0124] The process 4200 may begin with act 4201 (front end of line (FEOL) processing) and may continue to act 4203, which forms several metallization layers. Fig.15 An example is provided in cross-sectional view 1500 .

[0125] Action 4205 forms a first gate stack. The first gate stack and all other depositions extend over the first, second, and third regions of the substrate. Forming the first gate stack includes: action 4207, forming a bottom electrode layer; action 4209, forming a gate dielectric layer; action 4219, forming a channel layer; and action 4221, forming a hard mask layer. Action 4205 may optionally include one or more of the following actions: action 4211, depositing a second buried layer; action 4213, depositing a second thin layer; action 4215, depositing a first buried layer; and action 4217, depositing a first thin layer. Depositing a thin layer may include depositing a few angstroms of gate dielectric layer material. By making appropriate selections among these optional actions, a gate stack corresponding to the substrate may be formed. Figure 1 to Figure 2 and Figures 4 to 6 The gate stack of any of transistors 100 , 200 , 400 , 500 , or 600 is shown. Fig.16 Cross-sectional view 1600 provides an example of action 4205.

[0126] Action 4223 is to etch away the first gate stack from the first region and the second region. Fig.17 An example is provided in cross-sectional view 1700 .

[0127] Action 4225 forms a second gate stack. Action 4225 is similar to action 4205 but may use different options among the optional steps and may use different layer compositions or thicknesses. Fig.18 An example is provided in cross-sectional view 1800 .

[0128] Action 4227 is to etch away the second gate stack from the first region and the third region. Fig.19 An example is provided in cross-sectional view 1900 .

[0129] Action 4229 forms a third gate stack. Action 4229 is similar to action 4205 but may use different options among optional steps and may use different layer compositions or thicknesses. Fig. 20 An example is provided in the cross-sectional view 2000 .

[0130] Action 4231 is patterning the third gate stack in the first region while etching the third gate stack from the second region and the third region. Fig.21 An example is provided in cross-sectional view 2100 .

[0131] Action 4233 is patterning the first gate stack in the third region and patterning the second gate stack in the second region. Such patterning can be accomplished using one patterning process or two patterning processes. Fig. 22 and Fig.23 Cross-sectional views 2200 and 2300 provide examples.

[0132] Action 4235 is forming a spacer adjacent to a transistor resulting from patterning the first gate stack, the second gate stack, and the third gate stack. Fig.24 An example is provided in cross-sectional view 2400 .

[0133] Action 4237 is planarization for removing the hard mask layer from the transistors. Prior to planarization, a material is deposited to fill the space between the transistors. The fill material may be an ILD layer or a temporary material (such as an ARC coating) that may be removed after planarization. Figure 25 to Figure 27 Cross-sectional views 2500 to 2700 provide examples.

[0134] Action 4239 is to form source and drain regions above the gate electrode of the transistor. This may include depositing an ILD layer, etching openings in the ILD layer, and filling the openings with metal or other conductive materials to provide source and drain regions. Figures 28 to 30 Examples are provided in cross-sectional views 2800 to 3000 .

[0135] Action 4241 is to form an upper metallization layer in contact with the source and drain regions. Fig.13 IC device 1300 provides an example of the resulting structure.

[0136] Fig.43 A flow chart of a process 4300 that may be used to form an IC device having top gate transistors according to the present disclosure is presented. Fig.43 The process 4300 is shown and described herein as a series of actions or events, however, it should be understood that the order in which these actions or events are shown should not be interpreted as having a limiting meaning. For example, some actions may occur in a different order and / or occur simultaneously with other actions or events other than those shown and / or described herein. In addition, not all of the actions shown are required when implementing one or more aspects or embodiments described herein, and one or more of the actions depicted herein may be performed in one or more separate actions and / or stages.

[0137] Process 4300 may first perform an act 4301 of providing a semiconductor substrate and an act 4303 of forming a first gate stack on the substrate. Forming the first gate stack includes: an act 4313 of forming a gate dielectric layer; an act 4315 of forming an electrode layer; and an act 4317 of forming a hard mask layer. Act 4303 may optionally include one or more of the following acts: an act 4305 of forming a first thin layer; an act 4307 of depositing a first buried layer; an act 4309 of depositing a second thin layer; and an act 4311 of depositing a second buried layer. Fig.31The cross-sectional view 3100 of FIG. 3100 provides an example. Depositing a thin layer may include depositing a few angstroms of gate dielectric material. By appropriately selecting among these optional actions, a corresponding Figures 7 and 8 and Figures 10 to 12 The gate stack of any of transistors 700 , 800 , 1000 , 1100 , or 1200 is shown.

[0138] Action 4319 is to etch away the first gate stack from the first region and the second region. Fig.32 An example is provided in cross-sectional view 3200 .

[0139] Action 4321 is to form a second gate stack. Fig.33 An example is provided by cross-sectional view 3300 of . Action 4321 is similar to action 4303 but different options may be used among the optional steps and different layer compositions or thicknesses may be used.

[0140] Action 4323 is to etch away the second gate stack from the first region and the third region. Fig.34 An example is provided in cross-sectional view 3400 .

[0141] Action 4325 is to form a third gate stack. Fig.35 An example is provided by cross-sectional view 3500 of . Action 4325 is similar to action 4303 but different options may be used among the optional steps and different layer compositions or thicknesses may be used.

[0142] Action 4327 is patterning the third gate stack in the first region while etching the third gate stack from the second region and the third region. Fig.36 An example is provided in cross-sectional view 3600 .

[0143] Action 4329 is to pattern the first gate stack in the third region and pattern the second gate stack in the second region. Such patterning can be accomplished using one patterning process or two patterning processes. Fig.37 An example is provided in cross-sectional view 3700 .

[0144] Action 4331 is forming a spacer adjacent to a transistor resulting from patterning the first gate stack, the second gate stack, and the third gate stack. Fig.38 An example is provided in cross-sectional view 3800 .

[0145] Action 4333 is to perform doping to form source and drain regions aligned with the spacers. Fig.39 An example is provided in cross-sectional view 3900 .

[0146] Action 4335 is to deposit an ILD layer over the transistor. Fig.40 The cross-sectional view 4000 provides an example.

[0147] Action 4337 is the planarization used to remove the hard mask layer from the transistor. Fig.41 An example is provided in cross-sectional view 4100 .

[0148] Some aspects of the present disclosure relate to an integrated circuit device, the integrated circuit device including a transistor, the transistor having a gate electrode, a gate dielectric and a semiconductor channel. The gate dielectric is located between the gate electrode and the semiconductor channel. A second dielectric layer is embedded in the gate dielectric. The second dielectric layer has a higher dielectric constant than the gate dielectric.

[0149] In some embodiments, the second dielectric layer is closer to the semiconductor channel than to the gate electrode. In some embodiments, the thickness of the second dielectric layer is less than the distance from the second dielectric layer to the gate electrode. In some embodiments, the gate dielectric and the second dielectric layer are oxides. In some embodiments, the gate dielectric is silicon dioxide (SiO 2 ). In some embodiments, the second dielectric layer is a mixture of two dielectrics. The oxygen surface density of the two dielectrics is in any of the following situations: both oxygen surface densities are higher than the oxygen surface density of the gate dielectric or both oxygen surface densities are lower than the oxygen surface density of the gate dielectric. In some embodiments, the third dielectric layer is embedded in the gate dielectric. The third dielectric layer has a higher dielectric constant than the gate dielectric. In some embodiments, a thin layer of gate dielectric separates the second dielectric layer from the third dielectric layer.

[0150] In some embodiments, the gate dielectric and the second dielectric layer have a greater electronegativity difference than the electronegativity difference between silicon dioxide and hafnium oxide. In some embodiments, the gate dielectric and the second dielectric layer have a greater oxygen surface density difference than the oxygen surface density difference between silicon dioxide and hafnium oxide. In some embodiments, the semiconductor channel is located above the semiconductor channel. In some embodiments, the semiconductor channel is located below the semiconductor channel.

[0151] Some aspects of the present disclosure relate to an integrated circuit device, the integrated circuit device including a transistor, the transistor having a gate electrode, a gate dielectric structure, and a semiconductor channel. The gate dielectric structure includes a first dielectric layer and a second dielectric layer. The first dielectric layer is at least half the thickness of the gate dielectric structure and is located between the second dielectric layer and the gate electrode. The second dielectric layer has a higher dielectric constant than the first dielectric layer.

[0152] In some embodiments, the second dielectric layer is spaced apart from the semiconductor channel. In some embodiments, the gate dielectric structure further includes a third dielectric layer. The third dielectric layer has a different composition than the first dielectric layer and the second dielectric layer and has a higher dielectric constant than the first dielectric layer. In some embodiments, the third dielectric layer is spaced apart from the second dielectric layer. In some embodiments, the second dielectric layer comprises a mixture of two dielectrics, the two dielectrics having a higher dielectric constant than the first dielectric layer.

[0153] Some aspects of the present disclosure relate to an integrated circuit device, the integrated circuit device including a transistor having a gate electrode, a gate dielectric structure, and a semiconductor channel. The gate dielectric structure includes a first dielectric layer and a second dielectric layer. A first interface between the first dielectric layer and the second dielectric layer is closer to the semiconductor channel than to the gate electrode. A composition of the first dielectric layer and a composition of the second dielectric layer cause an electrical dipole to be formed in the gate dielectric structure near the first interface. The electrical dipole significantly affects the threshold voltage of the transistor.

[0154] Some aspects of the present disclosure relate to a method of forming a dielectric structure between a semiconductor and a gate electrode. Forming the dielectric structure includes embedding a high-κ dielectric layer within a gate dielectric. The high-κ dielectric layer has a higher dielectric constant than the gate dielectric. In some embodiments, embedding the high-κ dielectric layer within the gate dielectric includes: depositing a first layer of the gate dielectric; depositing the high-κ dielectric layer over the first layer; and depositing a second layer of the gate dielectric over the high-κ dielectric layer. In some embodiments, the high-κ dielectric layer is thinner than the gate dielectric and closer to the semiconductor.

[0155] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated circuit device comprising: A transistor having a gate electrode, a gate dielectric and a semiconductor channel, wherein the gate dielectric is located between the gate electrode and the semiconductor channel; as well as The buried layer is embedded in the gate dielectric, wherein the buried layer has a higher dielectric constant than the gate dielectric. 2 . The integrated circuit device according to claim 1 , wherein the buried layer is closer to the semiconductor channel than to the gate electrode. 3 . The integrated circuit device according to claim 1 , wherein a thickness of the buried layer is smaller than a distance from the buried layer to the gate electrode.

4. The integrated circuit device according to claim 1, wherein the gate dielectric is silicon dioxide (SiO2), and the buried layer is gallium oxide (Ga2O3), indium oxide (In2O3), zinc oxide (ZnO), aluminum oxide (Al2O3), titanium oxide (TiO2) or hafnium oxide (HfO2). 5 . The integrated circuit device of claim 1 , further comprising a second buried layer embedded in the gate dielectric, wherein the second buried layer has a higher dielectric constant than the gate dielectric.

6. An integrated circuit device comprising: A transistor having a gate electrode, a gate dielectric structure and a semiconductor channel; wherein the gate dielectric structure comprises a first dielectric layer and a second dielectric layer; The first dielectric layer is at least half the thickness of the gate dielectric structure and is located between the second dielectric layer and the gate electrode; and The second dielectric layer has a higher dielectric constant than the first dielectric layer.

7. The integrated circuit device according to claim 6, wherein: The gate dielectric structure further includes a third dielectric layer; The third dielectric layer has a different composition than the first dielectric layer and the second dielectric layer; and The third dielectric layer has a higher dielectric constant than that of the first dielectric layer. 8 . The integrated circuit device according to claim 7 , wherein the third dielectric layer is spaced apart from the second dielectric layer.

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