Circuit for realizing overload transient state

Abstract

The utility model belongs to the technical field of control circuits, and discloses a circuit for realizing an overload transient state, when an output load is detected to be less than 110% load, a seventh pin of an LM2904DGKR outputs a high level, and a first pin outputs a low level, so that a cathode of a BAV70 is at a high level, and an ILIMT level is maintained in an original state; when it is detected that the output load is larger than 110% load and smaller than 130% load, the seventh pin of the LM2904DGKR outputs a low level, the first pin of the LM2904DGKR outputs a low level, the cathode of the BAV70 is in a low level, and the level of the ILIMT is pulled down; when it is detected that the output load is larger than 130% load, the seventh pin of the LM2904DGKR outputs low level, the first pin of the LM2904DGKR outputs high level, the cathode of the BAV70 is high level, and the level of the ILIMT is kept in the original state. The beneficial effects of the utility model are that under the condition that the original performance and advantages are kept unchanged, the ILIMT voltage is lowered to prevent the ILIMT voltage from triggering a set protection point by limiting the moment that the transient peak power triggers the overpower protection, so that the overload dynamic function is realized.

Description

Technical Field

[0001] The utility model relates to the technical field of control circuits, in particular to a circuit for realizing overload transient state. Background Art

[0002] With the needs of society and the development of graphics card technology, the power of PSUs on the market is rising steadily. At the same time, because graphics cards operate in "frames", similar to the sawtooth wave of PWN, some players blindly buy high-power power supplies to prevent the PSU from being "exhausted", but such high power is rarely used in daily home use, resulting in cost and energy waste. Some PSUs on the market that meet the ATX3.0 specification are achieved by infinitely amplifying the maximum load capacity, which will increase the stress on the PSU's own components and pose a great risk of damage.

[0003] Intel has released the most significant update to the industry power specification since the original ATX 2.0 specification was introduced in 2003. The updated ATX 3.0 specification unlocks the full capabilities and potential of next-generation hardware and upcoming components targeting technologies such as PCIe Gen 5.0. Intel has also revised its ATX12VO specification, providing the PC industry with an updated blueprint for designing power supply units (PSUs) and motherboards to reduce power consumption when idle, helping customers reduce power requirements.

[0004] With the introduction of the ATX 3.0 and ATX12VO 2.0 specifications, a compatible power supply is essential for desktop users who want to get the best performance from the next generation of PCIe 5.0 desktop graphics cards. These next generation graphics cards will be more powerful than before, and in order to be able to maximize system performance, the proper power supply needs to be in place. A new 12VHPWR connector will be required to power most future PCIe 5.0 desktop add-in cards (such as graphics cards), this new connector provides up to 600 watts of power directly to any PCIe 5.0 add-in / graphics card. It also includes sideband signaling that will allow the power supply to communicate the power limit that it can provide to any PCIe 5.0 graphics card.

[0005] Therefore, it is necessary to provide a circuit to realize overload transient. This circuit can make good use of the advantages of LM2904DGKR while realizing the requirements of output constant current control and power supply miniaturization. It has the advantages of simple control circuit and high efficiency, and has broad prospects in practical applications. Utility Model Content

[0006] The utility model discloses a circuit for realizing overload transient state, which can effectively solve the technical problems involved in the background technology.

[0007] To achieve the above purpose, the technical solution of the utility model is:

[0008] A circuit for realizing overload transient state, comprising a port +12VT, wherein the port +12VT is connected to pin 3 of a transformer T200, one end of a capacitor C8 and one end of a capacitor C126, a pin 4 of the transformer T200 is connected to the port +12VT, the other end of the capacitor C8 and the other end of the capacitor C126 are connected to a port AGND, a pin 1 of the transformer T200 is connected to one end of an inductor L3, the other end of the inductor L3 is connected to pin 2 of a current transformer TR1, the pin 1 of the current transformer TR1 and the pin 2 of the transformer T200 are connected to a voltage control circuit, the voltage control circuit is connected to a control chip U2, the pin 3 of the current transformer TR1 is connected to a port 6020, and the pin 4 of the current transformer TR1 is connected to a port 6018;

[0009] The port 6018 is connected to pin 1 of the BAV99 diode D10, the pin 2 of the BAV99 diode D10 is connected to one end of the resistor R91, one end of the resistor R401 and pin 2 of the BAV99 diode D12, the pin 3 of the BAV99 diode D10 is connected to pin 3 of the BAV99 diode D12 and port AGND, the port 6020 is connected to pin 1 of the BAV99 diode D12, the other end of the resistor R91 is connected to port LIMIT1, one end of the resistor R29, the other end of the resistor R401 and the resistor The positive end of the diode D14 is connected to one end of the resistor R68, the other end of the resistor R29 is connected to the other end of the resistor R68, one end of the resistor R180, one end of the resistor R92, one end of the capacitor C47 and the positive end of the diode D14, the negative end of the diode D14 is connected to one end of the capacitor C62 and one end of the resistor R94, the other end of the resistor R94 is connected to the port ILIMT, the other end of the resistor R180, the other end of the resistor R92, the other end of the capacitor C47 and the other end of the capacitor C62 are connected to the port AGND, and the port ILIMT is connected to the control chip U2;

[0010] The port LIMIT1 is connected to the negative end of the voltage regulator tube Z7, the positive end of the voltage regulator tube Z7 is connected to one end of the resistor R202, the other end of the resistor R202 is connected to one end of the capacitor C159, one end of the resistor R221, one end of the resistor R201 and one end of the resistor R220, the other end of the capacitor C159 is connected to the other end of the resistor R201, one end of the capacitor C160, one end of the resistor R222 and the port AGND, the other end of the resistor R220 is connected to one end of the capacitor C158 and the pin 6 of the operational amplifier U11, the other end of the capacitor C160 is connected to the other end of the capacitor C158, the pin 5 of the operational amplifier U11, one end of the resistor R200, the other end of the resistor R222 and one end of the resistor R204, the other end of the resistor R204 is connected to the port +5VS, the other end of the resistor R200 is connected to the pin 7 of the operational amplifier U11 and one end of the resistor R206, the port +5VS VS is connected to one end of resistor R194, the other end of the resistor R194 is connected to one end of capacitor C153, one end of resistor R191, one end of capacitor C124 and pin 2 of the operational amplifier U11, the other end of the capacitor C153 and the other end of the resistor R191 are connected to port AGND, the other end of the capacitor C124 is connected to the other end of the resistor R221, pin 3 of the operational amplifier U11 and one end of resistor R192, the other end of the resistor R192 and pin 1 of the operational amplifier U11 are connected to the positive end of diode D15, the negative end of diode D15 is connected to the other end of resistor R206 and pin 1 of BAV70 diode D11, pin 2 of BAV70 diode is connected to one end of resistor R195, pin 3 of BAV70 diode is connected to one end of resistor R190, the other end of resistor R195 and the other end of resistor R190 are connected to port ILIMT.

[0011] Specifically, the LM2904DGKR dual operational amplifier is used, and a method for implementing ATX3.0 (overload dynamic) control without changing the main power device is used. The core of the method is to determine the output load condition by sampling the resonant cavity current through the current transformer, and then accurately control the ILIMT state through LM2904DGKR operation and comparison to achieve the ability of transient overload PSU to work normally. The control method is that when it is detected that the output load is less than 110% load, the 7th pin of LM2904DGKR outputs a high level and the 1st pin outputs a low level, so that the cathode of BAV70 is high and the ILIMT level maintains the original state; when it is detected that the output load is greater than 110% load and less than 130% load, the 7th pin of LM2904DGKR outputs a low level and the 1st pin outputs a low level, so that the cathode of BAV70 is low and the ILIMT level will be pulled low; when it is detected that the output load is greater than 130% load, the 7th pin of LM2904DGKR outputs a low level and the 1st pin outputs a high level, so that the cathode of BAV70 is high and the ILIMT level maintains the original state.

[0012] Compared with the traditional circuit, the utility model adds a transient over-power protection limit function on the original basis. On the basis of not affecting the original performance, it can meet the latest Intel 3.0 specification. The newly added circuit is relatively independent, which increases the reliability of the PSU. The method of implementing this mode is that when the ILIMT voltage is not limited, when the output power increases, the ILIMT voltage will also increase to the set protection point, and the PSU will be locked for protection. This mode utilizes the transient load increase process. When it is detected that the load is greater than 110% load and less than 130% load, the circuit will pull down the ILIMT voltage so that it will not trigger the set protection point, thereby realizing the overload dynamic function. In simple terms, it is a circuit that realizes the latest Intel ATX3.0 specification (overload dynamic control) by instantly changing the ILIMT state (when the ILIMT voltage is greater than 7.5V, the whole machine triggers the OPP point protection) and limiting the ILIMT voltage.

[0013] As a preferred improvement of the present utility model: the port +12VT is connected to a load device.

[0014] As a preferred improvement of the present invention: the load device includes one or more of a graphics card, a CPU, a GPU, a display and a hard disk.

[0015] As a preferred improvement of the present invention: the port +5VS is connected to a power source.

[0016] As a preferred improvement of the present utility model: the operational amplifier U11 is of model LM2904DGKR.

[0017] As a preferred improvement of the utility model: the voltage control circuit includes a port VCCB, the port VCCB is connected to the positive end of the diode D37, the negative end of the diode D37 is connected to one end of the capacitor C16 and the collector of the transistor Q44, the base of the transistor Q44 is connected to the base of the transistor Q46 and the port HG, the emitter of the transistor Q44 is connected to the emitter of the transistor Q46, one end of the resistor R209 and the negative end of the diode D3, the positive end of the diode D3 is connected to one end of the resistor R93, the other end of the resistor R209 is connected to the positive end of the diode D3, and the positive end of the diode D3 is connected to one end of the resistor R93. The other end of the resistor R93, one end of the resistor R205, one end of the bidirectional voltage regulator Z10 and the gate of the MOS tube Q8 are connected, the drain of the MOS tube Q8 is connected to the port +VDC and one end of the capacitor C217, the other end of the capacitor C16, the collector of the triode Q46, the other end of the resistor R205, the other end of the bidirectional voltage regulator Z10, the source of the MOS tube Q8, the other end of the capacitor C217, the drain of the MOS tube Q9 and one end of the capacitor C223 are connected to the pin 1 of the current transformer TR1;

[0018] The port VCCB is connected to one end of the capacitor C189 and the collector of the transistor Q45, the base of the transistor Q45 is connected to the base of the transistor Q47 and the port LG, the emitter of the transistor Q45 is connected to the emitter of the transistor Q47, one end of the resistor R35 and the negative end of the diode D5, the positive end of the diode D5 is connected to one end of the resistor R145, the other end of the resistor R35 is connected to the other end of the resistor R145, one end of the resistor R235, one end of the bidirectional voltage regulator Z11 and the gate of the MOS tube Q9, and the The other end of capacitor C189, the collector of the transistor Q47, the other end of the bidirectional voltage regulator Z11, the other end of the resistor R235, the source of the MOS tube Q9, the other end of the capacitor C223, one end of the capacitor C218, one end of the capacitor C14 and one end of the capacitor C201 are connected to port GND, the other end of the capacitor C218, the other end of the capacitor C14 and the other end of the capacitor C201 are connected to pin 2 of the transformer T200, and the port HG and the port LG are connected to the control chip U2.

[0019] As a preferred improvement of the utility model: Pin 1 of the control chip U2 is connected to port VREF1, one end of resistor R9, one end of resistor R80 and one end of capacitor C26; Pin 2 of the control chip U2 is connected to the other end of the resistor R9 and one end of resistor R8; the other end of the resistor R8 is connected to port AGND; Pin 3 of the control chip U2 is connected to one end of resistor R86, one end of resistor R20, one end of capacitor C31, one end of resistor R16, one end of resistor R11 and one end of capacitor C67; the other end of capacitor C31 is connected to one end of resistor R21; the other end of resistor R21 is connected to one end of resistor R259, the other end of resistor R20, the other end of resistor R86 and one end of resistor R109; the other end of resistor R259 is connected to Port +12VS, the other end of the resistor R109 is connected to port +12VT, pin 4 of the control chip U2 is connected to one end of the capacitor C145 and one end of the resistor R81, the other end of the resistor R81 is connected to one end of the capacitor C28, pin 5 of the control chip U2 is connected to the other end of the resistor R80, one end of the capacitor C25, one end of the resistor R71 and one end of the resistor R60, the other end of the resistor R60 is connected to one end of the capacitor C97, the other end of the resistor R16, the other end of the resistor R11, the other end of the capacitor C67, the other end of the capacitor C145, the other end of the capacitor C28, the other end of the capacitor C26, the other end of the capacitor C25, the other end of the resistor R71 and the other end of the capacitor C97 are connected to port AGND;

[0020] Pin 7 of the control chip U2 is connected to one end of the resistor R23, the other end of the resistor R23 is connected to one end of the capacitor C61, pin 8 of the control chip U2 is connected to port ILIMT, one end of the resistor R82, one end of the capacitor C29 and one end of the resistor R402, the other end of the resistor R82 is connected to the negative end of the diode D9, the positive end of the diode D9 is connected to port VREF1 and one end of the resistor R83, pin 9 of the control chip U2 is connected to the other end of the resistor R83 and one end of the capacitor C30, pin 10 of the control chip U2, one end of the capacitor C37, one end of the capacitor C85, the other end of the capacitor C30, the other end of the capacitor C29, the other end of the resistor R402 and the other end of the capacitor C61 are connected to port AGND;

[0021] Pin 13 of the control chip U2 is connected to port LG, pin 14 of the control chip U2 is connected to port HG, port LG and port HG are connected to the voltage control circuit, and pin 15 of the control chip U2 is connected to pin 16 of the control chip U2, the other end of the capacitor C37, the other end of the capacitor C85 and port VDD.

[0022] As a preferred improvement of the present invention: the port +12VS and the port +12VT are connected to a load device.

[0023] As a preferred improvement of the present invention: the port VDD is connected to a power supply.

[0024] As a preferred improvement of the present invention: the model of the control chip U2 is CU6901VACISTR.

[0025] The beneficial effects of the utility model are as follows:

[0026] The utility model keeps the original performance and advantages unchanged, limits the instant when the transient peak power triggers the over-power protection, pulls down the ILIMT voltage so that it does not trigger the set protection point, thereby realizing the overload dynamic function, and can fully meet and realize the Intel ATX3.0 specification. The circuit simplifies the system design, has the advantages of simplicity and high efficiency, and has broad application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present utility model, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative work, among which:

[0028] Figure 1 This is a schematic diagram of the voltage control circuit of the utility model;

[0029] Figure 2 This is a schematic diagram of the current signal processing part of the utility model;

[0030] Figure 3 This is a schematic diagram of the signal processing part of ILIMT1 of the utility model;

[0031] Figure 4 This is a partial schematic diagram of the control chip of the utility model. DETAILED DESCRIPTION

[0032] The technical solutions in the embodiments of the present invention will be described clearly and completely below in combination with the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0033] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0034] In addition, in the present invention, descriptions such as "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0035] In the present invention, unless otherwise clearly specified and limited, the terms "connection", "fixation", etc. should be understood in a broad sense. For example, "fixation" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0036] In addition, the technical solutions between the various embodiments of the present invention can be combined with each other, but it must be based on the fact that ordinary technicians in the field can implement it. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0037] See also Figure 1As shown, the utility model provides a circuit for realizing overload transient, including port +12VT, the port +12VT is connected to pin 3 of transformer T200, one end of capacitor C8 and one end of capacitor C126, pin 4 of transformer T200 is connected to port +12VT, the other end of capacitor C8 and the other end of capacitor C126 are connected to port AGND, pin 1 of transformer T200 is connected to one end of inductor L3, the other end of inductor L3 is connected to pin 2 of current transformer TR1, pin 1 of current transformer TR1 and pin 2 of transformer T200 are connected to voltage control circuit, the voltage control circuit is connected to control chip U2, pin 3 of current transformer TR1 is connected to port 6020, and pin 4 of current transformer TR1 is connected to port 6018. In this embodiment, the port +12VT is connected to a load device, and the load device includes one or more of a graphics card, a CPU, a GPU, a display and a hard disk. Port +12VT connects to the device, detects the voltage and current of the device, and transmits them to the Figure 2 The circuit in Figure 2 The circuit processes the current signal, and transmits part of it to the control chip as the feedback point of over-protection, and the other part to the Figure 3 The circuit is processed.

[0038] See also Figure 2 As shown, the port 6018 is connected to the pin 1 of the BAV99 diode D10, the pin 2 of the BAV99 diode D10 is connected to one end of the resistor R91, one end of the resistor R401 and the pin 2 of the BAV99 diode D12, the pin 3 of the BAV99 diode D10 is connected to the pin 3 of the BAV99 diode D12 and the port AGND, the port 6020 is connected to the pin 1 of the BAV99 diode D12, the other end of the resistor R91 is connected to the port LIMIT1, one end of the resistor R29, the other end of the resistor R401 and One end of the resistor R68 and the other end of the resistor R29 are connected to the other end of the resistor R68, one end of the resistor R180, one end of the resistor R92, one end of the capacitor C47 and the positive end of the diode D14, the negative end of the diode D14 is connected to one end of the capacitor C62 and one end of the resistor R94, the other end of the resistor R94 is connected to the port ILIMT, the other end of the resistor R180, the other end of the resistor R92, the other end of the capacitor C47 and the other end of the capacitor C62 are connected to the port AGND, and the port ILIMT is connected to the control chip U2.

[0039] See also Figure 3As shown, the port LIMIT1 is connected to the negative end of the voltage regulator tube Z7, the positive end of the voltage regulator tube Z7 is connected to one end of the resistor R202, the other end of the resistor R202 is connected to one end of the capacitor C159, one end of the resistor R221, one end of the resistor R201 and one end of the resistor R220, the other end of the capacitor C159 is connected to the other end of the resistor R201, one end of the capacitor C160, one end of the resistor R222 and the port AGND, the other end of the resistor R220 is connected to the capacitor C15 8 and pin 6 of the operational amplifier U11, the other end of the capacitor C160 is connected to the other end of the capacitor C158, pin 5 of the operational amplifier U11, one end of the resistor R200, the other end of the resistor R222 and one end of the resistor R204, the other end of the resistor R204 is connected to port +5VS, the other end of the resistor R200 is connected to pin 7 of the operational amplifier U11 and one end of the resistor R206, the port +5VS is connected to one end of the resistor R194, the The other end of resistor R194 is connected to one end of capacitor C153, one end of resistor R191, one end of capacitor C124 and pin 2 of the operational amplifier U11, the other end of capacitor C153 and the other end of resistor R191 are connected to port AGND, the other end of capacitor C124 is connected to the other end of resistor R221, pin 3 of the operational amplifier U11 and one end of resistor R192, the other end of resistor R192 and pin 1 of the operational amplifier U11 are connected to the positive end of diode D15, the negative end of diode D15 is connected to the other end of resistor R206 and pin 1 of BAV70 diode D11, pin 2 of BAV70 diode is connected to one end of resistor R195, pin 3 of BAV70 diode is connected to one end of resistor R190, the other end of resistor R195 and the other end of resistor R190 are connected to port ILIMT, the port +5VS is connected to the power supply, and the model of operational amplifier U11 is LM2904DGKR.

[0040] See also Figure 1As shown, the voltage control circuit includes a port VCCB, the port VCCB is connected to the positive end of the diode D37, the negative end of the diode D37 is connected to one end of the capacitor C16 and the collector of the transistor Q44, the base of the transistor Q44 is connected to the base of the transistor Q46 and the port HG, the emitter of the transistor Q44 is connected to the emitter of the transistor Q46, one end of the resistor R209 and the negative end of the diode D3, the positive end of the diode D3 is connected to one end of the resistor R93, the other end of the resistor R209 is connected to the other end of the resistor R93, One end of the resistor R205, one end of the bidirectional voltage regulator Z10 and the gate of the MOS tube Q8, the drain of the MOS tube Q8 is connected to the port +VDC and one end of the capacitor C217, the other end of the capacitor C16, the collector of the transistor Q46, the other end of the resistor R205, the other end of the bidirectional voltage regulator Z10, the source of the MOS tube Q8, the other end of the capacitor C217, the drain of the MOS tube Q9 and one end of the capacitor C223 are connected to the pin 1 of the current transformer TR1; the port VCCB is connected to one end of the capacitor C189 end and the collector of the transistor Q45, the base of the transistor Q45 is connected to the base of the transistor Q47 and the port LG, the emitter of the transistor Q45 is connected to the emitter of the transistor Q47, one end of the resistor R35 and the negative end of the diode D5, the positive end of the diode D5 is connected to one end of the resistor R145, the other end of the resistor R35 is connected to the other end of the resistor R145, one end of the resistor R235, one end of the bidirectional voltage regulator Z11 and the gate of the MOS tube Q9, the other end of the capacitor C189, the collector of the transistor Q47, The other end of the bidirectional voltage regulator Z11, the other end of the resistor R235, the source level of the MOS tube Q9, the other end of the capacitor C223, one end of the capacitor C218, one end of the capacitor C14 and one end of the capacitor C201 are connected to port GND, the other end of the capacitor C218, the other end of the capacitor C14 and the other end of the capacitor C201 are connected to pin 2 of the transformer T200, the port HG and the port LG are connected to the control chip U2, and the transistor model is: D-FR / 1N4148W-SOD123-A.

[0041] See also Figure 4As shown, pin 1 of the control chip U2 is connected to port VREF1, one end of resistor R9, one end of resistor R80 and one end of capacitor C26, pin 2 of the control chip U2 is connected to the other end of the resistor R9 and one end of resistor R8, the other end of the resistor R8 is connected to port AGND, pin 3 of the control chip U2 is connected to one end of resistor R86, one end of resistor R20, one end of capacitor C31, one end of resistor R16, one end of resistor R11 and one end of capacitor C67, the other end of capacitor C31 is connected to one end of resistor R21, the other end of resistor R21 is connected to one end of resistor R259, the other end of resistor R20, the The other end of R86 is connected to one end of the resistor R109, the other end of the resistor R259 is connected to the port +12VS, the other end of the resistor R109 is connected to the port +12VT, the pin 4 of the control chip U2 is connected to one end of the capacitor C145 and one end of the resistor R81, the other end of the resistor R81 is connected to one end of the capacitor C28, the pin 5 of the control chip U2 is connected to the other end of the resistor R80, one end of the capacitor C25, one end of the resistor R71 and one end of the resistor R60, the other end of the resistor R60 is connected to one end of the capacitor C97, the other end of the resistor R16, the other end of the resistor R11, the other end of the capacitor C67, the other end of the capacitor C The other end of the capacitor C145, the other end of the capacitor C28, the other end of the capacitor C26, the other end of the capacitor C25, the other end of the resistor R71 and the other end of the capacitor C97 are connected to port AGND; pin 7 of the control chip U2 is connected to one end of the resistor R23, the other end of the resistor R23 is connected to one end of the capacitor C61, pin 8 of the control chip U2 is connected to port ILIMT, one end of the resistor R82, one end of the capacitor C29 and one end of the resistor R402, the other end of the resistor R82 is connected to the negative end of the diode D9, the positive end of the diode D9 is connected to port VREF1 and one end of the resistor R83, and pin 10 of the control chip U2 is connected to port ILIMT, one end of the resistor R82, one end of the capacitor C29 and one end of the resistor R402. Pin 9 is connected to the other end of the resistor R83 and one end of the capacitor C30, and pin 10 of the control chip U2, one end of the capacitor C37, one end of the capacitor C85, the other end of the capacitor C30, the other end of the capacitor C29, the other end of the resistor R402 and the other end of the capacitor C61 are connected to port AGND; pin 13 of the control chip U2 is connected to port LG, pin 14 of the control chip U2 is connected to port HG, port LG and port HG are connected to the voltage control circuit, and pin 15 of the control chip U2 is connected to pin 16 of the control chip U2, the other end of the capacitor C37, the other end of the capacitor C85 and port VDD.The port +12VS and the port +12VT are connected to the load device, the port VDD is connected to the power supply, the model of the control chip U2 is CU6901VACISTR (dedicated chip-PWM controller, SMD, CU6901VACISTR, SLS controll, LLC, 118KHz, SOP-16, CHAMPION), and the port ILIMT is the load voltage feedback pin. When the port voltage exceeds a certain value, the OPP protection will be triggered. The control chip U2 is connected to the power supply or other controller of the load to protect the load by cutting off power or limiting output.

[0042] The purpose is to provide a circuit for realizing Intel 3.0 overload dynamic control, using the characteristics of dynamic load increment to achieve precise control of ILIMT voltage, and has the advantages of small size, simplicity and high efficiency. The technical solution is as follows:

[0043] like Figure 1 : On the secondary side, +12VT is connected to devices such as graphics cards, CPUs, GPUs, monitors, hard disks, etc. through output cables. Different working conditions of CPUs, GPUs and other devices will correspond to different output load currents. The output load current is transmitted to the primary winding through T200 at 1 / N (N is the turns ratio of T200). On the primary side, the TR1 primary winding and the T200 primary winding are in series, that is, the currents are the same. The current through the TR1 primary winding will change with the output load, and the current signal will be transmitted to the TR1 secondary winding at a ratio of 1 / n (n is the turns ratio of TR1).

[0044] like Figure 2 :The current signal detected by the secondary winding of TR1 is processed by a rectifier diode and a series of resistors to output the voltage ILIMT1.

[0045] like Figure 3 : Through ILIMT1 conversion, when the output load is detected to be less than 110% load, the 7th pin of LM2904DGKR outputs a high level and the 1st pin outputs a low level, so that the cathode of BAV70 is high and the ILIMT level maintains the original state; when the output load is detected to be greater than 110% load and less than 130% load, the 7th pin of LM2904DGKR outputs a low level and the 1st pin outputs a low level, so that the cathode of BAV70 is low and the ILIMT level will be pulled low; when the output load is detected to be greater than 130% load, the 7th pin of LM2904DGKR outputs a low level and the 1st pin outputs a high level, so that the cathode of BAV70 is high and the ILIMT level maintains the original state.

[0046] like Figure 4:12VS is the output voltage sampling signal line, which controls the switching frequency of HG, LG and other drive signals by sampling the change of 12VT voltage, that is, the switching frequency of Q8, Q9, Q44, Q45, Q46, Q47 and other tubes, and the working state of L3, C14, C201, C218 and other devices, to maintain the stability of the output 12VT voltage. Figure 3 As shown, when the overload dynamic is performed, that is, 160% of the full load is maintained for 10ms, 180% of the load is maintained for 1ms, and 200% of the load is maintained for 0.1ms, the ILIMT voltage will be instantly pulled down at the moment of overload, that is, at this time, the voltage of the 8th foot of U2 will be instantly pulled down to below 7.5V, so that the PSU will not trigger the OPP protection, thereby realizing the overload dynamic.

[0047] Although the implementation scheme of the utility model has been disclosed as above, it is not limited to the applications listed in the specification and the implementation scheme. It can be fully applied to various fields suitable for the utility model. For those familiar with the art, additional modifications can be easily implemented. Therefore, without departing from the general concept defined by the claims and the scope of equivalents, the utility model is not limited to the specific details and the illustrations shown and described herein.

Claims

1. A circuit for realizing overload transient, characterized in that: Including port +12VT, the port +12VT is connected to pin 3 of transformer T200, one end of capacitor C8 and one end of capacitor C126, pin 4 of transformer T200 is connected to port +12VT, the other end of capacitor C8 and the other end of capacitor C126 are connected to port AGND, pin 1 of transformer T200 is connected to one end of inductor L3, the other end of inductor L3 is connected to pin 2 of current transformer TR1, pin 1 of current transformer TR1 and pin 2 of transformer T200 are connected to voltage control circuit, the voltage control circuit is connected to control chip U2, pin 3 of current transformer TR1 is connected to port 6020, and pin 4 of current transformer TR1 is connected to port 6018; The port 6018 is connected to pin 1 of the BAV99 diode D10, the pin 2 of the BAV99 diode D10 is connected to one end of the resistor R91, one end of the resistor R401 and pin 2 of the BAV99 diode D12, the pin 3 of the BAV99 diode D10 is connected to pin 3 of the BAV99 diode D12 and port AGND, the port 6020 is connected to pin 1 of the BAV99 diode D12, the other end of the resistor R91 is connected to port LIMIT1, one end of the resistor R29, the other end of the resistor R401 and the resistor The positive end of the diode D14 is connected to one end of the resistor R68, the other end of the resistor R29 is connected to the other end of the resistor R68, one end of the resistor R180, one end of the resistor R92, one end of the capacitor C47 and the positive end of the diode D14, the negative end of the diode D14 is connected to one end of the capacitor C62 and one end of the resistor R94, the other end of the resistor R94 is connected to the port ILIMT, the other end of the resistor R180, the other end of the resistor R92, the other end of the capacitor C47 and the other end of the capacitor C62 are connected to the port AGND, and the port ILIMT is connected to the control chip U2; The port LIMIT1 is connected to the negative end of the voltage regulator tube Z7, the positive end of the voltage regulator tube Z7 is connected to one end of the resistor R202, the other end of the resistor R202 is connected to one end of the capacitor C159, one end of the resistor R221, one end of the resistor R201 and one end of the resistor R220, the other end of the capacitor C159 is connected to the other end of the resistor R201, one end of the capacitor C160, one end of the resistor R222 and the port AGND, the other end of the resistor R220 is connected to one end of the capacitor C158 and the pin 6 of the operational amplifier U11, the other end of the capacitor C160 is connected to the other end of the capacitor C158, the pin 5 of the operational amplifier U11, one end of the resistor R200, the other end of the resistor R222 and one end of the resistor R204, the other end of the resistor R204 is connected to the port +5VS, the other end of the resistor R200 is connected to the pin 7 of the operational amplifier U11 and one end of the resistor R206, the port +5VS VS is connected to one end of resistor R194, the other end of the resistor R194 is connected to one end of capacitor C153, one end of resistor R191, one end of capacitor C124 and pin 2 of the operational amplifier U11, the other end of the capacitor C153 and the other end of the resistor R191 are connected to port AGND, the other end of the capacitor C124 is connected to the other end of the resistor R221, pin 3 of the operational amplifier U11 and one end of resistor R192, the other end of the resistor R192 and pin 1 of the operational amplifier U11 are connected to the positive end of diode D15, the negative end of diode D15 is connected to the other end of resistor R206 and pin 1 of BAV70 diode D11, pin 2 of BAV70 diode is connected to one end of resistor R195, pin 3 of BAV70 diode is connected to one end of resistor R190, the other end of resistor R195 and the other end of resistor R190 are connected to port ILIMT.

2. A circuit for realizing overload transient according to claim 1, characterized in that: The port +12VT is connected to the load device.

3. A circuit for realizing overload transient state according to claim 2, characterized in that: The load device includes one or more of a graphics card, a CPU, a GPU, a display and a hard disk.

4. A circuit for realizing overload transient according to claim 1, characterized in that: The +5VS port is connected to the power supply.

5. A circuit for realizing overload transient according to claim 1, characterized in that: The operational amplifier U11 is LM2904DGKR.

6. A circuit for realizing overload transient state according to claim 1, characterized in that: The voltage control circuit includes a port VCCB, wherein the port VCCB is connected to the positive end of a diode D37, the negative end of the diode D37 is connected to one end of a capacitor C16 and the collector of a transistor Q44, the base of the transistor Q44 is connected to the base of a transistor Q46 and the port HG, the emitter of the transistor Q44 is connected to the emitter of the transistor Q46, one end of a resistor R209 and the negative end of a diode D3, the positive end of the diode D3 is connected to one end of a resistor R93, and the other end of the resistor R209 is connected to the resistor The other end of R93, one end of the resistor R205, one end of the bidirectional voltage regulator Z10 and the gate of the MOS transistor Q8, the drain of the MOS transistor Q8 is connected to the port +VDC and one end of the capacitor C217, the other end of the capacitor C16, the collector of the transistor Q46, the other end of the resistor R205, the other end of the bidirectional voltage regulator Z10, the source of the MOS transistor Q8, the other end of the capacitor C217, the drain of the MOS transistor Q9 and one end of the capacitor C223 are connected to the pin 1 of the current transformer TR1; The port VCCB is connected to one end of the capacitor C189 and the collector of the transistor Q45, the base of the transistor Q45 is connected to the base of the transistor Q47 and the port LG, the emitter of the transistor Q45 is connected to the emitter of the transistor Q47, one end of the resistor R35 and the negative end of the diode D5, the positive end of the diode D5 is connected to one end of the resistor R145, the other end of the resistor R35 is connected to the other end of the resistor R145, one end of the resistor R235, one end of the bidirectional voltage regulator Z11 and the gate of the MOS tube Q9, and the The other end of capacitor C189, the collector of the transistor Q47, the other end of the bidirectional voltage regulator Z11, the other end of the resistor R235, the source of the MOS tube Q9, the other end of the capacitor C223, one end of the capacitor C218, one end of the capacitor C14 and one end of the capacitor C201 are connected to port GND, the other end of the capacitor C218, the other end of the capacitor C14 and the other end of the capacitor C201 are connected to pin 2 of the transformer T200, and the port HG and the port LG are connected to the control chip U2.

7. A circuit for realizing overload transient state according to claim 1, characterized in that: Pin 1 of the control chip U2 is connected to port VREF1, one end of resistor R9, one end of resistor R80 and one end of capacitor C26; pin 2 of the control chip U2 is connected to the other end of resistor R9 and one end of resistor R8; the other end of resistor R8 is connected to port AGND; pin 3 of the control chip U2 is connected to one end of resistor R86, one end of resistor R20, one end of capacitor C31, one end of resistor R16, one end of resistor R11 and one end of capacitor C67; the other end of capacitor C31 is connected to one end of resistor R21; the other end of resistor R21 is connected to one end of resistor R259, the other end of resistor R20, the other end of resistor R86 and one end of resistor R109; the other end of resistor R259 is connected to port +12VS; The other end of the resistor R109 is connected to the port +12VT, the pin 4 of the control chip U2 is connected to one end of the capacitor C145 and one end of the resistor R81, the other end of the resistor R81 is connected to one end of the capacitor C28, the pin 5 of the control chip U2 is connected to the other end of the resistor R80, one end of the capacitor C25, one end of the resistor R71 and one end of the resistor R60, the other end of the resistor R60 is connected to one end of the capacitor C97, the other end of the resistor R16, the other end of the resistor R11, the other end of the capacitor C67, the other end of the capacitor C145, the other end of the capacitor C28, the other end of the capacitor C26, the other end of the capacitor C25, the other end of the resistor R71 and the other end of the capacitor C97 are connected to the port AGND; Pin 7 of the control chip U2 is connected to one end of the resistor R23, the other end of the resistor R23 is connected to one end of the capacitor C61, pin 8 of the control chip U2 is connected to port ILIMT, one end of the resistor R82, one end of the capacitor C29 and one end of the resistor R402, the other end of the resistor R82 is connected to the negative end of the diode D9, the positive end of the diode D9 is connected to port VREF1 and one end of the resistor R83, pin 9 of the control chip U2 is connected to the other end of the resistor R83 and one end of the capacitor C30, pin 10 of the control chip U2, one end of the capacitor C37, one end of the capacitor C85, the other end of the capacitor C30, the other end of the capacitor C29, the other end of the resistor R402 and the other end of the capacitor C61 are connected to port AGND; Pin 13 of the control chip U2 is connected to port LG, pin 14 of the control chip U2 is connected to port HG, port LG and port HG are connected to the voltage control circuit, and pin 15 of the control chip U2 is connected to pin 16 of the control chip U2, the other end of the capacitor C37, the other end of the capacitor C85 and port VDD.

8. A circuit for realizing overload transient state according to claim 7, characterized in that: The port +12VS and the port +12VT are connected to a load device.

9. A circuit for realizing overload transient state according to claim 7, characterized in that: The port VDD is connected to a power source.

10. The circuit for realizing overload transient state according to claim 7, characterized in that: The model of the control chip U2 is CU6901VACISTR.

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