Large capacitive load power-up buffer circuit

Abstract

The utility model relates to the technical field of power-up buffer circuits, in particular to a large capacitive load power-up buffer circuit, which comprises a reverse protection diode controller, an input detection end of the reverse protection diode controller is respectively connected with a Vin input end and a drain electrode of a metal oxide semiconductor (MOS) tube Q1, and the input detection end of the reverse protection diode controller is connected with an output end of the MOS tube Q1. The source electrode of the MOS tube Q1 is connected with the source electrode of the MOS tube Q2 and the source connection end of the reverse protection diode controller, the drain electrode of the MOS tube Q2 is connected with one end of the capacitor C4, the Vout output end, one end of the resistor R4 and the output detection end of the reverse protection diode controller, and the other end of the resistor R4 is connected with one end of the capacitor C2. According to the utility model, the problem of surge current in the power-up process of the large capacitive load is effectively solved, and the circuit uses the backward diode controller to accurately regulate and control the on and off states of the MOS tube, so that the current impact at the moment of starting is successfully limited, and the safety of the circuit is remarkably improved.

Description

Technical Field

[0001] The utility model relates to the technical field of power-on buffer circuits, in particular to a large capacitive load power-on buffer circuit. Background Art

[0002] In modern electronic devices and circuits, large capacitive loads are widely used in various applications including power management, motor control, communication systems, computer hardware, etc. When there is a large capacitive load in the circuit, especially at the moment of power-on, especially when the power is first connected or reconnected, the large capacitive load needs to be charged to enter the working state. This process often generates a huge current peak, which is the starting surge current.

[0003] The surge current generated often exceeds the rated current range that the circuit components and power supply system can withstand. The surge current will cause the power supply voltage to drop instantly, which in turn will cause abnormal operation of other components in the circuit and even seriously affect the stability of the entire device. Utility Model Content

[0004] The utility model proposes a large capacitive load power-on buffer circuit to solve the problem that when a large capacitive load exists in a circuit, a large surge current is generated when the large capacitive load needs to be charged at the moment of power-on startup, so that the circuit cannot work normally.

[0005] The utility model is realized by the following technical solutions:

[0006] A large capacitive load power-up buffer circuit comprises a reverse protection diode controller, wherein an input detection end of the reverse protection diode controller is respectively connected to a Vin input end and a drain of a MOS tube Q1, a source of the MOS tube Q1 is respectively connected to a source of a MOS tube Q2 and a source connection end of the reverse protection diode controller, a drain of the MOS tube Q2 is respectively connected to one end of a capacitor C4, a Vout output end, one end of a resistor R4, and an output detection end of the reverse protection diode controller, the other end of the resistor R4 is respectively connected to one end of a capacitor C2 and one end of a capacitor C2, the other end of the capacitor C2 is respectively connected to a ground end of the reverse protection diode controller and one end of a resistor R1, and the other end of the resistor R1 is grounded; a gate of the MOS tube Q2 is respectively connected to a gate drive output end of the reverse protection diode controller and one end of a resistor R3, and the other end of the resistor R3 is connected to the gate of the MOS tube Q1.

[0007] Furthermore, the drain of the MOS tube Q2 is connected to one end of the capacitor C1, one end of the capacitor C5, and one end of the capacitor C6. The other end of the capacitor C4 is respectively connected to the other end of the capacitor C5. The other end of the capacitor C6 is then grounded. The other end of the capacitor C1 is grounded.

[0008] Furthermore, the gate of the MOS transistor Q1 is connected to one end of a resistor R2, the other end of the resistor R2 is connected to one end of a capacitor C3, and the other end of the capacitor C3 is grounded.

[0009] Furthermore, the input detection end of the reverse protection diode controller is connected to one end of the bidirectional breakdown diode D1, and the other end of the bidirectional breakdown diode D1 is connected to one end of the resistor R1.

[0010] Furthermore, the other end of the resistor R4 is connected to the cathode of the voltage-stabilizing diode D2, and the anode of the voltage-stabilizing diode D2 is connected to the other end of the capacitor C2 and one end of the resistor R1 respectively.

[0011] Furthermore, the MOS transistor Q1 and the MOS transistor Q2 are N-channel MOS transistors.

[0012] Furthermore, the capacitance value of capacitor C1 is 10uF, the capacitance value of capacitor C2 is 47nF, and the capacitance value of capacitor C3 is 10nF; capacitor C4, capacitor C5, and capacitor C6 are large capacitive loads, and the capacitance value is 30000μF.

[0013] Furthermore, the resistance value of the resistor R1 is 1 kΩ, the resistance value of the resistor R2 is 10 kΩ, the resistance value of the resistor R3 is 10Ω, and the resistance value of the resistor R4 is 300Ω.

[0014] Beneficial effects of the utility model:

[0015] (1) The utility model proposes a large capacitive load power-on buffer circuit, which effectively solves the surge current problem faced by large capacitive loads during the power-on process. The circuit uses a reverse diode controller to accurately control the on and off states of the MOS tube, thereby successfully limiting the current impact at the startup moment and significantly improving the safety of the circuit;

[0016] (2) The large capacitive load power-on buffer circuit proposed in the utility model not only effectively protects the various components in the circuit from the impact of surge current, but also ensures the stable operation of the power supply system, so that the entire circuit can quickly return to normal working state after power-on. This design not only enhances the stability of the circuit, but also prolongs the service life of the circuit components, providing a more reliable and stable operating environment for various electronic equipment;

[0017] (3) The utility model proposes a large capacitive load power-on buffer circuit which uses relatively simple electronic components and does not need to occupy too much space or consume a lot of energy. Therefore, it can be widely adapted to electronic devices of various sizes and power requirements. This design not only effectively solves the surge current problem generated by large capacitive loads when powered on, but also makes the circuit layout more compact and energy utilization more efficient.

[0018] To sum up, the utility model proposes a large capacitive load power-on buffer circuit which introduces a reverse protection diode controller, which can effectively limit the sharp impact of current at the moment of circuit startup, thereby greatly protecting various components in the circuit and the power supply system. At the same time, the utility model proposes a large capacitive load power-on buffer circuit which introduces a reverse protection diode controller, which can effectively limit the sharp impact of current at the moment of circuit startup, thereby greatly protecting various components in the circuit and the power supply system. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0020] Figure 1 The present invention is a circuit diagram of a large capacitive load power-up buffer circuit proposed in an embodiment of the present invention. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solutions and advantages of the utility model more clearly understood, the utility model is further described in detail below in conjunction with embodiments and drawings. The schematic implementation manner of the utility model and its description are only used to explain the utility model and are not intended to limit the utility model.

[0022] Example 1

[0023] This embodiment provides a specific implementation of a large capacitive load power-up buffer circuit.

[0024] refer to Figure 1A large capacitive load power-on buffer circuit includes a reverse protection diode controller, the model of the reverse protection diode controller is LT4359I, the input detection end of the reverse protection diode controller is respectively connected to the Vin input end and the drain of the MOS tube Q1, through which the reverse protection diode controller can compare the voltage difference between Vin and the drain of the MOS tube Q1, thereby deciding whether to turn on or off the MOS tube Q1 and the MOS tube Q2. If the input voltage Vin is negative or reversely connected, when the reverse protection diode controller detects an abnormal voltage difference, it will not drive the MOS tubes Q1 and Q2 to conduct, thereby protecting the circuit components from reverse current damage. This design ensures that when the power polarity is wrong, the current will not flow into the subsequent circuit through Q1 and Q2, effectively protecting the large capacitive load capacitor C4 in the circuit. When powered on normally, the reverse protection diode controller determines to provide a high level or low level signal to the gate of the MOS tubes Q1 and Q2 by detecting the input voltage Vin and the drain voltage of Q1. In the initial stage, due to the large voltage difference, the controller provides a low level signal to the gates of Q1 and Q2 to make them non-conductive and prevent large current impact. When the voltage difference decreases to a certain extent (after the slow charging stage is completed), the controller provides a high-level signal to the gates of Q1 and Q2 to turn them on and allow current to pass directly. This connection method ensures that the current in the circuit is controlled at the beginning of power-on and will not directly enter the large capacitive load through the MOS tubes Q1 and Q2. When the slow charging is completed, the controller will turn on Q1 and Q2 only when the output voltage and input voltage are close to the same as detected by the detection terminal, ensuring that the load starts safely and stably.

[0025] The source of the MOS tube Q1 is respectively connected to the source of the MOS tube Q2 and the source connection end of the reverse protection diode controller, and the drain of the MOS tube Q2 is respectively connected to one end of the capacitor C4, the Vout output end, one end of the resistor R4, and the output detection end of the reverse protection diode controller. This connection method makes the source voltages of the two MOS tubes Q1 and Q2 consistent, which is convenient for control and protection. The reverse protection diode controller can monitor and control the source voltages of the two to ensure that there is no excessive voltage difference when the power is powered on. The drain of MOS tube Q2 is connected to capacitor C4, Vout output terminal, resistor R4 and output detection terminal of reverse protection diode controller. The reverse protection diode controller can detect the voltage of output terminal Vout in real time. The output detection terminal feeds back the current output voltage value to the controller. The controller determines whether to adjust or turn on the MOS tube according to the detected voltage value. Resistor R4 is connected between the drain of Q2 and the output detection terminal of reverse protection diode controller. The existence of R4 limits the rising speed of current, ensuring that the current will not flow into the large capacitive load quickly at the beginning of power-on, causing current shock. Therefore, the circuit can be charged slowly through R4 at the beginning of power-on to protect the circuit and load. When the slow charging process is completed, the output voltage (Vout) rises to close to the input voltage (Vin). The reverse protection diode controller detects that the output and input voltage difference is small, thereby driving the gate of MOS tubes Q1 and Q2 to a high level, making them conductive. Once MOS tubes Q1 and Q2 are conductive, the power supply voltage Vin flows directly through these two MOS tubes into the large capacitive load capacitor C4, ensuring that the load can be powered stably.

[0026] The other end of the resistor R4 is connected to one end of the capacitor C2 and one end of the capacitor C2, and the other end of the capacitor C2 is respectively connected to the ground end of the reverse protection diode controller and one end of the resistor R1, and the other end of the resistor R1 is grounded; the gate of the MOS tube Q2 is respectively connected to the gate drive output end of the reverse protection diode controller and one end of the resistor R3, and the other end of the resistor R3 is connected to the gate of the MOS tube Q1, wherein the resistor C2 can smooth the voltage fluctuation, filter out the high-frequency noise in the power supply, and provide a stable voltage to the subsequent circuit. One end of R1 is connected to the capacitor C2, and the other end is grounded. Therefore, the resistor R1 forms an RC filter by cooperating with the capacitor C2 to further smooth the voltage fluctuation and stabilize the working voltage of the circuit. In addition, in this embodiment, the resistor R1 also plays a role in current limiting to prevent the current in the circuit from being too large and protect the circuit components. The resistor R3 is connected to the gates of the MOS tubes Q2 and Q1 to distribute and adjust the gate drive signal. The resistor R3 ensures that the gate drive signal can be correctly distributed to the gates of Q1 and Q2 by limiting the current, so as to avoid excessive drive current affecting the normal operation of the MOS tube.

[0027] The large capacitive load in this embodiment also includes capacitor C5 and capacitor C6. The main purpose of setting multiple large capacitive capacitors in a circuit is to cope with different power supply requirements and current smoothness requirements. Each capacitor may have different functions. The drain of the MOS tube Q2 is connected to one end of the capacitor C1, one end of the capacitor C5, and one end of the capacitor C6. The other end of the capacitor C4 is respectively connected to the other end of the capacitor C5. The other end of the capacitor C6 is then grounded, and the other end of the capacitor C1 is grounded.

[0028] The gate of the MOS tube Q1 is connected to one end of the resistor R2, the other end of the resistor R2 is connected to one end of the capacitor C3, and the other end of the capacitor C3 is grounded. The resistor R2 is connected between the gate of the MOS tube Q1 and the capacitor C3, and is used to stabilize the gate voltage. The resistor R2 limits the magnitude of the gate drive current to prevent the gate voltage from changing too quickly. The capacitor C3 is connected between R2 and the ground for filtering and decoupling. The capacitor C3 can filter out high-frequency noise in the gate drive signal and provide a smoother and more stable gate voltage.

[0029] The decoupling effect of the capacitor C3 helps to eliminate high-frequency interference signals generated by the power line or other circuit parts, thereby ensuring the stable operation of the MOS tube Q1. The resistor R2 and the capacitor C3 together form an RC network with a certain time constant. The RC network can control the rise and fall time of the gate voltage, so that the MOS tube Q1 is smoother when switching, reducing switching losses and electromagnetic interference. In this embodiment, the switching speed and performance of the MOS tube Q1 can be optimized by adjusting the parameters of R2 and C3 to meet specific circuit requirements.

[0030] The input detection end of the reverse protection diode controller is connected to one end of the bidirectional breakdown diode D1, and the other end of the bidirectional breakdown diode D1 is connected to one end of the resistor R1. When the voltage of the power input end Vin exceeds the breakdown voltage of the bidirectional breakdown diode D1, the bidirectional breakdown diode D1 will be turned on immediately. By turning on the bidirectional breakdown diode D1, the excessive voltage is clamped at a safe voltage level, thereby protecting subsequent circuit components including the reverse protection diode controller, MOS tubes Q1 and Q2 from overvoltage damage. The bidirectional breakdown diode D1 can be turned on when both the forward and reverse voltages exceed its breakdown voltage, which can ensure that when the input voltage Vin is reversely connected or negative voltage occurs, the circuit can still be effectively protected to prevent the reverse voltage from damaging the circuit components. In addition, the bidirectional breakdown diode D1 in this embodiment can suppress the sudden transient high voltage (such as transient pulses caused by lightning strikes and power switches) on the power line. By suppressing these transient high voltages, the bidirectional breakdown diode D1 protects the circuit components from transient voltage shocks, prolongs the service life of the circuit, and improves the reliability of the system.

[0031] The other end of the resistor R4 is connected to the cathode of the voltage-stabilizing diode D2, and the anode of the voltage-stabilizing diode D2 is respectively connected to the other end of the capacitor C2 and one end of the resistor R1. The voltage-stabilizing diode D2 plays a voltage-stabilizing role in the circuit through its stable breakdown voltage. When the voltage in the circuit reaches the breakdown voltage of the voltage-stabilizing diode D2, the voltage-stabilizing diode D2 starts to conduct and clamps the voltage near its breakdown voltage value, providing a stable voltage reference. When the voltage in the circuit exceeds the breakdown voltage of the voltage-stabilizing diode D2, the voltage-stabilizing diode D2 will conduct and clamp the voltage within a safe range to prevent excessive voltage from causing damage to circuit components. Through this clamping effect, the voltage-stabilizing diode D2 protects subsequent circuits from overvoltage and ensures stable operation of the circuit.

[0032] In this embodiment, the voltage stabilizing diode D2 can filter out high-frequency noise and voltage spikes in the power supply, and provide a more stable voltage output. By suppressing these voltage fluctuations, D2 improves the anti-interference ability and reliability of the circuit.

[0033] Example 2

[0034] This embodiment proposes a functional principle of a large capacitive load power-up buffer circuit based on the first embodiment.

[0035] A large capacitive load power-on buffer circuit is designed to provide a smooth power-on process for large capacitive loads, namely, capacitors C4, C5, and C6 in this embodiment, by controlling and slowly charging, so as to avoid the impact of instantaneous large current on the circuit. The circuit is mainly composed of a reverse protection diode controller, an N-channel MOS tube, a bidirectional breakdown diode, a voltage regulator diode, and related resistors and capacitors. The specific working principle of the circuit is as follows:

[0036] The circuit is powered on. When power is applied from IN (power input terminal), initially, the drain and source of N-channel MOS tubes Q1 and Q2 are not conducting. Since the voltage difference between the input and output terminals of the reverse protection diode controller is too large, its gate drive output gives a low level to the gates of Q1 and Q2. Therefore, the current cannot directly pass through MOS tubes Q1 and Q2 into the large capacitive load capacitors C4, C5, and C6.

[0037] Slow charging. At the beginning of slow charging, a voltage difference is generated at both ends of the bidirectional breakdown diode, making it conduct. The current in the circuit passes through the resistor R1, part of it flows to the Zener diode D2, and the other part flows to the ground. When a certain voltage difference is generated at both ends of the Zener diode D2, the Zener diode D2 is conducted and the current flows to the output end.

[0038] At this point the current gradually begins to charge the large capacitive load, which is a slow process because resistor R4 limits the rate of current rise.

[0039] The N-channel MOS tube is turned on. When the large capacitive load capacitors C4, C5, and C6 are charged, the voltage at the output end rises to almost the same as the voltage at the input end. At this time, the input detection and output detection voltages of the reverse protection diode controller are also almost the same. The gate drive of the controller outputs a high level to the gates of the N-channel MOS tubes Q1 and Q2, turning them on.

[0040] The current flows into the large capacitive load. When the MOS tubes Q1 and Q2 are turned on, a path is formed between the input voltage terminal and the output voltage terminal. At this time, the circuit of D1 and D2 in series is open, and the current can directly pass through the drain and source of the two N-channel MOS tubes. The current is directly input into the large capacitive load capacitors C4, C5, and C6, and the power-on buffer startup is completed. Through the above working principle, the circuit realizes the smooth power-on of the large capacitive load, avoids the impact of instantaneous large current on the circuit components, and provides effective overvoltage protection and voltage stabilization functions to ensure the stability and reliability of the circuit.

[0041] The above shows and describes the basic principle and main features of the utility model and the advantages of the utility model. Those skilled in the art should understand that the utility model is not limited by the above embodiments. The above embodiments and descriptions are only for explaining the principle of the utility model. Without departing from the spirit and scope of the utility model, the utility model may have various changes and improvements, which fall within the scope of the utility model to be protected. The scope of protection claimed by the utility model is defined by the attached claims and their equivalents.

Claims

1. A large capacitive load power-up buffer circuit, characterized in that: It comprises a reverse protection diode controller, wherein the input detection end of the reverse protection diode controller is respectively connected to the Vin input end and the drain of the MOS tube Q1, the source of the MOS tube Q1 is respectively connected to the source of the MOS tube Q2 and the source connection end of the reverse protection diode controller, the drain of the MOS tube Q2 is respectively connected to one end of the capacitor C4, the Vout output end, one end of the resistor R4, and the output detection end of the reverse protection diode controller, the other end of the resistor R4 is connected to one end of the capacitor C2 and one end of the capacitor C2, the other end of the capacitor C2 is respectively connected to the ground end of the reverse protection diode controller and one end of the resistor R1, and the other end of the resistor R1 is grounded; the gate of the MOS tube Q2 is respectively connected to the gate drive output end of the reverse protection diode controller and one end of the resistor R3, and the other end of the resistor R3 is connected to the gate of the MOS tube Q1.

2. A large capacitive load power-up buffer circuit according to claim 1, characterized in that: The drain of the MOS tube Q2 is connected to one end of the capacitor C1, one end of the capacitor C5, and one end of the capacitor C6. The other end of the capacitor C4 is connected to the other end of the capacitor C5. The other end of the capacitor C6 is grounded. The other end of the capacitor C1 is grounded.

3. A large capacitive load power-up buffer circuit according to claim 2, characterized in that: The gate of the MOS transistor Q1 is connected to one end of a resistor R2, the other end of the resistor R2 is connected to one end of a capacitor C3, and the other end of the capacitor C3 is grounded.

4. A large capacitive load power-up buffer circuit according to claim 3, characterized in that: The input detection end of the reverse protection diode controller is connected to one end of the bidirectional breakdown diode D1, and the other end of the bidirectional breakdown diode D1 is connected to one end of the resistor R1.

5. A large capacitive load power-up buffer circuit according to claim 4, characterized in that: The other end of the resistor R4 is connected to the cathode of the voltage stabilizing diode D2, and the anode of the voltage stabilizing diode D2 is connected to the other end of the capacitor C2 and one end of the resistor R1 respectively.

6. A large capacitive load power-up buffer circuit according to claim 5, characterized in that: The MOS transistor Q1 and the MOS transistor Q2 are N-channel MOS transistors.

7. A large capacitive load power-up buffer circuit according to claim 6, characterized in that: The capacitance value of capacitor C1 is 10uF, the capacitance value of capacitor C2 is 47nF, and the capacitance value of capacitor C3 is 10nF; capacitor C4, capacitor C5, and capacitor C6 are large capacitive loads, and the capacitance value is 30000μF.

8. A large capacitive load power-up buffer circuit according to claim 6, characterized in that: The resistance value of the resistor R1 is 1 kΩ, the resistance value of the resistor R2 is 10 kΩ, the resistance value of the resistor R3 is 10Ω, and the resistance value of the resistor R4 is 300Ω.

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