Groove type semiconductor bridge chip

Abstract

The utility model discloses a groove type semiconductor bridge chip, and belongs to the technical field of initiating explosive devices. The semiconductor bridge chip comprises an N-type silicon substrate, a silicon dioxide layer, a front pattern polycrystalline silicon layer and a front pattern metal electrode layer. The silicon dioxide layer is located on the upper surface of the N-type silicon substrate, the front pattern polycrystalline silicon layer is located on the upper surface of the silicon dioxide layer, the front pattern metal electrode layer is located on the upper surface of the front pattern polycrystalline silicon layer, V-shaped notches are formed in the two side edges of the polycrystalline silicon bridge region, and honeycomb groove structures are manufactured in the regions, except the V-shaped notches, of the two side edges of the bridge region. After electrification, the current density of the V-shaped gap and the honeycomb groove structure is greatly improved, Joule heat is quickly formed, and plasma discharge is quickly formed. The problems that the ignition time and the ignition energy of the semiconductor bridge initiating explosive device are difficult to further reduce, and the accuracy and the rapidness of a semiconductor bridge initiating explosive device system are difficult to improve are solved. The semiconductor bridge chip is widely applied to the technical field of SCB initiating explosive device semiconductor bridge chips.

Description

Technical Field

[0001] The utility model belongs to the technical field of pyrotechnics, and further relates to the technical field of semiconductor bridge pyrotechnics, and specifically relates to a groove-type semiconductor bridge chip. Background Art

[0002] Initiators are components or devices that provide ignition, detonation or power sources. They are the first and most sensitive components in weapons and ammunition, rockets, satellites, spacecraft, pilot life-saving, civil engineering blasting, gunpowder power and other devices. In recent years, with the development of science and technology, the requirements for the precision, accuracy and consistency of blasting and explosive ignition have become increasingly higher. The development of ammunition systems and the strengthening of the harshness of the electromagnetic environment require that the ignition system has the ability to resist static electricity, electromagnetic radiation, power supply transients, stray currents and lightning, and the ignition system should have good electromagnetic compatibility with other systems. Modern aerospace technology requires that initiators have the following characteristics: high anti-interference, including anti-electromagnetic interference, anti-mechanical stress and high safety insensitivity; low ignition energy and fast ignition; low-cost mass production with good consistency; miniaturization and intelligence of ignition devices. Traditional initiators can no longer meet these requirements, and it is necessary to study and develop advanced initiator technologies. Semiconductor Bridge (SCB) pyrotechnics is a high-tech pyrotechnic product that has been developed at home and abroad in recent years and is a typical representative of modern advanced pyrotechnic products.

[0003] The mechanism of action of SCB explosives is different from the heat conduction mechanism of traditional bridgewire explosives. It is generally believed to be a micro-convection mechanism. That is, when a pulse current is passed through the SCB, the silicon bridge material is rapidly vaporized due to Joule heat and forms a 4100K~6000K plasma discharge under the action of the electric field. This high-temperature, high-pressure fluid quickly diffuses into the explosive, causing the explosive to heat up to the ignition temperature and ignite. In addition, the shock wave generated by the rapid diffusion of the plasma also acts on the explosive.

[0004] When current passes through SCB, energy is dissipated through many channels and methods, mainly heat conduction from the bridge to the substrate; consumption of heating bridge materials; melting heat and vaporization heat of bridge materials; thermal radiation; circuit losses outside the bridge. The distribution of these energies depends on the electrical characteristics of the ignition device and the geometric shape and structure of the bridge. At present, the bridge area structure of semiconductor bridge chips is long and narrow, and it is difficult to reduce the ignition time and ignition energy. For semiconductor bridge pyrotechnics used in smart or intelligent weapons, satellites, ammunition, civilian anti-collision airbags and blasting engineering, the requirements for ignition time and ignition energy are extremely high. Having faster ignition time and lower ignition energy is a new development direction for semiconductor bridge pyrotechnics. At present, the ignition time and ignition energy of the bridge area structure of semiconductor bridge chips are difficult to reduce.

[0005] Therefore, a semiconductor bridge chip with a new bridge region structure is urgently needed to solve the above problems.

[0006] The purpose of the utility model is to provide a semiconductor bridge chip and its preparation method with faster ignition time and lower ignition energy, which can greatly improve the ignition time and ignition energy of the semiconductor bridge, realize the accuracy and rapidity of the semiconductor bridge pyrotechnics, and realize micro-difference blasting.

[0007] In view of this, the present utility model is proposed. Summary of the invention

[0008] The technical problem to be solved by the utility model is: to solve the problem that the ignition time of the existing semiconductor bridge pyrotechnics is difficult to be further faster and the ignition energy is difficult to be further lower, and it is difficult to improve the accuracy and rapidity of the semiconductor bridge pyrotechnics system.

[0009] The inventive concept of the utility model is: V-shaped notches are made on both sides of the bridge area, and honeycomb groove structures are made in the areas other than the V-shaped notches on both sides of the bridge area, so that the current density at the V-shaped notches and the honeycomb groove structure is greatly improved after power is turned on, Joule heat is quickly formed here, the temperature rises rapidly, the ignition energy is small, and the vaporization point is quickly formed to form plasma discharge. Therefore, the ignition time and ignition energy of the semiconductor bridge chip are reduced.

[0010] To this end, the utility model provides a trench-type semiconductor bridge chip, such as Figure 1-2 As shown. The chip structure includes:

[0011] N-type silicon substrate 1, silicon dioxide layer 2, front pattern polysilicon layer 3, front pattern metal electrode layer 4.

[0012] A silicon dioxide layer 2 is formed on the N-type silicon substrate 1 .

[0013] A front pattern polysilicon layer is formed on the silicon dioxide layer 2.

[0014] A front pattern metal electrode layer 4 is formed on the front pattern polysilicon layer 3.

[0015] The thickness of the silicon dioxide layer 2 is 2000 angstroms to 20000 angstroms.

[0016] The thickness of the front pattern polysilicon layer 3 is 10000 angstroms to 50000 angstroms.

[0017] The thickness of the front pattern metal electrode layer 4 is 10000 angstroms to 50000 angstroms.

[0018] V-shaped notches are made on both sides of the polysilicon bridge area, and honeycomb groove structures are made in the areas outside the V-shaped notches on both sides of the bridge area.

[0019] The utility model provides a method for preparing a groove-type semiconductor bridge chip, which comprises the following steps:

[0020] (1) growing a silicon dioxide layer (2000 angstroms to 20000 angstroms) on the N-type silicon substrate;

[0021] (2) forming a polysilicon layer (10,000 angstroms to 50,000 angstroms) on the silicon dioxide layer;

[0022] (3) heavily doping the polysilicon layer;

[0023] (4) forming a polysilicon bridge region and a bridge region groove on the polysilicon layer;

[0024] (5) forming an ultra-thick metal layer (10,000 angstroms to 50,000 angstroms) on the polysilicon bridge region;

[0025] (6) making the metal layer into a semiconductor bridge chip electrode;

[0026] (7) performing annealing to form an ohmic contact between the metal layer and silicon (metal-silicon ohmic contact layer);

[0027] (8) The wafer is diced to form individual semiconductor bridge chips.

[0028] For semiconductor bridge pyrotechnics, lower ignition voltage and faster ignition time are important manifestations of better performance of semiconductor bridge pyrotechnics.

[0029] The bridge area structure of the V-shaped notch + honeycomb groove structure provided by the utility model has a greater edge effect than other semiconductor bridge products, and the ignition time and ignition energy of the product are greatly improved; at the same time, during the charging period, the groove provides more area for the explosive contact, and the product reliability is greatly improved.

[0030] Therefore, the semiconductor bridge chip with a V-shaped notch + honeycomb groove structure has a better edge effect, the ignition time required for the semiconductor bridge area is faster, and the ignition energy is lower; at the same time, the honeycomb groove structure on the surface of the bridge area also greatly widens the contact area with the explosive, and the ignition reliability has been steadily improved.

[0031] The beneficial effects of the utility model are:

[0032] Due to the adoption of the semiconductor bridge chip with a bridge area structure of V-shaped notch + honeycomb groove structure, the performance and reliability of semiconductor bridge products have been greatly improved, providing a new direction for the development of semiconductor bridge chips with lower ignition time, lower ignition energy and greater reliability.

[0033] The technical solution of the utility model can be widely used in the technical field of SCB pyrotechnic semiconductor bridge chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a schematic diagram of the longitudinal structure of a semiconductor bridge chip with a V-shaped + honeycomb groove bridge area structure.

[0035] Figure 2 This is a schematic diagram of the structure of the polysilicon trench bridge area.

[0036] In the figure: 1 is an N-type silicon substrate, 2 is a silicon dioxide layer, 3 is a front pattern polysilicon layer, and 4 is a front pattern metal electrode layer. DETAILED DESCRIPTION

[0037] like Figure 1-2 As shown, the trench-type semiconductor bridge chip is specifically implemented as follows:

[0038] The N-type silicon substrate 1 is single crystal silicon, with a thickness of 500±25 μm and a resistivity of (55-65) ohm.cm.

[0039] The V-shaped notches are single V-shaped, double V-shaped or multiple V-shaped (at least 3), and are symmetrically distributed on both sides of the bridge area.

[0040] The honeycomb grooves are circular, elliptical, groove-shaped or other grooves, and are distributed in the bridge area.

[0041] The silicon dioxide layer is grown on an N-type silicon substrate by thermal oxidation. The thickness of the silicon dioxide layer 2 is 12000 angstroms.

[0042] The polysilicon layer is deposited on the silicon dioxide layer by LPCVD or PECVD. The thickness of the polysilicon layer 3 is 25000 angstroms.

[0043] The heavy doping is to heavily dope the polysilicon layer with phosphorus. The doping concentration of the heavily doped phosphorus is 5E20.

[0044] The polysilicon bridge region and the bridge region groove are formed by etching the polysilicon bridge region and the bridge region groove on the polysilicon layer through a photolithography process.

[0045] The metal layer is a gold layer, which is formed on the polysilicon bridge region by evaporation or sputtering process (gold electrode layer). The thickness of the gold electrode layer 4 is 40000 angstroms.

[0046] The semiconductor bridge chip electrode is formed by photolithography of an ultra-thick gold layer through a photolithography process.

[0047] The metal layer-silicon ohmic contact is formed by an annealing process.

[0048] The scribing is laser scribing, grinding wheel scribing or diamond knife scribing.

[0049] Finally, it should be noted that the above embodiments are only examples for clear explanation. The present utility model includes but is not limited to the above embodiments. It is not necessary and impossible to list all implementation methods here. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made on the basis of the above description. All implementation methods that meet the requirements of the present utility model belong to the protection scope of the present utility model.

Claims

1. A trench-type semiconductor bridge chip, characterized in that ,The chip structure includes: N-type silicon substrate, silicon dioxide layer, front pattern polysilicon layer, front pattern metal electrode layer; The silicon dioxide layer is located on the upper surface of the N-type silicon substrate; The front pattern polysilicon layer is located on the upper surface of the silicon dioxide layer; The front pattern metal electrode layer is located at two ends of the upper surface of the front pattern polysilicon layer; The front pattern polysilicon layer between the front pattern metal electrode layers is a polysilicon bridge area, V-shaped notches are made on both sides of the polysilicon bridge area, and honeycomb groove structures are made on both sides of the bridge area except the V-shaped notches.

2. A trench-type semiconductor bridge chip as claimed in claim 1, characterized in that: The thickness of the N-type silicon substrate 1 is 500±25 μm.

3. A trench-type semiconductor bridge chip as claimed in claim 1, characterized in that: The V-shaped notches are single V-shaped, double V-shaped, or three or more V-shaped, and are symmetrically distributed on both sides of the bridge area.

4. A trench-type semiconductor bridge chip as claimed in claim 1, characterized in that: The thickness of the silicon dioxide layer is 2000 angstroms to 20000 angstroms.

5. A trench-type semiconductor bridge chip as claimed in claim 4, characterized in that: The thickness of the silicon dioxide layer is 12000 angstroms.

6. A trench-type semiconductor bridge chip as claimed in claim 1, characterized in that: The thickness of the front pattern polysilicon layer is 10000 angstroms to 50000 angstroms.

7. A trench-type semiconductor bridge chip as claimed in claim 6, characterized in that: The thickness of the polysilicon layer is 25000 angstroms.

8. The trench-type semiconductor bridge chip according to claim 1, characterized in that: The thickness of the front pattern metal electrode layer is 10000 angstroms to 50000 angstroms.

9. A trench-type semiconductor bridge chip as claimed in claim 8, characterized in that: The thickness of the front pattern metal electrode layer is 40,000 angstroms.

10. The trench-type semiconductor bridge chip according to claim 1, characterized in that: Between the metal layer and the silicon is a metal-silicon ohmic contact layer.

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