Detection circuit, chip and electronic equipment

Abstract

The utility model provides a detection circuit, a chip and electronic equipment, and belongs to the technical field of electronics. The detection circuit comprises a detection switch array module and a logic gate module, the detection switch array module comprises a plurality of detection switch units, and the plurality of detection switch units are connected in parallel; the first end of the detection switch unit is used for receiving a first voltage, the second end of the detection switch unit is connected with the first end of a target switch unit to be detected in a target circuit, the second end of the detection switch unit is further connected with the input end of the logic gate module, and in the target circuit, the logic gate module is connected with the logic gate module. The second end of the target switch unit is used for receiving a second voltage, and the first voltage and the second voltage are opposite in level; and the output end of the logic gate module is used for outputting a target detection result of the target circuit. According to the invention, whether the switch has a fault can be detected.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a detection circuit, a chip and an electronic device. Background Art

[0002] Capacitors are indispensable in circuit design. In practical applications, capacitor circuits with adjustable capacitance are often used, i.e., adjustable capacitor circuits. For example, in the design of PCB (Printed Circuit Board), it is necessary to consider the need for adjustable capacitance in different applications. For example, when capacitors are integrated into a chip, PVT (Process, Voltage, Temperature) deviation is considered and the capacitance is designed to be adjustable, so an adjustable capacitor circuit is used.

[0003] With the improvement of circuit integration and the complexity of application scenarios, the reliability requirements of circuits are also gradually increasing. In traditional adjustable capacitor circuits, there may be common reliability risks, such as the connection between the capacitor and the plate connected to the switch is broken due to stress or other reasons, or the switch enable signal loses control of the switch and causes the switch to be in an open state. These may cause the capacitance value connected to the circuit to achieve the function to be inconsistent with the design value. For example, the design requires the capacitors connected to the circuit to be capacitors 1 to n, and the line connecting capacitor n to the switch is disconnected due to unexpected reasons, or the switch enable signal of capacitor n loses control of switch n, causing switch n to not close. At this time, capacitor n is not connected to the circuit, and the capacitance value of the adjustable capacitor circuit does not meet the design value.

[0004] If the capacitance value of the adjustable capacitor circuit does not match the design value, it may cause the circuit performance to decline or the function to be lost, causing reliability problems. Therefore, a detection circuit is urgently needed to detect whether there is a fault in the connection of the capacitor. Utility Model Content

[0005] In order to solve the problems of the prior art, the embodiments of the present application provide a detection circuit, a chip and an electronic device, which can detect whether there is a fault in the connection of a capacitor, so as to improve the reliability of the circuit. The technical solution is as follows:

[0006] According to one aspect of the present application, a detection circuit is provided, the detection circuit comprising a detection switch array module and a logic gate module, the detection switch array module comprising a plurality of detection switch units, the plurality of detection switch units being connected in parallel;

[0007] The first end of the detection switch unit is used to receive a first voltage, the second end of the detection switch unit is connected to the first end of the target switch unit to be detected in the target circuit, and the second end of the detection switch unit is also connected to the input end of the logic gate module, wherein in the target circuit, the second end of the target switch unit is used to receive a second voltage, and the first voltage and the second voltage are not equal;

[0008] The output end of the logic gate module is used to output the target detection result of the target circuit.

[0009] According to another aspect of the present application, a chip is provided, comprising the above-mentioned detection circuit.

[0010] According to another aspect of the present application, an electronic device is provided, comprising the above detection circuit.

[0011] In the present application, the detection circuit includes a detection switch array module and a logic gate module, and the detection switch array module includes a plurality of detection switch units. During the test process of the target circuit, whether the target switch unit in the target circuit is faulty is detected based on the second terminal voltage of the detection switch unit, thereby detecting whether the access of the corresponding capacitor unit is faulty, and outputting the target detection result of the target circuit through the logic gate module. The detection circuit provided by the present application has a simple structure, a small scale, and a small area overhead. In addition, the accurate positioning of the target switch unit and the capacitor unit where the fault occurs can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Further details, features and advantages of the present application are disclosed in the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

[0013] Figure 1 A schematic diagram of a detection circuit provided according to an exemplary embodiment of the present application is shown;

[0014] Figure 2 A schematic diagram of a conventional adjustable capacitor circuit provided according to an exemplary embodiment of the present application is shown;

[0015] Figure 3 A switch control schematic diagram provided according to an exemplary embodiment of the present application is shown;

[0016] Figure 4 A schematic diagram of a detection circuit based on an OR gate provided according to an exemplary embodiment of the present application is shown;

[0017] Figure 5 A schematic diagram of a detection circuit based on an AND gate provided according to an exemplary embodiment of the present application is shown;

[0018] Figure 6A schematic diagram of a first logic gate unit based on an OR gate provided according to an exemplary embodiment of the present application is shown;

[0019] Figure 7 A schematic diagram of a first logic gate unit based on an AND gate provided according to an exemplary embodiment of the present application is shown;

[0020] Figure 8 A schematic diagram of a second logic gate unit based on an OR gate provided according to an exemplary embodiment of the present application is shown;

[0021] Fig. 9 A schematic diagram of a second logic gate unit based on an AND gate provided according to an exemplary embodiment of the present application is shown;

[0022] Fig.10 A schematic diagram of a logic gate module provided according to an exemplary embodiment of the present application is shown;

[0023] Fig.11 A schematic diagram of a third logic gate unit based on an OR gate provided according to an exemplary embodiment of the present application is shown;

[0024] Fig.12 A schematic diagram of a third logic gate unit based on an AND gate provided according to an exemplary embodiment of the present application is shown;

[0025] Fig.13 A schematic diagram of a fourth logic gate unit based on an OR gate provided according to an exemplary embodiment of the present application is shown;

[0026] Fig.14 A schematic diagram of a fourth logic gate unit based on an AND gate provided according to an exemplary embodiment of the present application is shown.

[0027] In the figure,

[0028] 1. Detection switch array module; 11. Detection switch unit; 2. Logic gate module; 21. First logic gate unit; 22. Second logic gate unit; 23. Enable control module; 24. Third logic gate unit; 25. Fourth logic gate unit. DETAILED DESCRIPTION

[0029] The embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be construed as being limited to the embodiments described herein. Instead, these embodiments are provided to provide a more thorough and complete understanding of the present application. It should be understood that the drawings and embodiments of the present application are only for exemplary purposes and are not intended to limit the scope of protection of the present application.

[0030] The term "including" and its variations used in this document are open inclusions, that is, "including but not limited to". The term "based on" means "based at least in part on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one other embodiment"; the term "some embodiments" means "at least some embodiments". Relevant definitions of other terms will be given in the description below. It should be noted that the concepts of "first", "second", etc. mentioned in this application are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

[0031] In addition, the "plurality" in the embodiments of the present application refers to two or more than two. In view of this, in the embodiments of the present application, "plurality" can also be understood as "at least two". "At least one" can be understood as one or more, for example, one, two or more. For example, including at least one means including one, two or more, and there is no limit on which ones are included. For example, including at least one of A, B and C, then A, B, C, A and B, A and C, B and C, or A, B and C can be included.

[0032] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0033] The names of the messages or information exchanged between multiple devices in the embodiments of the present application are only used for illustrative purposes and are not used to limit the scope of these messages or information.

[0034] An embodiment of the present application provides a detection circuit. The detection circuit provided by the embodiment can be integrated in a chip or set in an electronic device.

[0035] like Figure 1 The detection circuit schematic diagram shown in the figure, the detection circuit may include a detection switch array module 1 and a logic gate module 2, the detection switch array module 1 may include a plurality of detection switch units 11, and the plurality of detection switch units 11 are connected in parallel;

[0036] The first end of the detection switch unit 11 can be used to receive a first voltage, the second end of the detection switch unit 11 can be connected to the first end of the target switch unit to be detected in the target circuit, and the second end of the detection switch unit 11 is also connected to the input end of the logic gate module 2, wherein in the target circuit, the second end of the target switch unit is used to receive a second voltage, and the first voltage and the second voltage are not equal;

[0037] The output end of the logic gate module 2 is used to output the target detection result of the target circuit.

[0038] The target circuit may refer to a circuit to be detected, and the target circuit may include multiple target switch units. For example, the target circuit may be an adjustable capacitor circuit, and the adjustable capacitor circuit may use discrete capacitor components or integrated capacitors on a chip. Figure 2 As shown, one of the plates of capacitors 1 to n is connected to the capacitor access circuit point, and the other plate is connected to its corresponding switch 1 to n. The capacitance value of the access circuit is controlled by the switch enable signal of capacitors 1 to n controlled by the system. For example, the system controls switch 1 of capacitor 1 and switch 2 of capacitor 2 to be closed, and the other switches are disconnected. At this time, the capacitors connected to the circuit are only capacitor 1 and capacitor 2, and the capacitance value of the adjustable capacitor circuit is the sum of the capacitance values ​​of capacitor 1 and capacitor 2. Of course, the target circuit can also be other types of circuits, including multiple target switch units, and the second end of each target switch unit can receive the second voltage.

[0039] The implementation principle is as follows:

[0040] In a possible implementation manner, the detection circuit provided in this embodiment is used to detect whether a target switch unit in a target circuit has a fault, that is, whether the target switch unit can be normally closed under the control of a switch control signal. During the detection process, the first switch enable signal received by the target switch unit can be controlled by the system to close the target switch unit. At the same time, the second switch enable signal received by the detection switch unit 11 can be controlled in the detection circuit to close each detection switch unit 11 of the detection switch array module 1. As a specific example, Figure 3 In the switch control schematic diagram shown, the target switch unit may include an NMOS (Negative channel-Metal-Oxide-Semiconductor, N-type metal oxide semiconductor) tube, and the detection switch unit 11 may include a PMOS (Positive channel-Metal-Oxide-Semiconductor, P-type metal oxide semiconductor) tube. The control end of the NMOS tube in the target switch unit may be used to receive a first switch enable signal, and the control end of the PMOS tube in the detection switch unit 11 may be used to receive a second switch enable signal. During the detection process, the first switch enable signal may be a high-level signal, and the second switch enable signal may be a low-level signal, thereby controlling the target switch unit and the detection switch unit 11 to close. Of course, the target switch unit and the detection switch unit 11 may also include other types of switch units, such as triodes, and the present embodiment does not limit the specific types of switch units.

[0041] The logic gate module 2 may include a plurality of input terminals, each of which is used to receive a voltage at a second terminal of a detection switch unit 11 (ie, a first terminal of a target switch unit connected to the detection switch unit 11 ).

[0042] The following is an introduction using a detection switch unit 11 as an example. When both the target switch unit and the detection switch unit 11 are closed, the voltage received by the corresponding input end of the logic gate module 2 can be the voltage divided by the impedance of the target switch unit and the impedance of the detection switch unit 11. Through reasonable impedance value, switch selection, etc., the voltage can be made to conform to the logic level of the second voltage, indicating that the target switch unit is closed and connected to the second voltage. For example, the second voltage received by the target switch unit can be a zero potential voltage, and its logic level is a low level; correspondingly, the first voltage received by the detection switch unit 11 can be a power supply voltage, and its logic level is a high level; when both the target switch unit and the detection switch unit 11 are closed, the voltage received by the corresponding input end of the logic gate module 2 can be a low level (i.e., conforming to the logic level of the second voltage), conversely, if the target switch unit is not closed and the detection switch unit 11 is closed, the voltage received by the corresponding input end of the logic gate module 2 can be a high level.

[0043] Optionally, the detection switch unit 11 may be a switch unit with a certain turn-on impedance, and may specifically include a field effect tube unit or a transistor unit.

[0044] Optionally, the impedance of the detection switch unit 11 may be greater than the impedance of the target switch unit, so that when the target switch unit is closed, the voltage difference between the first end and the second end is small, and the voltage at the first end of the target switch unit may be close to the second voltage at the second end, which conforms to the logic level of the second voltage. Optionally, in order to facilitate adjusting the impedance of the detection switch unit 11 to a suitable impedance value, the detection switch unit 11 may include an impedance subunit and a switch subunit, and the impedance of the detection switch unit 11 is further adjusted by the impedance subunit, for example, the impedance subunit may include a resistor.

[0045] If the target switch unit is faulty, i.e. not closed, and the detection switch unit 11 is closed, the voltage received by the input end of the logic gate module 2 may be a first voltage, which is logically opposite to the second voltage. Therefore, it is possible to determine whether the first voltage is received by the logic level result output by the logic gate module 2. If the first voltage is received, it indicates that the target circuit is faulty.

[0046] As a specific example, the first voltage may refer to a high-level voltage (e.g., a power supply voltage), and the second voltage may refer to a low-level voltage (e.g., a ground voltage). If the target switch unit and the detection switch unit 11 are both closed, the target switch unit pulls down the voltage at the corresponding input terminal of the logic gate module 2 so that the signal of the voltage conforms to logic 0. If the target switch unit is not closed, the detection switch unit 11 is closed, and the detection switch unit 11 pulls up the voltage at the input terminal of the logic gate module 2 so that the signal of the voltage conforms to logic 1.

[0047] As another specific example, the first voltage may refer to a low-level voltage (e.g., a ground voltage), and the second voltage may refer to a high-level voltage (e.g., a power supply voltage). If the target switch unit and the detection switch unit 11 are both closed, the target switch unit pulls up the voltage at the input end connected to the logic gate module 2, so that the signal of the voltage conforms to logic 1. If the target switch unit is not closed, the detection switch unit 11 is closed, and the detection switch unit 11 pulls down the voltage at the input end connected to the logic gate module 2, so that the signal of the voltage conforms to logic 0.

[0048] Optionally, when the first voltage is higher than the second voltage, the logic gate module 2 may include an OR gate module; when the second voltage is higher than the first voltage level, the logic gate module 2 may include an AND gate module.

[0049] The OR gate module may include a digital OR gate or a circuit capable of realizing an “OR” function, and the AND gate module may include a digital AND gate or a circuit capable of realizing an “AND” function.

[0050] In one possible implementation, refer to Figure 4 A schematic diagram of a detection circuit based on an OR gate is shown, in which the first voltage is higher than the second voltage, that is, the first voltage is a high-level voltage, and the second voltage level is a low-level voltage. At this time, the logic gate module 2 may include an OR gate module, and an OR operation is performed on its input signal in the logic gate module 2. The second end of the target switch unit receives a low-level voltage. If each target switch unit is closed normally, the input signal of the logic gate module 2 is logic 0, and the output signal after the OR operation is also logic 0, indicating that the target circuit is normal; if any target switch unit has a fault and is not closed, the corresponding detection switch unit 11 pulls up the voltage of its second end, then the input signal of the logic gate module 2 includes logic 1, and the output signal after the OR operation also includes logic 1, indicating that the target circuit has a fault.

[0051] In another possible implementation, referring to Figure 5A schematic diagram of a detection circuit based on an AND gate is shown, in which the second voltage is higher than the first voltage, that is, the second voltage is a high-level voltage, and the first voltage level is a low-level voltage. At this time, the logic gate module 2 may include an AND gate module, and an AND operation is performed on its input signal in the logic gate module 2. The second end of the target switch unit receives a high-level voltage. If each target switch unit is closed normally, the input signal of the logic gate module 2 is logic 1, and the output signal after the AND operation is also logic 1, indicating that the target circuit is normal; if any target switch unit has a fault and is not closed, the corresponding detection switch unit 11 pulls down the voltage of its second end, then the input signal of the logic gate module 2 includes logic 0, and the output signal after the AND operation also includes logic 0, indicating that the target circuit has a fault.

[0052] Optionally, the logic gate module 2 may include a first logic gate unit 21, the input end of the first logic gate unit 21 is connected to the second end of each detection switch unit 11, and the output end of the first logic gate unit 21 is used to output the first detection sub-result of the target circuit.

[0053] In a possible implementation, the first logic gate unit 21 can be used as a total logic gate unit to perform a logic operation on the second terminal voltage of each detection switch unit 11, and output a first detection sub-result of the target circuit to indicate whether the target circuit has a fault. The output end of the first logic gate unit 21 can be connected to the output end of the logic gate module, and the first detection sub-result is used as the target detection result of the target circuit. For example, the detection switch array module 1 can include detection switch 1, detection switch 2, detection switch 3, and detection switch 4, and the second terminal voltages of detection switches 1 to 4 can be connected to the first logic gate unit 21 for logic operation.

[0054] Reference Figure 6 The schematic diagram of the first logic gate unit based on the OR gate is shown. When the logic gate module 2 includes an OR gate module, the first logic gate unit 21 can be used as a total OR gate unit to perform a phase OR operation on the second terminal voltage of each detection switch unit 11. When the output signal is logic 0, it indicates that the target switch in the target circuit is working normally. When the output signal is logic 1, it indicates that there is a fault in the target circuit.

[0055] Reference Figure 7 The schematic diagram of the first logic gate unit based on the AND gate is shown. When the logic gate module 2 includes an AND gate module, the first logic gate unit 21 can be used as a total AND gate unit to perform an AND operation on the second terminal voltage of each detection switch unit 11. When the output signal is logic 1, it indicates that the target switch in the target circuit is working normally. When the output signal is logic 0, it indicates that there is a fault in the target circuit.

[0056] Further, on the basis of the above-mentioned first logic gate unit 21, the logic gate module 2 may further include a plurality of second logic gate units 22, and the second logic gate units 22 correspond to the detection switch units 11 one by one;

[0057] The first input end of the second logic gate unit 22 is connected to the second end of the corresponding detection switch unit 11, the second input end of the second logic gate unit 22 is used to receive the second voltage, and the output end of the second logic gate unit 22 is used to output the second detection sub-result of the corresponding detection switch unit 11.

[0058] In a possible implementation, when a target switch unit in a target circuit fails, the target switch unit that fails can be accurately located by the second logic gate unit 22. The second logic gate unit 22 corresponds to the detection switch unit 11 one by one, and each second logic gate unit 22 performs a logic operation on the second terminal voltage and the second voltage of the input detection switch unit 11, and outputs the second detection sub-result of the corresponding detection switch unit 11 to determine whether the logic level of the second terminal voltage meets the logic level of the second voltage. If it meets, it indicates that the target switch unit is working normally; if it does not meet, it indicates that the target switch unit is faulty.

[0059] The output end of the second logic gate unit 22 can be connected to the output end of the logic gate module 2, and each second detection sub-result is used as the target detection result. Optionally, when the output end of the first logic gate unit 21 is also connected to the output end of the logic gate module 2, the target detection result can include the first detection sub-result output by the first logic gate unit 21 and the second detection sub-result output by each second logic gate unit 22.

[0060] As a specific example, see Figure 8 The schematic diagram of the second logic gate unit based on the OR gate is shown. When the logic gate module 2 includes the OR gate module, each second logic gate unit 22 may include an OR gate subunit, and the input signal of the OR gate subunit may include the second terminal voltage and the ground voltage of the detection switch unit 11. Assuming that the output signal of the total OR gate unit is logic 1, the output signal of OR gate 1 is logic 1, the output signal of OR gate 2 is logic 0, the output signal of OR gate 3 is logic 0, and the output signal of OR gate 4 is logic 0, it can be determined that the target switch 1 is faulty, the target switch 2 is normal, the target switch 3 is normal, and the target switch 4 is normal.

[0061] As another specific example, refer to Fig. 9The schematic diagram of the second logic gate unit based on the AND gate is shown. When the logic gate module 2 includes the AND gate module, each second logic gate unit 22 may include an AND gate subunit, and the input signal of the AND gate subunit may include the second terminal voltage and the power supply voltage of the detection switch unit 11. Assuming that the output signal of the total AND gate unit is logic 0, the output signal of the AND gate 1 is logic 0, the output signal of the AND gate 2 is logic 1, the output signal of the AND gate 3 is logic 1, and the output signal of the AND gate 4 is logic 1, it can be determined that the target switch 1 is faulty, the target switch 2 is normal, the target switch 3 is normal, and the target switch 4 is normal.

[0062] Optional, see Fig.10 As shown in the schematic diagram of the logic gate module, the logic gate module 2 may further include an enable control module 23 , the input end of the enable control module 23 is connected to the output end of the first logic gate unit 21 , and the output end of the enable control module 23 is used to output an enable control signal of the second logic gate unit 22 .

[0063] In a possible implementation, when the enable control module 23 receives the first detection sub-result indicating that the target switch in the target circuit works normally, it can output an enable control signal at a non-enable level to control the second logic gate unit 22 to be in a non-working state; when the enable control module 23 receives the first detection sub-result indicating that the target switch in the target circuit is faulty, it can output an enable control signal at an enable level to control the second logic gate unit 22 to be in a working state. That is, when the target switch in the target circuit works normally, the second logic gate unit 22 does not work to reduce circuit power consumption; when the target switch in the target circuit is faulty, the second logic gate unit 22 works to locate the faulty target switch.

[0064] Optionally, the logic gate module 2 may include a plurality of third logic gate units 24, and the third logic gate units 24 correspond one-to-one to the detection switch units 11;

[0065] The first input end of the third logic gate unit 24 is connected to the second end of the corresponding detection switch unit 11, the second input end of the third logic gate unit 24 is used to receive the second voltage, and the output end of the third logic gate unit 24 is used to output the second detection sub-result of the corresponding detection switch unit 11.

[0066] A third logic gate unit based on an OR gate such as Fig.11 As shown, a third logic gate unit based on an AND gate is as follows Fig.12 The implementation principle of the third logic gate unit 24 is the same as that of the second logic gate unit 22, and will not be described in detail here.

[0067] Furthermore, based on the above-mentioned third logic gate unit 24, the logic gate module 2 can also include a fourth logic gate unit 25, the input end of the fourth logic gate unit 25 is connected to the output end of each third logic gate unit 24, and the output end of the fourth logic gate unit 25 is used to output the fourth detection sub-result of the target circuit.

[0068] A fourth logic gate unit based on an OR gate such as Fig.13 As shown, a fourth logic gate unit based on an AND gate is as follows Fig.14 As shown. The fourth logic gate unit 25 has the same function as the first logic gate unit 21, and can be used as a total logic gate unit to output the detection result of the target circuit, that is, the fourth detection sub-result. The difference between the fourth logic gate unit 25 and the first logic gate unit 21 is the input signal. The output signal of the fourth logic gate unit 25 is the output signal of each third logic gate unit 24, while the input signal of the first logic gate unit 21 is the second terminal voltage of each detection switch unit 11.

[0069] Thereafter, if the target detection result of the target circuit indicates that it is normal, the target circuit can be applied in subsequent processing; if the target detection result of the target circuit indicates that there is a fault, the target circuit can be discontinued. This embodiment does not limit the application of the target circuit.

[0070] The embodiments of the present application can achieve the following beneficial effects:

[0071] (1) The detection circuit includes a detection switch array module and a logic gate module, wherein the detection switch array module includes a plurality of detection switch units. During the test process of the target circuit, whether the target switch unit in the target circuit has a fault is detected based on the second terminal voltage of the detection switch unit, thereby detecting whether the access of the corresponding capacitor unit has a fault, and outputting the target detection result of the target circuit through the logic gate module.

[0072] (2) The detection circuit provided in this application has a simple structure, small scale and small area overhead.

[0073] (3) The detection circuit provided in the present application can accurately locate the target switch unit and capacitor unit where a fault occurs.

[0074] The exemplary embodiment of the present application also provides a chip, including the detection circuit provided by the embodiment of the present application. The chip provided by the present application can be used to detect whether a switch is faulty. During the test process of the target circuit, based on the second terminal voltage of the detection switch unit, whether a target switch unit in the target circuit is faulty is detected, thereby detecting whether the access of the corresponding capacitor unit is faulty, and outputting the target detection result of the target circuit through the logic gate module.

[0075] The exemplary embodiment of the present application also provides an electronic device, including the detection circuit provided by the embodiment of the present application. The electronic device provided by the present application can be used to detect whether a switch has a fault. During the test process of the target circuit, based on the second terminal voltage of the detection switch unit, whether the target switch unit in the target circuit has a fault is detected, thereby detecting whether the access of the corresponding capacitor unit has a fault, and outputting the target detection result of the target circuit through the logic gate module.

Claims

1. A detection circuit, characterized in that: The detection circuit includes a detection switch array module and a logic gate module, the detection switch array module includes a plurality of detection switch units, and the plurality of detection switch units are connected in parallel; The first end of the detection switch unit is used to receive a first voltage, the second end of the detection switch unit is connected to the first end of the target switch unit to be detected in the target circuit, and the second end of the detection switch unit is also connected to the input end of the logic gate module, wherein in the target circuit, the second end of the target switch unit is used to receive a second voltage, and the first voltage and the second voltage are not equal; The output end of the logic gate module is used to output the target detection result of the target circuit.

2. The detection circuit according to claim 1, characterized in that: The logic gate module includes a first logic gate unit, an input end of the first logic gate unit is connected to the second end of each detection switch unit, and an output end of the first logic gate unit is used to output a first detection sub-result of the target circuit.

3. The detection circuit according to claim 2, characterized in that: The logic gate module further includes a plurality of second logic gate units, and the second logic gate units correspond one to one to the detection switch units; The input end of the second logic gate unit is connected to the second ends of the remaining detection switch units except the corresponding detection switch unit, and the output end of the second logic gate unit is used to output the second detection sub-result of the corresponding detection switch unit.

4. The detection circuit according to claim 3, characterized in that: The logic gate module further includes an enable control module, the input end of the enable control module is connected to the output end of the first logic gate unit, and the output end of the enable control module is used to output an enable control signal of the second logic gate unit.

5. The detection circuit according to claim 1, characterized in that: The logic gate module includes a plurality of third logic gate units, and the third logic gate units correspond to the detection switch units one by one; The input end of the third logic gate unit is connected to the second ends of the remaining detection switch units except the corresponding detection switch unit, and the output end of the third logic gate unit is used to output the third detection sub-result of the corresponding detection switch unit.

6. The detection circuit according to claim 5, characterized in that: The logic gate module further includes a fourth logic gate unit, an input end of the fourth logic gate unit is connected to an output end of each of the third logic gate units, and an output end of the fourth logic gate unit is used to output a fourth detection sub-result of the target circuit.

7. The detection circuit according to claim 1, characterized in that: When the first voltage is higher than the second voltage, the logic gate module includes an OR gate module; When the second voltage is higher than the first voltage, the logic gate module includes an AND gate module.

8. The detection circuit according to claim 1, characterized in that: The detection switch unit includes a field effect tube unit or a transistor unit.

9. The detection circuit according to claim 1, characterized in that: The impedance of the detection switch unit is greater than the impedance of the target switch unit.

10. A chip, characterized in that: The method comprises the detection circuit as claimed in any one of claims 1 to 9.

11. An electronic device, characterized in that: The method comprises the detection circuit as claimed in any one of claims 1 to 9.

Images