Silicon carbide MOSFET active Miller clamp circuit

Abstract

The utility model provides a silicon carbide MOSFET active Miller clamping circuit comprising a driving module which is connected with a power supply module, a comparison module, a pulse signal end and a silicon carbide MOSFET tube. The power supply module, the pulse signal end, the comparison module and the silicon carbide MOSFET tube are also connected with the logic module; the comparison module is also connected with the silicon carbide MOSFET tube; the power supply module is also connected with a power supply VCC; according to the technical scheme of the utility model, the gate drive signal is acquired, compared with the reference voltage, and then fed back to the logic module, so that the on / off of the MOSFET tube in the logic module is controlled. When a gate pole driving signal is at a low level, the MOSFET in the logic module is switched on, a low-impedance path is provided for the silicon carbide MOSFET, the gate pole of the silicon carbide MOSFET can be forcefully switched off by the low-impedance path, and the situation that a power device is damaged due to direct connection of an upper bridge arm and a lower bridge arm is avoided.

Description

Technical Field

[0001] The utility model belongs to the technical field of power electronic drive, and in particular relates to a silicon carbide MOSFET active Miller clamp circuit. Background Art

[0002] Silicon carbide MOSFETs are mostly used in high voltage and high switching rate situations. Due to its own properties, its dv / dt during switching is significantly higher than that of ordinary silicon-based MOSFETs. Taking a bridge circuit as an example, for the switching devices in the circuit, when the upper tube is quickly turned on and the lower tube is turned off, the Vds of the lower tube will rise rapidly, and the dv / dt will generate a high current on the Miller parasitic capacitor, which will cause a small spike in the gate voltage through the lower tube gate turn-off resistor Rgoff. Since the dv / dt of the silicon carbide MOSFET switching process is much higher than that of ordinary silicon-based MOSFETs, the gate voltage spike generated is higher than that of ordinary silicon-based MOSFETs. The threshold voltage of silicon carbide MOSFETs is generally 2V to 5V. If the voltage rise caused by crosstalk during this process exceeds the threshold voltage of the silicon carbide MOSFET, it will cause the lower bridge arm to be turned on by mistake, resulting in the upper and lower bridge arms being directly connected, causing serious consequences such as system short circuit damage.

[0003] At present, in order to suppress the mis-turning on of silicon carbide MOSFET, the gate-level drive circuit and power circuit are mainly used. By increasing the gate-level turn-on resistance Rgon to reduce the switching speed, dv / dt is reduced; reducing the gate-level turn-off resistance Rgoff to reduce the voltage spike caused by crosstalk; adding a small capacitor between the gate and the source to reduce the influence of Miller capacitance. Although the above method effectively suppresses crosstalk, it also reduces the switching speed and increases the loss. The negative voltage shutdown method can effectively suppress it, but the voltage spike caused by crosstalk is too large and can also cause mis-turning on. Utility Model Content

[0004] In order to solve the above technical problems, the utility model provides a silicon carbide MOSFET active Miller clamp circuit.

[0005] The utility model is realized through the following technical solutions.

[0006] The utility model provides a silicon carbide MOSFET active Miller clamp circuit, comprising a driving module, wherein the driving module is connected to a power module, a comparison module, a pulse signal end, and a silicon carbide MOSFET tube; the power module, the pulse signal end, the comparison module, and the silicon carbide MOSFET tube are also connected to a logic module; the comparison module is also connected to the silicon carbide MOSFET tube; and the power module is also connected to a power supply VCC.

[0007] The power module includes a SiC MOSFET drive power module and a power conversion circuit module both connected to a power supply VCC.

[0008] The power conversion circuit module includes an LDO linear regulator U3; the IN pin of the LDO linear regulator U3 is connected to the power supply VCC and one end of the capacitor C13, the Out pin is connected to one end of the capacitor C14, and the GND pin is connected to the other end of the capacitor C13 and the capacitor C14 and then connected to the power supply ground GND.

[0009] The SiC MOSFET driving power module includes a PWM control chip U1, a MOSFET driving chip U2, a transformer T and a rectifier and voltage stabilization circuit;

[0010] Pin 1 of the PWM control chip U1 is connected to one end of the resistor R7, and pins 3, 4, 5, 6, 8, 9, and 10 are connected to the power supply ground GND through resistor R1, resistor R2, capacitor C1, resistor R4, capacitor C2, capacitor C6, and resistor R8, respectively; pin 7 is connected to pin 5 of the PWM control chip U1 through resistor R5, and pins 13 and 16 are both connected to the power supply ground GND through capacitor C5; pin 9 is also connected to the other end of the resistor R7, and pins 15 and 12 are respectively connected to the power supply VCC and the power supply ground GND; pin 16 is also connected to pin 2 of the PWM control chip U1 through resistor R3, and pin 2 is also connected to the power supply ground GND through resistor R6;

[0011] The INA pin and INB pin of the MOSFET driver chip U2 are connected to the 14 pin and the 11 pin of the PWM control chip U1 respectively, the INA pin and the INB pin are also connected to the power supply ground GND through the resistor R13 and the resistor R14 respectively, the GND pin is connected to the power supply ground GND, the OUTA pin is connected to one end of the resistor R15 and the gate of the N-type MOS tube Q2 through the resistor R10, the OUTB pin is connected to one end of the resistor R16 and the gate of the N-type MOS tube Q3 through the resistor R12, the VDD pin is connected to the power supply VCC, and the other ends of the resistors R15 and R16 are connected to the power supply GND;

[0012] Pin 1 and pin 4 of the transformer T are connected to the drain of the N-type MOS transistor Q2 and the drain of the N-type MOS transistor Q3 respectively, pin 2 and pin 3 are connected to one end of the capacitor C11 and the capacitor C12 connected in parallel, pin 8 is connected between the anode of the diode D2 and the cathode of the diode D5, pin 7 is connected between the anode of the diode D3 and the cathode of the diode D4, pin 6 is connected between the anode of the diode D7 and the cathode of the diode D9, and pin 5 is connected between the anode of the diode D8 and the cathode of the diode D10; the other end of the capacitor C11 and the capacitor C12 connected in parallel is connected to the power supply ground GND;

[0013] The rectifier and voltage stabilizing circuit includes a diode D2, a diode D3, a diode D7 and a diode D8; the cathodes of the diode D2 and the diode D3 are connected to the cathode of the voltage regulator tube D1, and one end of the capacitor C3 and the capacitor C4; the anode of the voltage regulator tube D1 and the other end of the capacitor C3 are connected to one end of the resistor R9 and the base of the transistor Q1; the other end of the capacitor C4 is connected to the emitter of the transistor Q1, one end of the capacitor C7 and the power supply ground Gnd_ISO1; the diode D5 and the anode of the diode D4, the other end of the resistor R9, and the other end of the capacitor C7 are connected to the emitter of the transistor Q1, ... cathode of the diode D4, the other end of the resistor R9, and the other end of the capacitor C The cathodes of the diode D7 and the diode D8 are connected to the cathode of the voltage-stabilizing tube D6, and one end of the capacitor C8 and the capacitor C9; the anode of the voltage-stabilizing tube D8 and the other end of the capacitor C8 are connected to one end of the resistor R11 and the base of the transistor Q4; the other end of the capacitor C9 is connected to the emitter of the transistor Q4, one end of the capacitor C10 and the power ground Gnd_ISO2; the anodes of the diode D9 and the diode D10, the other end of the resistor R11, and the other end of the capacitor C10 are connected to the collector of the transistor Q4.

[0014] The logic module includes an AND gate chip U5, a NOR gate chip U6, and a resistor R18; pin 1 of the AND gate chip U5 is connected to pin 1 of the NOR gate chip U6, pin 2 is connected to the pulse signal end through a resistor R19, pin 2 is also connected to the power supply ground GND through a capacitor C15, pin 3 is connected to the power supply ground GND, pin 4 is connected to pin 2 of the NOR gate chip U6, and pin 5 is connected to the Out pin of the LDO linear regulator U3; pin 5 of the NOR gate chip U6 is connected to the Out pin of the LDO linear regulator U3, pin 3 is connected to the power supply ground GND, and pin 4 is connected to the gate of the MOS tube Q5 through a resistor R18; the drain of the MOS tube Q5 is connected to the gate of the silicon carbide MOSFET tube, and the source is connected to the power ground VEE_ISO1.

[0015] The comparison module includes a comparator U4 and a resistor R17; the non-phase input terminal of the comparator U4 is connected to the gate of the silicon carbide MOSFET tube, the output terminal is connected to one end of the resistor R17 and pin 1 of the gate chip U5, the power supply voltage input terminal is connected to the other end of the resistor R17 and the Out pin of the LDO linear regulator U3, and the power supply voltage output terminal is connected to the power supply ground GND.

[0016] The drive module includes an isolation drive chip U7; the VCC1 pin of the isolation drive chip U7 is connected to the Out pin of the LDO linear regulator U3, and one end of the capacitor C17 and the capacitor C18 connected in parallel, the IN+ pin is connected to the pulse signal end through the resistor R20, the IN+ pin is also connected to the power supply ground GND through the capacitor C16, the IN- pin and the GND1 pin are connected to the power supply ground GND, the VEE2 pin is connected to the collector of the transistor Q1, and one end of the capacitor C21 and the capacitor C22 connected in parallel. The OUTL pin and the OUTH pin are connected to the gate of the silicon carbide MOSFET tube through the resistor R21 and the resistor R22 respectively, the VCC2 pin is connected to one end of the capacitor C4, and one end of the capacitor C19 and the capacitor C20 in parallel; the other end of the capacitor C17 and the capacitor C18 in parallel is connected to the power supply ground GND, the other end of the capacitor C19 and the capacitor C20 in parallel, and the other end of the capacitor C21 and the capacitor C22 in parallel are connected to the power ground GND and the power ground Gnd_ISO1.

[0017] The beneficial effects of the utility model are as follows: an active Miller clamp circuit of a silicon carbide MOSFET of the utility model collects a gate drive signal, compares it with a reference voltage, and further feeds back to a logic module, thereby controlling the on and off of the MOSFET tube in the logic module; when the gate drive signal is at a low level, the MOSFET tube in the logic module is turned on, providing a low-impedance path for the silicon carbide MOSFET, and this low-impedance path can effectively turn off the gate of the silicon carbide MOSFET tube, thereby avoiding damage to the power device caused by the direct conduction of the upper and lower bridge arms. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic diagram of the structural principle of the utility model;

[0019] Figure 2 It is a circuit principle diagram of the power conversion circuit module of the utility model;

[0020] Figure 3 This is a circuit schematic diagram of the SiC MOFET drive power module of the utility model;

[0021] Figure 4 It is the circuit principle diagram of the logic module and comparison module of the utility model;

[0022] Figure 5 This is a circuit schematic diagram of a drive module of the utility model. DETAILED DESCRIPTION

[0023] The technical solution of the utility model is further described below, but the scope of protection required is not limited to the description.

[0024] Example 1

[0025] like Figure 1 The figure shows a schematic diagram of the structure principle of the utility model; a silicon carbide MOSFET active Miller clamp circuit, comprising a driving module, the driving module is connected to a power module, a comparison module, a pulse signal end, and a silicon carbide MOSFET tube; the power module, the pulse signal end, the comparison module and the silicon carbide MOSFET tube are also connected to a logic module; the comparison module is also connected to the silicon carbide MOSFET tube; the power module is also connected to a power supply VCC;

[0026] Preferably, the voltage value of the power supply VCC is 15V.

[0027] The power module includes a SiC MOSFET drive power module and a power conversion circuit module both connected to a power supply VCC.

[0028] like Figure 2 The figure shows a circuit schematic diagram of the power conversion circuit module of the utility model; the power conversion circuit module includes an LDO linear regulator U3; the IN pin of the LDO linear regulator U3 is connected to the power supply VCC and one end of the capacitor C13, the Out pin is connected to one end of the capacitor C14, and the GND pin is connected to the other end of the capacitor C13 and the capacitor C14 and then connected to the power supply ground GND;

[0029] Preferably, the model of the LDO linear regulator U3 is CJ7805;

[0030] The maximum output current of the CJ7805 LDO linear regulator U3 is 1.5A, which can convert the 15V power supply into a +5V power supply to provide a +5V power supply to the logic module and the driver module.

[0031] like Figure 3 The figure shows the circuit schematic diagram of the SiC MOFET driving power module of the utility model; the SiC MOFET driving power module includes a PWM control chip U1, a MOSFET driving chip U2, a transformer T and a rectifier voltage stabilizing circuit;

[0032] The SiC MOFET drive power module converts the 15V power supply into drive voltages VCC_ISO1 (18V), VCC_ISO2 (18V) and VEE_ISO1 (-3V), VEE_ISO2 (-3V) for two silicon carbide MOSFET tubes.

[0033] Pin 1 of the PWM control chip U1 is connected to one end of the resistor R7, and pins 3, 4, 5, 6, 8, 9, and 10 are connected to the power supply ground GND through resistor R1, resistor R2, capacitor C1, resistor R4, capacitor C2, capacitor C6, and resistor R8, respectively; pin 7 is connected to pin 5 of the PWM control chip U1 through resistor R5, and pins 13 and 16 are both connected to the power supply ground GND through capacitor C5; pin 9 is also connected to the other end of the resistor R7, and pins 15 and 12 are respectively connected to the power supply VCC and the power supply ground GND; pin 16 is also connected to pin 2 of the PWM control chip U1 through resistor R3, and pin 2 is also connected to the power supply ground GND through resistor R6;

[0034] The INA pin and INB pin of the MOSFET driver chip U2 are connected to the 14 pin and the 11 pin of the PWM control chip U1 respectively, the INA pin and the INB pin are also connected to the power supply ground GND through the resistor R13 and the resistor R14 respectively, the GND pin is connected to the power supply ground GND, the OUTA pin is connected to one end of the resistor R15 and the gate of the N-type MOS tube Q2 through the resistor R10, the OUTB pin is connected to one end of the resistor R16 and the gate of the N-type MOS tube Q3 through the resistor R12, the VDD pin is connected to the power supply VCC, and the other ends of the resistors R15 and R16 are connected to the power supply GND;

[0035] Preferably, the model of the PWM control chip U1 is SG3525M / TR;

[0036] Preferably, the model of the MOSFET driver chip U2 is COS4427SR-SOP8;

[0037] The SG3525 is a PWM control chip. The input power supply VCC can vary within 8 to 35V, usually powered by +15V. The output drive is a push-pull output form, which increases the driving capability. It integrates an undervoltage lockout circuit, a soft start control circuit, and a PWM latch. It also has overcurrent protection functions and adjustable frequency functions. The chip output signals drva and drvb use a push-pull output circuit. The phase difference between the two is 180°. The peak value of the pull current and the sink current can reach 400mA. There is a certain dead time between the two drive pulses to prevent direct connection due to factors such as switch delays, which may damage the device.

[0038] The oscillation frequency f of SG3525 is calculated by the following formula:

[0039]

[0040] Where: C T Indicates: the capacitance value of the 5-pin external capacitor C1 of the PWM control chip U1; R T Indicates: the resistance value of the 6-pin external resistor R4 of the PWM control chip U1; R D is: the resistance value of the 7-pin external resistor R5 of the PWM control chip U1;

[0041] Two-way drive pulse dead time t D for:

[0042] t D =3C T R D (2)

[0043] The PWM control chip U1, model SG3525M / TR, generates two output signals drva and drvb, and the driving capability is enhanced by the MOSFET driver chip U2, model COS4427SR-SOP8, which can provide a peak current of 1.5A for a 1000pF capacitive load.

[0044] Pin 1 and pin 4 of the transformer T are connected to the drain of the N-type MOS transistor Q2 and the drain of the N-type MOS transistor Q3 respectively, pin 2 and pin 3 are connected to one end of the capacitor C11 and the capacitor C12 connected in parallel, pin 8 is connected between the anode of the diode D2 and the cathode of the diode D5, pin 7 is connected between the anode of the diode D3 and the cathode of the diode D4, pin 6 is connected between the anode of the diode D7 and the cathode of the diode D9, and pin 5 is connected between the anode of the diode D8 and the cathode of the diode D10; the other end of the capacitor C11 and the capacitor C12 connected in parallel is connected to the power supply ground GND;

[0045] Preferably, the transformer T is a self-wound transformer T;

[0046] The self-wound transformer T has one input and two outputs. In order to convert the 15V power supply voltage into two 21V voltages, the primary and secondary turns ratio needs to be:

[0047]

[0048] Where: N1 represents: the number of primary turns of the self-winding transformer T; N2 represents: the number of secondary turns of the self-winding transformer T.

[0049] The rectifier and voltage stabilizing circuit includes a diode D2, a diode D3, a diode D7 and a diode D8; the cathodes of the diode D2 and the diode D3 are connected to the cathode of the voltage regulator tube D1, and one end of the capacitor C3 and the capacitor C4; the anode of the voltage regulator tube D1 and the other end of the capacitor C3 are connected to one end of the resistor R9 and the base of the transistor Q1; the other end of the capacitor C4 is connected to the emitter of the transistor Q1, one end of the capacitor C7 and the power supply ground Gnd_ISO1; the diode D5 and the anode of the diode D4, the other end of the resistor R9, and the other end of the capacitor C7 are connected to the emitter of the transistor Q1, ... cathode of the diode D4, the other end of the resistor R9, and the other end of the capacitor C The cathodes of the diode D7 and the diode D8 are connected to the cathode of the voltage regulator tube D6, and one end of the capacitor C8 and the capacitor C9, the anode of the voltage regulator tube D8 and the other end of the capacitor C8 are connected to one end of the resistor R11 and the base of the transistor Q4, the other end of the capacitor C9 is connected to the emitter of the transistor Q4, one end of the capacitor C10 and the power ground Gnd_ISO2, the anodes of the diode D9 and the diode D10, the other end of the resistor R11, and the other end of the capacitor C10 are connected to the collector of the transistor Q4;

[0050] The output voltage of the self-winding transformer T is divided into 21V voltage into VCC_ISO1 (18V), VCC_ISO2 (18V) voltage and VEE_ISO1 (-3V), VEE_ISO2 (-3V) voltage through the rectification and voltage stabilization circuit.

[0051] like Figure 4 The figure shows the circuit principle diagram of the logic module and comparison module of the utility model; the logic module includes an AND gate chip U5, a NOR gate chip U6, and a resistor R18; the pin No. 1 of the AND gate chip U5 is connected to the pin No. 1 of the NOR gate chip U6, the pin No. 2 is connected to the pulse signal end through a resistor R19, the pin No. 2 is also connected to the power supply ground GND through a capacitor C15, the pin No. 3 is connected to the power supply ground GND, the pin No. 4 is connected to the pin No. 2 of the NOR gate chip U6, and the pin No. 5 is connected to the Out pin of the LDO linear regulator U3; the pin No. 5 of the NOR gate chip U6 is connected to the Out pin of the LDO linear regulator U3, the pin No. 3 is connected to the power supply ground GND, and the pin No. 4 is connected to the gate of the MOS tube Q5 through a resistor R18; the drain of the MOS tube Q5 is connected to the gate of the silicon carbide MOSFET tube, and the source is connected to the power supply ground VEE_ISO1;

[0052] The comparison module includes a comparator U4 and a resistor R17; the non-inverting input terminal of the comparator U4 is connected to the gate of the silicon carbide MOSFET tube, the output terminal is connected to one end of the resistor R17 and the pin 1 of the AND gate chip U5, the power supply voltage input terminal is connected to the other end of the resistor R17 and the Out pin of the LDO linear regulator U3, and the power supply voltage output terminal is connected to the power supply ground GND;

[0053] Preferably, the model of the comparator U4 is LMV331M5;

[0054] Preferably, the model of the AND gate chip U5 is SN74AHC1G08;

[0055] Preferably, the model of the NOR gate chip U6 is SN74LVC1G02;

[0056] Specifically, the driving signal G1 of the silicon carbide MOSFET tube is compared with the Vclamp_th (2V) signal through the comparator U4; the output signal of the comparator U4 is used as the input signal IN2 of the AND gate chip U5, and IN1 is used as another input signal of the AND gate chip U5; further, the output signal of the AND gate chip U5 and IN2 are used as input signals of the NOR gate chip U6; the output signal of the NOR gate chip U6 is used as the driving signal for controlling the MOS tube Q5, thereby providing a low impedance path for the silicon carbide MOSFET tube;

[0057] Preferably, the resistor R17 is a pull-up resistor; the resistor R9 and the capacitor C15 form a low-pass filter to filter out high-frequency signals in the circuit; and the resistor R18 is a current-limiting resistor.

[0058] like Figure 5 The schematic diagram of the driving module circuit of the utility model is shown; the driving module includes an isolation driving chip U7; the VCC1 pin of the isolation driving chip U7 is connected to the Out pin of the LDO linear regulator U3, and one end of the capacitor C17 and the capacitor C18 in parallel, the IN+ pin is connected to the pulse signal end through the resistor R20, the IN+ pin is also connected to the power supply ground GND through the capacitor C16, the IN- pin and the GND1 pin are connected to the power supply ground GND, the VEE2 pin is connected to the collector of the transistor Q1, and the capacitor C21 and the capacitor C18 are connected to the collector of the transistor Q1. One end of the capacitor C22 connected in parallel is connected, the OUTL pin and the OUTH pin are connected to the gate of the silicon carbide MOSFET tube through the resistor R21 and the resistor R22 respectively, the VCC2 pin is connected to one end of the capacitor C4, and one end of the capacitor C19 and the capacitor C20 connected in parallel is connected; the other end of the capacitor C17 and the capacitor C18 connected in parallel is connected to the power supply ground GND, the other end of the capacitor C19 and the capacitor C20 connected in parallel, and the other end of the capacitor C21 and the capacitor C22 connected in parallel are connected to the power supply ground GND and the power supply ground Gnd_ISO1;

[0059] Preferably, the model of the isolation driver chip U7 is IVCO1A01, the chip adopts a separate output, the package form is SOIC-8, the isolation voltage can reach 3.75kVrms, and the peak current can reach 10A. In addition, the common mode anti-interference degree is ≥100kV / us, which enhances the robustness of the system;

[0060] Capacitor C17 and capacitor C18 are bypass capacitors for the +5V power supply voltage;

[0061] Capacitors C19, C20, C21 and C22 are driving energy storage capacitors, which are required to have low parasitic parameters and large capacitance;

[0062] Resistors R21 and R22 are driving power resistors, which are required to have a power greater than 2W. The packages usually selected are 1206 or 2512.

[0063] Example 2

[0064] The pulse signal PWM is the control signal, which controls the silicon carbide MOSFET tube through the drive module; the drive module plays the role of signal isolation on the one hand, and amplifies the control signal on the other hand, providing sufficient drive current for the switch of the silicon carbide MOSFET tube, thereby enhancing the signal driving ability;

[0065] The isolation driver chip U7 controls the speed of the silicon carbide MOSFET tube on and off through the driving resistors R21 and R22. Increasing or decreasing the driving resistors R21 and R22 can reduce or speed up the switching speed of the silicon carbide MOSFET tube. Too fast a switching speed will increase the risk of mis-conduction, and too slow a switching speed will increase power consumption, so it is necessary to balance the impact of the two;

[0066] The gate drive signal is fed back to the non-inverting input terminal of the comparator U4 and compared with the reference voltage Vclamp_th (2V) at the inverting input terminal of the comparator U4. When the drive signal is greater than Vclamp_th, the comparator U4 outputs a high level; when the drive signal is less than Vclamp_th, the comparator U4 outputs a low level;

[0067] Reference Figure 4 , IN1 is the input signal of the pulse signal PWM, IN2 is the output signal of the comparator U4, G2 is the switch signal for controlling the MOS tube Q5, and the truth table is shown in Table 1:

[0068] Table 1

[0069] IN1 IN2 G2 Q5 Status 0 0 1 open 0 1 0 close 1 0 0 close 1 1 0 close

[0070] It can be seen from the truth table that when the control signal IN1 is high, the MOS tube Q5 does not act; when the control signal IN1 is low, the comparator U4 output signal IN2 is high, and the MOS tube Q5 does not act; when the control signal IN1 is low, the comparator U4 output signal IN2 is low, and the MOS tube Q5 is turned on, pulling the gate signal of the silicon carbide MOSFET tube down to the shutdown voltage.

[0071] The beneficial effects of the utility model are as follows: an active Miller clamp circuit of a silicon carbide MOSFET of the utility model collects a gate drive signal, compares it with a reference voltage, and further feeds back to a logic module, thereby controlling the on and off of the silicon carbide MOSFET tube; when the gate drive signal is at a low level, the MOSFET tube in the logic module is turned on, thereby providing a low-impedance path for the silicon carbide MOSFET tube, and this low-impedance path can effectively turn off the gate of the silicon carbide MOSFET tube, thereby avoiding damage to the power device caused by the direct conduction of the upper and lower bridge arms.

Claims

1. A silicon carbide MOSFET active Miller clamp circuit, characterized in that: It includes a driving module, which is connected to a power module, a comparison module, a pulse signal end, and a silicon carbide MOSFET tube; the power module, the pulse signal end, the comparison module, and the silicon carbide MOSFET tube are also connected to a logic module; the comparison module is also connected to the silicon carbide MOSFET tube; and the power module is also connected to a power supply VCC.

2. The active Miller clamp circuit of silicon carbide MOSFET according to claim 1, characterized in that: The power module includes a SiC MOSFET drive power module and a power conversion circuit module both connected to a power supply VCC.

3. The active Miller clamp circuit of silicon carbide MOSFET according to claim 2, characterized in that: The power conversion circuit module includes an LDO linear regulator U3; the IN pin of the LDO linear regulator U3 is connected to the power supply VCC and one end of the capacitor C13, the Out pin is connected to one end of the capacitor C14, and the GND pin is connected to the other end of the capacitor C13 and the capacitor C14 and then connected to the power supply ground GND.

4. The active Miller clamp circuit of silicon carbide MOSFET according to claim 2, characterized in that: The SiC MOFET driving power module includes a PWM control chip U1, a MOSFET driving chip U2, a transformer T and a rectifier and voltage stabilization circuit; Pin 1 of the PWM control chip U1 is connected to one end of the resistor R7, and pins 3, 4, 5, 6, 8, 9, and 10 are connected to the power supply ground GND through resistor R1, resistor R2, capacitor C1, resistor R4, capacitor C2, capacitor C6, and resistor R8, respectively; pin 7 is connected to pin 5 of the PWM control chip U1 through resistor R5, and pins 13 and 16 are both connected to the power supply ground GND through capacitor C5; pin 9 is also connected to the other end of the resistor R7, and pins 15 and 12 are respectively connected to the power supply VCC and the power supply ground GND; pin 16 is also connected to pin 2 of the PWM control chip U1 through resistor R3, and pin 2 is also connected to the power supply ground GND through resistor R6; The INA pin and INB pin of the MOSFET driver chip U2 are connected to the 14 pin and the 11 pin of the PWM control chip U1 respectively, the INA pin and the INB pin are also connected to the power supply ground GND through the resistor R13 and the resistor R14 respectively, the GND pin is connected to the power supply ground GND, the OUTA pin is connected to one end of the resistor R15 and the gate of the N-type MOS tube Q2 through the resistor R10, the OUTB pin is connected to one end of the resistor R16 and the gate of the N-type MOS tube Q3 through the resistor R12, the VDD pin is connected to the power supply VCC, and the other ends of the resistors R15 and R16 are connected to the power supply GND; Pin 1 and pin 4 of the transformer T are connected to the drain of the N-type MOS transistor Q2 and the drain of the N-type MOS transistor Q3 respectively, pin 2 and pin 3 are connected to one end of the capacitor C11 and the capacitor C12 connected in parallel, pin 8 is connected between the anode of the diode D2 and the cathode of the diode D5, pin 7 is connected between the anode of the diode D3 and the cathode of the diode D4, pin 6 is connected between the anode of the diode D7 and the cathode of the diode D9, and pin 5 is connected between the anode of the diode D8 and the cathode of the diode D10; the other end of the capacitor C11 and the capacitor C12 connected in parallel is connected to the power supply ground GND; The rectifier and voltage stabilizing circuit includes a diode D2, a diode D3, a diode D7 and a diode D8; the cathodes of the diode D2 and the diode D3 are connected to the cathode of the voltage regulator tube D1, and one end of the capacitor C3 and the capacitor C4; the anode of the voltage regulator tube D1 and the other end of the capacitor C3 are connected to one end of the resistor R9 and the base of the transistor Q1; the other end of the capacitor C4 is connected to the emitter of the transistor Q1, one end of the capacitor C7 and the power supply ground Gnd_ISO1; the diode D5 and the anode of the diode D4, the other end of the resistor R9, and the other end of the capacitor C7 are connected to the emitter of the transistor Q1, ... cathode of the diode D4, the other end of the resistor R9, and the other end of the capacitor C The cathodes of the diode D7 and the diode D8 are connected to the cathode of the voltage-stabilizing tube D6, and one end of the capacitor C8 and the capacitor C9; the anode of the voltage-stabilizing tube D8 and the other end of the capacitor C8 are connected to one end of the resistor R11 and the base of the transistor Q4; the other end of the capacitor C9 is connected to the emitter of the transistor Q4, one end of the capacitor C10 and the power ground Gnd_ISO2; the anodes of the diode D9 and the diode D10, the other end of the resistor R11, and the other end of the capacitor C10 are connected to the collector of the transistor Q4.

5. The silicon carbide MOSFET active Miller clamp circuit according to claim 1, characterized in that: The logic module includes an AND gate chip U5, a NOR gate chip U6, and a resistor R18; pin 1 of the AND gate chip U5 is connected to pin 1 of the NOR gate chip U6, pin 2 is connected to the pulse signal end through a resistor R19, pin 2 is also connected to the power supply ground GND through a capacitor C15, pin 3 is connected to the power supply ground GND, pin 4 is connected to pin 2 of the NOR gate chip U6, and pin 5 is connected to the Out pin of the LDO linear regulator U3; pin 5 of the NOR gate chip U6 is connected to the Out pin of the LDO linear regulator U3, pin 3 is connected to the power supply ground GND, and pin 4 is connected to the gate of the MOS tube Q5 through a resistor R18; the drain of the MOS tube Q5 is connected to the gate of the silicon carbide MOSFET tube, and the source is connected to the power ground VEE_ISO1.

6. The silicon carbide MOSFET active Miller clamp circuit according to claim 1, characterized in that: The comparison module includes a comparator U4 and a resistor R17; the non-phase input terminal of the comparator U4 is connected to the gate of the silicon carbide MOSFET tube, the output terminal is connected to one end of the resistor R17 and pin 1 of the gate chip U5, the power supply voltage input terminal is connected to the other end of the resistor R17 and the Out pin of the LDO linear regulator U3, and the power supply voltage output terminal is connected to the power supply ground GND.

7. The silicon carbide MOSFET active Miller clamp circuit according to claim 1, characterized in that: The drive module includes an isolation drive chip U7; the VCC1 pin of the isolation drive chip U7 is connected to the Out pin of the LDO linear regulator U3, and one end of the capacitor C17 and the capacitor C18 connected in parallel, the IN+ pin is connected to the pulse signal end through the resistor R20, the IN+ pin is also connected to the power supply ground GND through the capacitor C16, the IN- pin and the GND1 pin are connected to the power supply ground GND, the VEE2 pin is connected to the collector of the transistor Q1, and one end of the capacitor C21 and the capacitor C22 connected in parallel. The OUTL pin and the OUTH pin are connected to the gate of the silicon carbide MOSFET tube through the resistor R21 and the resistor R22 respectively, the VCC2 pin is connected to one end of the capacitor C4, and one end of the capacitor C19 and the capacitor C20 in parallel; the other end of the capacitor C17 and the capacitor C18 in parallel is connected to the power supply ground GND, the other end of the capacitor C19 and the capacitor C20 in parallel, and the other end of the capacitor C21 and the capacitor C22 in parallel are connected to the power ground GND and the power ground Gnd_ISO1.

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