Analog-to-digital conversion circuit, chip and electronic equipment

Abstract

The embodiment of the utility model provides an analog-to-digital conversion circuit, a chip and electronic equipment, the analog-to-digital conversion circuit comprises a sampling and holding module and a conversion module, the sampling and holding module comprises a capacitor array, and the common end of the capacitor array is connected with the input end of the conversion module; the switching network is used for accessing an input signal to the free end of one or more capacitors corresponding to the sampling control signal in the capacitor array based on the sampling control signal; a preset voltage is connected to the free ends of one or more capacitors corresponding to the test control signal in the capacitor array based on the test control signal; wherein the preset voltage is the voltage of a preset node in the analog-to-digital conversion circuit. According to the analog-to-digital conversion circuit, the test input used for the conversion module is generated based on the voltage of the internal node and the test control signal, a high-precision external input source is not needed to generate the test input, the test cost can be reduced, and the area and the power consumption of the analog-to-digital conversion circuit are basically not increased.

Description

Technical Field

[0001] The present application relates to the field of signal processing technology, and in particular to an analog-to-digital conversion circuit, a chip and an electronic device. Background Art

[0002] Analog-to-digital converter (ADC) circuits can be used to convert analog signals (such as voltage and current) into digital signals to quantize analog signals. ADC is an important functional module for communication, instrument measurement, and sensor control systems, and is widely used in the fields of analog integrated circuits and mixed analog and digital integrated circuits.

[0003] The analog-to-digital converter may include a sampling and holding circuit and a conversion circuit. The sampling and holding circuit may sample the analog input signal, and the conversion circuit may quantize the sampling result and generate a digital output signal. When the performance of the analog-to-digital converter is usually required to be tested, in the related art, when testing the performance of the conversion circuit, a high-precision external input source is required to generate a test input (i.e., an analog input signal for testing). In some cases, the output voltage of the external input source needs to be modified several times to generate multiple test inputs. This greatly increases the testing cost and also brings a lot of inconvenience. Utility Model Content

[0004] In view of the above problems, the embodiments of the present application provide an analog-to-digital conversion circuit, a chip and an electronic device to solve the above technical problems.

[0005] In the first aspect, the embodiment of the present application provides an analog-to-digital conversion circuit, including a sampling and holding module and a conversion module, wherein the sampling and holding module includes: a capacitor array, the common end of the capacitor array is connected to the input end of the conversion module; a switch network, used to: connect the input signal to the free end of one or more capacitors corresponding to the sampling control signal in the capacitor array based on a sampling control signal; connect the preset voltage to the free end of one or more capacitors corresponding to the test control signal in the capacitor array based on a test control signal; wherein the preset voltage is the voltage of a preset node inside the analog-to-digital conversion circuit. The analog-to-digital conversion circuit, when working normally, connects the input signal to the free end of one or more capacitors corresponding to the sampling control signal in the capacitor array through the switch network based on the sampling control signal, so as to sample the analog-to-digital input signal, and quantize it by the conversion module; when testing, connects the preset voltage of the preset node inside the analog-to-digital conversion circuit to the free end of one or more capacitors corresponding to the test control signal in the capacitor array through the switch network based on the test control signal, and generates a test input for the conversion module based on the voltage of the internal node and the test control signal, without the need for a high-precision external input source to generate the test input, can reduce the test cost, and basically does not increase the area and power consumption of the analog-to-digital conversion circuit.

[0006] In a second aspect, an embodiment of the present application further provides a chip, comprising the above-mentioned analog-to-digital conversion circuit.

[0007] In a third aspect, an embodiment of the present application further provides an electronic device, comprising the above-mentioned chip or analog-to-digital conversion circuit.

[0008] The analog-to-digital conversion circuit, chip and electronic device provided in the embodiments of the present application, when operating normally, connect the input signal to the free ends of one or more capacitors in the capacitor array corresponding to the sampling control signal through a switch network based on a sampling control signal, so as to sample the analog-to-digital input signal, and quantize it by a conversion module; when testing, connect the preset voltage of the preset node inside the analog-to-digital conversion circuit to the free ends of one or more capacitors in the capacitor array corresponding to the test control signal through a switch network based on a test control signal, and generate a test input for the conversion module based on the voltage of the internal node and the test control signal, without the need for a high-precision external input source to generate the test input, thereby reducing the testing cost and substantially not increasing the area and power consumption of the analog-to-digital conversion circuit.

[0009] These and other aspects of the present application will become more clearly understood in the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0011] Figure 1 A schematic structural diagram of an analog-to-digital conversion circuit provided in an embodiment of the present application is shown.

[0012] Figure 2a A structural schematic diagram of another analog-to-digital conversion circuit provided in an embodiment of the present application is shown.

[0013] Figure 2b A structural schematic diagram of another analog-to-digital conversion circuit provided in an embodiment of the present application is shown.

[0014] Figure 3 A schematic structural diagram of another analog-to-digital conversion circuit provided in an embodiment of the present application is shown.

[0015] Figure 4 A schematic structural diagram of a Σ-Δ analog-to-digital conversion circuit provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0016] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0017] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application.

[0018] In the embodiments of the present application, it should be noted that, in this article, relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0019] Moreover, the terms "comprises," "comprising," or any other variation thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0020] In the description of the embodiments of the present application, words such as "example" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "example" or "for example" in the embodiments of the present application is not to be interpreted as being more preferred or having more advantages than another embodiment or design. The use of words such as "example" or "for example" is intended to present relative concepts in a clear manner.

[0021] In addition, the "plurality" in the embodiments of the present application refers to two or more than two. In view of this, in the embodiments of the present application, "plurality" can also be understood as "at least two". "At least one" can be understood as one or more, for example, one, two or more. For example, including at least one means including one, two or more, and there is no limit on which ones are included. For example, including at least one of A, B and C, then A, B, C, A and B, A and C, B and C, or A, B and C can be included.

[0022] It should be noted that, in the embodiments of the present application, "and / or" describes the association relationship of the associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects before and after are in an "or" relationship.

[0023] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0024] In the circuit structure provided in the embodiments of the present application, the first node, the second node and other nodes do not represent actual existing components, but represent the junction points of related couplings in the circuit diagram, that is, these nodes are nodes formed by the equivalent junction points of related couplings in the circuit diagram.

[0025] In the embodiment of the present application, the switch can be an NMOS tube, a PMOS tube, or a combination of NMOS and PMOS, and can also be a bootstrap switch, which is not limited in the embodiment of the present application. The capacitor can be a MOM (Metal-Oxide-Metal) capacitor, a PIP (Poly Insulator Poly) capacitor, or other capacitors, which is not limited in the embodiment of the present application.

[0026] The present application embodiment provides an analog-to-digital conversion circuit, such as Figure 1 As shown, the analog-to-digital conversion circuit 100 may include a sampling and holding module 110 and a conversion module 120, wherein the sampling and holding module 110 may sample an analog input signal, and the conversion module 120 may quantize the sampling result and generate a digital output signal corresponding to the sampling result.

[0027] In the embodiments of the present application, Figure 1 As shown, the sampling and holding module 110 may include: a capacitor array 111 and a switch network 112. The common end of the capacitor array 111 is connected to the input end of the conversion module 120. It should be understood that the common end of the capacitor array 111 and the conversion module 120 may be directly or indirectly connected. For example, in some examples, a buffer amplifier may be further included between the common end of the capacitor array 111 and the input end of the conversion module 120, which is not limited in the embodiments of the present application.

[0028] The switch network 112 is used to connect the input signal to the free ends of one or more capacitors corresponding to the sampling control signal in the capacitor array 111 based on the sampling control signal, and the one or more capacitors sample the input signal, and the sampling result is output to the conversion module 120 through the common end of the capacitor array 111. The switch network 112 is also used to connect the preset voltage to the free ends of one or more capacitors corresponding to the test control signal in the capacitor array 111 based on the test control signal, and the one or more capacitors sample the preset voltage of the preset node inside the analog-to-digital conversion circuit to generate a test input, and the test input is output to the conversion module 120 through the common end of the capacitor array 111. The conversion module 120 converts the test input to test the conversion performance.

[0029] In the embodiment of the present application, the capacitance of the capacitor connected to the preset voltage can be controlled by the test control signal to generate a test input corresponding to the capacitance. The capacitance of the capacitor connected to the input signal can be controlled by the sampling control signal to be a predetermined sampling capacitance to sample the input signal.

[0030] In some embodiments, the preset voltage is a reference voltage of the analog-to-digital conversion circuit, and accordingly, the internal preset node is a reference voltage node. The reference voltage has a high precision, and the switch network 112 connects the reference voltage to the free ends of one or more capacitors corresponding to the test control signal in the capacitor array 111 based on the test control signal, and the reference voltage is sampled by the one or more capacitors, so as to form a high-precision test input. At this time, the total capacitance of the capacitor array 111 is equal to the sampling capacitance of the analog-to-digital conversion circuit, and the switch network 112 is used to connect the input signal to the free ends of all capacitors in the capacitor array 111 based on the sampling control signal, so as to sample according to the sampling capacitance of the analog-to-digital conversion circuit.

[0031] In some embodiments, the preset voltage is less than the reference voltage of the analog-to-digital conversion circuit. For example, the preset voltage is a voltage division of the reference voltage of the analog-to-digital conversion circuit, and the voltage division of the reference voltage can be generated by a voltage division module. If the total capacitance of the capacitor array is greater than the capacitance of the sampling capacitor, the generated test input can be kept within the input voltage range of the analog-to-digital conversion circuit. At this time, since the total capacitance of the capacitor array can be greater than the capacitance of the sampling capacitor, the number of capacitors included in the capacitor array 111 and the capacitance of each capacitor are more flexible, and the capacitor connected to the preset voltage can be more flexibly selected through the switch network 112, thereby generating a test input more flexibly. Among them, the switch network 112 connects the input signal to the free end of one or more capacitors in the capacitor array 111 based on the sampling control signal, and the total capacitance of the one or more capacitors is equal to the capacitance of the sampling capacitor of the analog-to-digital conversion circuit, so as to sample the input signal according to the capacitance of the sampling capacitor. The switch network 112 selects a capacitor connected to the preset voltage among all the capacitors in the capacitor array based on the test control signal to generate a test input.

[0032] Exemplarily, the sampling capacitor of the analog-to-digital conversion circuit 100 has a capacitance of Ccs, and the total capacitance of the capacitor array 111 can be set to Ccs, and the total capacitance of the capacitor array 111 is equal to the capacitance of the adopted capacitor. The capacitor array 111 may include j capacitors, and the capacitance of each capacitor may be the same as 1 / j*Ccs. Assume that the voltage value of the reference voltage is V REF Based on the test control signal, when the free ends of all capacitors in the capacitor array 111 are connected to the reference voltage, the test input is V REF , when the free end of a capacitor in the capacitor array 111 is connected to the reference voltage, the test input is 1 / j*V REF When the free ends of the two capacitors in the capacitor array 111 are connected to the reference voltage, the test input is 2 / j*V REF , and so on, a variety of test inputs proportional to the reference voltage can be generated based on the test control signal.

[0033] Exemplarily, the sampling capacitor of the analog-to-digital conversion circuit 100 has a capacitance of Ccs, and the total capacitance of the capacitor array 111 can be set to Ccs, and the total capacitance of the capacitor array 111 is equal to the capacitance of the adopted capacitor. If Ccs is expressed as 16C, that is, 16 unit capacitances. The capacitor array 111 may include 5 capacitors with capacitances of 8C, 4C, 2C, 1C, and 1C. Assuming that the voltage value of the reference voltage is V REF Based on the test control signal, when the free end of the capacitor with a capacitance of 8C in the capacitor array 111 is connected to the reference voltage, the test input is 1 / 2*V REF When the free end of the capacitor with a capacitance of 4C in the capacitor array 111 is connected to the reference voltage, the test input is 1 / 4*V REFWhen the free end of the capacitor with a capacitance of 2C in the capacitor array 111 is connected to the reference voltage, the test input is 1 / 8*V REF When the free end of the capacitor with a capacitance of 1C in the capacitor array 111 is connected to the reference voltage, the test input is 1 / 16*V REF When the free ends of the capacitors with capacitances of 1C and 2C in the capacitor array 111 are connected to the reference voltage, the test input is 3 / 16*V REF By analogy, a variety of test inputs proportional to the reference voltage can be generated based on the test control signal.

[0034] Figure 2a and Figure 2b FIG. 4 shows a block diagram of an analog-to-digital conversion circuit provided in an embodiment of the present application. Figure 2a and Figure 2b As shown, the analog-to-digital conversion circuit 200 may include a sampling and holding module 210 and a conversion module 220, wherein the sampling and holding module 210 may sample an analog input signal, and the conversion module 220 quantizes the sampling result and generates a digital output signal corresponding to the sampling result. In the embodiment of the present application, the analog-to-digital conversion circuit 200 is a single-ended input analog-to-digital conversion circuit.

[0035] like Figure 2a and Figure 2b As shown, the sampling and holding module 210 may include: a capacitor array and a switch network. The common end of the capacitor array is connected to the input end of the conversion module 220. It should be understood that the common end of the capacitor array and the conversion module 220 may be directly or indirectly connected. For example, in some examples, a buffer amplifier may be included between the common end of the capacitor array and the input end of the conversion module 220, which is not limited in the embodiments of the present application.

[0036] In some embodiments, Figure 2a and Figure 2b As shown, the switch network may include: a plurality of first switches, Figure 2a and Figure 2b The system includes n first switches, which are marked as S1-1 to S1-n, and one end of any first switch receives a preset voltage ( Figure 2a and Figure 2b The other end is connected to the free end of the capacitor corresponding to the first switch in the capacitor array, and the control end of any first switch receives the control bit corresponding to the first switch in the test control signal, and the first switch is turned on or off based on the control bit. Figure 2a and Figure 2b As shown, the capacitor array may include a plurality of capacitors, Figure 2a and Figure 2bThe test control signal includes n capacitors, which are marked as C1 to Cn. The first switches S1-1 to S1-n are connected to the capacitors C1 to Cn respectively. The test control signal may include n control bits, each of which controls a first switch, and the first switch is turned on or off based on the control bit.

[0037] In some embodiments, Figure 2a and Figure 2b As shown, the switch network may further include: a plurality of second switches, Figure 2a The circuit includes n second switches, which are marked as S2-2 to S2-n, respectively. One end of any second switch among the second switches S2-1 to S2-n receives the input signal VI, and the other end is connected to the free end of the capacitor corresponding to the second switch in the capacitor array. The control end of any second switch receives the control bit corresponding to the second switch in the sampling control signal, and the second switch is turned on or off based on the control bit. Figure 2a and Figure 2b As shown, the capacitor array includes multiple capacitors. Figure 2a and Figure 2b The sampling control signal includes n capacitors, which are marked as C1 to Cn. The second switches S2-1 to S2-n are connected to the capacitors C1 to Cn respectively. The sampling control signal may include n control bits, each of which controls a second switch, and the second switch is turned on or off based on the control bit.

[0038] In some embodiments, Figure 2a As shown, the switch network may further include: a third switch S3, connected between the common end of the capacitor array and the first voltage node (whose voltage is V1), the third switch S3 is turned on in the sampling phase and turned off in the holding phase; a fourth switch S4, connected between the common end of the capacitor array and the conversion module 220, the fourth switch S4 is turned off in the sampling phase and turned on in the holding phase.

[0039] In some embodiments, Figure 2b As shown, the switch network may further include: a plurality of fifth switches, Figure 2b As shown, n fifth switches are included, respectively marked as S5-1 to S5-n, and any fifth switch among the fifth switches S5-1 to S5-n is connected between the common end of the capacitor corresponding to the fifth switch in the capacitor array and the first voltage node, as shown in FIG. Figure 2b As shown, the fifth switches S5-1 to S5-n are respectively connected to the capacitors C1 to Cn, and any fifth switch is turned on in the sampling phase and turned off in the holding phase. Further, the switch network may also include: a plurality of sixth switches, Figure 2b As shown, n sixth switches are included, respectively marked as S6-1 to S6-n, and any sixth switch is connected between the common end of the capacitor corresponding to the sixth switch in the capacitor array and the conversion module 220, such as Figure 2bAs shown, the sixth switches S6 - 1 to S6 - n are connected to the capacitors C1 to Cn respectively; any sixth switch is disconnected in the sampling phase and is turned on in the holding phase.

[0040] In some embodiments, Figure 2a and Figure 2b As shown, the switch network may further include: a plurality of seventh switches, Figure 2a and Figure 2b The device shown includes n seventh switches, which are marked as S7-1 to S7-n, respectively. Any seventh switch is connected between the second voltage node (whose voltage is V2) and the free end of the capacitor corresponding to the seventh switch in the capacitor array. Figure 2a and Figure 2b The seventh switches S7 - 1 to S7 - n are respectively connected to the free ends of the capacitors C1 to Cn, and any seventh switch is disconnected in the sampling phase and turned on in the holding phase.

[0041] In the embodiment of the present application, the first voltage node and the second voltage node may be the same voltage node, and their voltages are the same, that is, V1 is equal to V2; the first voltage node and the second voltage node may also be different voltages, and their voltages are different, that is, V1 is not equal to V2. The first voltage node and the second voltage node may be power supply terminals, ground terminals, or common mode voltage terminals, etc. The embodiment of the present application does not limit this.

[0042] refer to Figure 2a and Figure 2b As shown, when the analog-to-digital conversion circuit 200 is working normally, the second switches S2-2 to S2-n are turned on or off by the sampling control signal to sample the input signal through the capacitor array, and at this time, the first switches S1-1 to S1-n remain disconnected. When the analog-to-digital conversion circuit 200 is tested, the first switches S1-2 to S1-n are turned on or off by the test control signal to sample the preset voltage (such as the reference voltage) through the capacitor array to generate a test input, and at this time, the second switches S2-2 to S2-n remain disconnected.

[0043] Figure 3 FIG. 4 shows a block diagram of an analog-to-digital conversion circuit provided in an embodiment of the present application. Figure 3 As shown, the analog-to-digital conversion circuit 300 may include a sampling and holding module 310 and a conversion module 320, wherein the sampling and holding module 310 may sample the analog input signal, and the conversion module 320 may quantize the sampling result and generate a digital output signal corresponding to the sampling result. The analog-to-digital conversion circuit 300 is a differential input analog-to-digital conversion circuit. Figure 3 As shown, the analog input signal includes a first analog input signal VIP and a second analog input signal VIN.

[0044] like Figure 3As shown, the sampling and holding module 310 may include: a capacitor array and a switch network. The capacitor array may include a first capacitor array and a second capacitor array, and the switch network may include a first switch network and a second switch network. The common end of the first capacitor array (whose voltage is VOP) is connected to the first input end of the conversion module 320. The common end of the second capacitor array (whose voltage is VON) is connected to the second input end of the conversion module 320.

[0045] In some embodiments, Figure 3 As shown, the first switch network may include: a plurality of first switches, Figure 3 The circuit includes 2k first switches, which are marked as S1PP-1 to S1PP-k and S1PN-1 to S1PN-k, one end of any first switch among the first switches S1PP-1 to S1PP-k receives a first reference voltage VREFP, and the other end is connected to a free end of a capacitor corresponding to the first switch in the first capacitor array, one end of any first switch among the first switches S1PN-1 to S1PN-k receives a second reference voltage VREFN, and the other end is connected to a free end of a capacitor corresponding to the first switch in the first capacitor array, and a control end of any first switch among the first switches S1P-1 to S1PP-k and S1PN-1 to S1PN-k receives a control bit corresponding to the first switch in a test control signal. Reference Figure 3 As shown, the first capacitor array may include a plurality of capacitors. Figure 3 The first capacitor array includes k capacitors, which are marked as CP1 to CPk. The first switches S1PP-1 to S1PP-k are connected to the capacitors C1 to Ck respectively, and the first switches S1PN-1 to S1PN-k are connected to the capacitors CP1 to CPk in the first capacitor array respectively.

[0046] Accordingly, if Figure 3 As shown, the second switch network may further include: a plurality of first switches, respectively marked as S1NP-1 to S1NP-k and S1NN-1 to S1NN-k, one end of any first switch among the first switches S1NP-1 to S1NP-k receiving the second reference voltage VREFN, and the other end connected to the free end of the capacitor corresponding to the first switch in the second capacitor array, one end of any first switch among the first switches S1NN-1 to S1NN-k receiving the first reference voltage VREFP, and the other end connected to the free end of the capacitor corresponding to the first switch in the second capacitor array, and the control end of any first switch among the first switches S1NP-1 to S1NP-k and S1NN-1 to S1NN-k receiving the control bit corresponding to the first switch in the test control signal. Reference Figure 3 As shown, the second capacitor array may include a plurality of capacitors. Figure 3The first switches S1NN-1 to S1NN-k are respectively connected to the capacitors CN1 to CNk in the second capacitor array.

[0047] In some embodiments, Figure 3 As shown, the first switch network may further include: a plurality of second switches, Figure 3 The first switch network may further include: a plurality of second switches, Figure 3 The circuit includes k second switches, which are marked as S2N-1 to S2N-k. One end of any second switch among the second switches S2P-1 to S2P-k receives the input signal VIP, and the other end is connected to the free end of the capacitor corresponding to the second switch in the first capacitor array. One end of any second switch among the second switches S2N-1 to S2N-k receives the input signal VIN, and the other end is connected to the free end of the capacitor corresponding to the second switch in the first capacitor array. The control end of any second switch receives the control bit corresponding to the second switch in the sampling control signal. Reference Figure 3 As shown, the first capacitor array may include k capacitors, respectively marked as CP1 to CPk, and the second switches S2P-1 to S2P-k are respectively connected to the capacitors CP1 to CPk in the first capacitor array; the second capacitor array may include k capacitors, respectively marked as CN1 to CNk, and the second switches S2N-1 to S2N-k are respectively connected to the capacitors CN1 to CNk in the second capacitor array. The sampling control signal may include 2k control bits, and each control bit controls a second switch.

[0048] In some embodiments, Figure 3 As shown, the first switch network may further include: a plurality of fifth switches, Figure 3 The second switch network may further include: a plurality of fifth switches, Figure 3 The fifth switches shown in FIG. 1 include k fifth switches, which are marked as S5N-1 to S5N-k. Any fifth switch among the fifth switches S5P-1 to S5P-k is connected between the common end of the capacitor corresponding to the fifth switch in the first capacitor array and the first voltage node, as shown in FIG. Figure 3 As shown, the fifth switches S5P-1 to S5P-k are respectively connected to the capacitors CP1 to CPk in the first capacitor array. Any fifth switch among the fifth switches S5N-1 to S5N-k is connected between the common end of the capacitor corresponding to the fifth switch in the second capacitor array and the first voltage node, as shown in FIG. Figure 3As shown, the fifth switches S5N-1 to S5N-k are connected to the capacitors CN1 to CNk in the second capacitor array respectively. Any of the fifth switches S5P-1 to S5P-k and S5N-1 to S5N-k is turned on in the sampling phase and turned off in the holding phase.

[0049] Further, such as Figure 3 As shown, the first switch network may further include: a plurality of sixth switches, Figure 3 The second switch network may further include: a plurality of sixth switches, Figure 3 The figure shows k sixth switches, which are marked as S6N-1 to S6N-k. Any sixth switch among the sixth switches S6P-1 to S6P-k is connected between the common end of the capacitor corresponding to the sixth switch in the first capacitor array and the input end of the conversion module 220, as shown in FIG. Figure 3 As shown, the sixth switches S6P-1 to S6P-k are respectively connected to the capacitors CP1 to CPk in the first capacitor array. Any sixth switch among the sixth switches S6N-1 to S6N-k is connected between the common end of the capacitor corresponding to the sixth switch in the second capacitor array and the input end of the conversion module 220, as shown in FIG. Figure 3 As shown, the sixth switches S6N-1 to S6N-k are connected to the capacitors CN1 to CNk in the second capacitor array respectively. Any of the sixth switches S6P-1 to S6P-k and S6N-1 to S6N-k is turned off in the sampling phase and turned on in the holding phase.

[0050] In some embodiments, Figure 3 As shown, the first switch network may further include: a plurality of seventh switches, Figure 3 The second switch network may further include: a plurality of seventh switches, Figure 3 The figure shows k seventh switches, which are marked as S7N-1 to S7N-k. Any of the seventh switches S7P-1 to S7P-k is connected between the second voltage node (whose voltage is V2) and the free end of the capacitor corresponding to the seventh switch in the first capacitor array, as shown in FIG. Figure 3 As shown, the seventh switches S7P-1 to S7P-k are respectively connected to the free ends of the capacitors CP1 to CPk in the first capacitor array. Any of the seventh switches S7N-1 to S7N-k is connected between the second voltage node (whose voltage is V2) and the free end of the capacitor corresponding to the seventh switch in the second capacitor array, as shown in FIG. Figure 3 As shown, the seventh switches S7N-1 to S7N-k are respectively connected to the free ends of the capacitors CN1 to CNk in the second capacitor array. Any seventh switch is disconnected in the sampling phase and turned on in the holding phase.

[0051] refer to Figure 3 As shown, when the analog-to-digital conversion circuit 300 works normally, the second switches S2P-1 to S2P-k and S2P-1 to S2P-k are turned on or off by the sampling control signal to sample the first input signal through the first capacitor array and sample the second input signal through the second capacitor array. At this time, the first switches S1PP-1 to S1PP-k and S1PN-1 to S1PN-k, S1NP-1 to S1NP-k and S1NN-1 to S1NN-k remain disconnected. When testing the analog-to-digital conversion circuit 200, the first switches S1PP-1 to S1PP-k and S1PN-1 to S1PN-k, S1NP-1 to S1NP-k and S1NN-1 to S1NN-k are turned on or off by a test control signal to sample a preset voltage (e.g., a reference voltage) through the first capacitor array to generate a first test input, and a preset voltage (e.g., a reference voltage) is sampled through the second capacitor array to generate a second test input. At this time, the second switches S2P-1 to S2P-k and S2P-1 to S2P-k remain disconnected.

[0052] Figure 4 FIG. 4 shows a block diagram of an analog-to-digital conversion circuit provided in an embodiment of the present application. Figure 4 As shown, the module conversion circuit 400 includes a sampling and holding module 410 and a conversion module 420, wherein the sampling and holding module 410 can sample the analog input signal, and the conversion module 420 quantizes the sampling result and generates a digital output signal corresponding to the sampling result.

[0053] like Figure 4 As shown, the sampling and holding module 410 may include: a capacitor array 411 and a switch network 412. The common end of the capacitor array 411 is connected to the input end of the conversion module 420. It should be understood that the common end of the capacitor array 411 and the conversion module 420 may be directly or indirectly connected. For example, in some examples, a buffer amplifier may be further included between the common end of the capacitor array 411 and the input end of the conversion module 420, which is not limited in the embodiments of the present application.

[0054] like Figure 4 As shown, the module conversion circuit 400 is a Sigma Delta Analog to Digital Converter (SDADC), and the conversion module 420 may include an integrator 421 , a quantizer 422 , a digital-to-analog converter (DAC) 423 and a digital filter 424 .

[0055] The test of the module conversion circuit 400 generally includes testing offset error, gain error, integral nonlinearity, etc. And when testing integral nonlinearity, it is necessary to modify the test voltage several times to obtain an integral nonlinearity curve. In an embodiment of the present application, when working normally (i.e., performing analog-to-digital conversion on an analog-to-digital input signal), the switch network 412 can access the input signal to the free end of one or more capacitors corresponding to the sampling control signal in the capacitor array 411 based on the sampling control signal, and the input signal is sampled by the one or more capacitors, and the sampling result is output to the conversion module 420 (e.g., integrator 421) through the common end of the capacitor array 411. During the test, the switch network 412 can access the preset voltage to the free end of one or more capacitors corresponding to the test control signal in the capacitor array 411 based on the test control signal, and the preset voltage of the preset node inside the analog-to-digital conversion circuit is sampled by the one or more capacitors, and a test input is generated, and the test input is output to the conversion module 420 through the common end of the capacitor array 411. When testing integral nonlinearity, multiple test inputs can be generated by adjusting the test control signal to select different capacitors or capacitor quantities to improve test efficiency.

[0056] The present application embodiment also provides a chip, the chip includes the above-mentioned analog-to-digital conversion circuit. The chip is also called an integrated circuit (Integrated Circuit, IC), and the chip can be but is not limited to a SOC (System on Chip, chip-level system) chip, a SIP (system in package, system-level packaging) chip. When the chip is working normally, the input signal is connected to the free end of one or more capacitors corresponding to the sampling control signal in the capacitor array through a switch network based on a sampling control signal, and the analog-to-digital input signal is sampled and quantized by a conversion module; when testing, the preset voltage of the preset node inside the analog-to-digital conversion circuit is connected to the free end of one or more capacitors corresponding to the test control signal in the capacitor array based on a test control signal through a switch network, and a test input for the conversion module is generated based on the voltage of the internal node and the test control signal, and no high-precision external input source is required to generate the test input, so that the test cost can be reduced, and the area and power consumption of the analog-to-digital conversion circuit are substantially not increased.

[0057] The embodiment of the present application also provides an electronic device, which includes a device body and a chip as described above disposed in the device body. The electronic device may be, but is not limited to, a weight scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a human body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a car charger, an adapter, a display, a USB (Universal Serial Bus) docking station, a stylus, a true wireless headset, a car central control screen, a car, a smart wearable device, a mobile terminal, and a smart home device. Smart wearable devices include, but are not limited to, smart watches, smart bracelets, and cervical massagers. Mobile terminals include, but are not limited to, smart phones, laptops, tablet computers, and POS (point of sales terminal). Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart sweepers, and smart lights. When the electronic device is in normal operation, the input signal is connected to the free ends of one or more capacitors in the capacitor array corresponding to the sampling control signal through the switch network based on the sampling control signal, so as to sample the analog-to-digital input signal, and the analog-to-digital input signal is quantized by the conversion module; when testing, the preset voltage of the preset node inside the analog-to-digital conversion circuit is connected to the free ends of one or more capacitors in the capacitor array corresponding to the test control signal through the switch network based on the test control signal, and the test input for the conversion module is generated based on the voltage of the internal node and the test control signal. There is no need for a high-precision external input source to generate the test input, which can reduce the test cost and basically does not increase the area and power consumption of the analog-to-digital conversion circuit.

[0058] The above are only preferred embodiments of the present application, and are not intended to limit the present application in any form. Although the present application has been disclosed as above with preferred embodiments, it is not intended to limit the present application. Any technical personnel in the field can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present application. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. An analog-to-digital conversion circuit, characterized in that: The invention comprises a sampling and holding module and a conversion module, wherein the sampling and holding module comprises: A capacitor array, a common end of the capacitor array is connected to an input end of the conversion module; Switching networks for: Connecting the input signal to the free ends of one or more capacitors in the capacitor array corresponding to the sampling control signal based on the sampling control signal; Connecting a preset voltage to the free ends of one or more capacitors in the capacitor array corresponding to the test control signal based on the test control signal; The preset voltage is the voltage of a preset node inside the analog-to-digital conversion circuit.

2. The analog-to-digital conversion circuit according to claim 1, characterized in that: The switch network comprises: A plurality of first switches, one end of any first switch receives the preset voltage, and the other end is connected to the free end of the capacitor corresponding to the first switch in the capacitor array, and the first switch is turned on or off according to the control bit corresponding to the first switch in the test control signal.

3. The analog-to-digital conversion circuit according to claim 2, characterized in that: The switch network comprises: A plurality of second switches, one end of any second switch receives the input signal, and the other end is connected to the free end of the capacitor corresponding to the second switch in the capacitor array, and the second switch is turned on or off according to the control bit corresponding to the second switch in the sampling control signal.

4. The analog-to-digital conversion circuit according to claim 1, characterized in that: The switch network further comprises: a third switch connected between the common terminal of the capacitor array and the first voltage node, the third switch being turned on in a sampling phase and turned off in a holding phase; A fourth switch is connected between the common end of the capacitor array and the conversion module, and the fourth switch is disconnected in the sampling phase and turned on in the holding phase.

5. The analog-to-digital conversion circuit according to claim 1, characterized in that: The switch network further comprises: a plurality of fifth switches, any one of which is connected between a common end of a capacitor corresponding to the fifth switch in the capacitor array and the first voltage node, and any one of which is turned on in a sampling phase and turned off in a holding phase; A plurality of sixth switches, any one of which is connected between a common end of a capacitor corresponding to the sixth switch in the capacitor array and the conversion module, and the sixth switch is disconnected in a sampling phase and turned on in a holding phase.

6. The analog-to-digital conversion circuit according to claim 1, characterized in that: The switch network further comprises: A plurality of seventh switches, any one of which is connected between the second voltage node and a free end of a capacitor in the capacitor array corresponding to the seventh switch, the seventh switch being disconnected in a sampling phase and turned on in a holding phase.

7. The analog-to-digital conversion circuit according to any one of claims 1 to 6, characterized in that: The preset voltage is a reference voltage.

8. The analog-to-digital conversion circuit according to any one of claims 1 to 6, characterized in that: Also includes: The voltage division module is used to generate a divided voltage of a reference voltage, and the preset voltage is the divided voltage.

9. A chip, characterized in that: The analog-to-digital conversion circuit comprises any one of claims 1 to 8.

10. An electronic device, characterized in that: The invention comprises a device body and the chip as claimed in claim 9 arranged in the device body.

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