TRIAC device
By introducing multiple semiconductor regions into the TRIAC design and forming series resistors, the problem of insufficient sensitivity and commutation performance in high voltage applications is solved, and the sensitivity and commutation performance improvement under high voltage conditions is achieved.
Patent Information
- Application Number
- CN202421209638.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Priority Date
- 2023-05-31
- Filing Date
- 2024-05-30
- Publication Date
- 2025-05-13
- Estimated Expiration
- 2034-05-30
AI Technical Summary
In high voltage applications, the sensitivity and commutation performance of TRIAC are affected by the shortened free carrier lifetime and memory area caused by the increase in semiconductor material thickness, resulting in reduced sensitivity, slower shutdown time and insufficient commutation performance.
By introducing a plurality of semiconductor regions into the design of the TRIAC, including a third N-type region, a second P-type region, a second N-type region, a first P-type region, a first N-type region, a fourth N-type region and a fifth N-type region, and forming a series resistance through the doping type and distribution of these regions, the sensitivity and commutation performance of the TRIAC are improved.
This design improves the sensitivity and commutation performance of TRIAC under certain operating conditions without causing a significant reduction in sensitivity under other operating conditions, and is suitable for high voltage applications.
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Figure CN222869294U_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of TRIACs, and in particular to a gate design of a TRIAC for improving ratio commutation sensitivity. Background Art
[0002] Figure 1 A TRIAC (Triode Alternating Current), whose schematic diagram is shown in , is a three-terminal semiconductor device that acts as a bidirectional switch. When a trigger signal is applied to the gate terminal (G) of the TRIAC, the TRIAC can conduct and control the flow of current in either direction between its first main terminal (MT1) and its second main terminal (MT2).
[0003] A TRIAC is effectively formed by two thyristors Th1 and Th2 connected in parallel but with opposite polarity. It is designed to provide full-wave control of an AC circuit. A TRIAC can be triggered into conduction by applying a small positive or negative current at its gate terminal (G) relative to its first main terminal (MT1). Once a TRIAC is triggered, it continues to conduct until the current flowing through it drops below the TRIAC's holding current level, or when the AC waveform approaches zero (near the zero crossing point).
[0004] The performance of a TRIAC is affected by its sensitivity and commutation characteristics. Sensitivity refers to the level of gate current required to trigger the TRIAC into conduction. In contrast, commutation refers to the ability of the TRIAC to change from a conducting state to a non-conducting state when the current through the TRIAC drops below the holding current and the voltage is reapplied with the opposite polarity. Commutation also involves the maximum rate of drop in load current that is allowed to turn off the TRIAC; if the load current drops too quickly, the TRIAC may not be able to turn off and remain conducting into the next polarity.
[0005] In a TRIAC, there is a trade-off between commutation and sensitivity due to the inherent properties of the semiconductor materials used in its construction. Enhanced commutation capability, allowing faster transitions between the conducting and non-conducting states, can be achieved by shortening the free carrier lifetime or by design. However, these solutions usually come at the expense of reduced sensitivity.
[0006] As the voltage rating of the TRIAC increases, the device is subjected to higher voltage stresses, and therefore the thickness of the semiconductor material needs to be increased to withstand these higher voltages. This increase in thickness results in a shortened free-carrier lifetime and an increased storage area, which can lead to reduced sensitivity, slower turn-off times, and insufficient commutation performance. To counteract this effect, design changes are needed to increase sensitivity and maintain proper commutation in thicker semiconductor materials.
[0007] However, the design changes typically required for proper commutation can further reduce the sensitivity of the TRIAC, making control at low gate currents more challenging. The trade-off between commutation and sensitivity, exacerbated by increased thickness for higher voltage processing, is a limitation in conventional TRIAC design and operation, especially for high voltage applications.
[0008] In view of this, further development is needed. Utility Model Content
[0009] An object of the present invention is to provide an improved TRIAC.
[0010] A TRIAC is disclosed herein, comprising first and second main terminal contacts and a gate terminal contact. The TRIAC further comprises a plurality of semiconductor regions stacked along a first axis and extending laterally along an intersecting second axis, defining a first region, a second region and an intermediate region.
[0011] The plurality of semiconductor regions include the following regions. The third N-type region overlies the second main terminal contact, extends laterally through the second region and partially through the middle region. The second P-type region overlies the second main terminal contact, extends laterally through the first region, is partially located above the third N-type region in the middle region, and is located above the third N-type region in the second region. The second N-type region overlies the second P-type region, extends laterally across the first region, the middle region, and the second region. The first P-type region overlies the second N-type region, extends laterally across the first region, the middle region, and the second region. The first N-type region partially overlies the first P-type region and partially extends laterally through the first region. The fourth N-type region partially overlies the first P-type region and partially extends laterally through the middle region. The fifth N-type region partially overlies the first P-type region and partially extends laterally through the first region and the middle region.
[0012] A portion of the first main terminal contact is arranged on the first N-type region in the first region, and another portion is arranged on the first P-type region in the second region. The gate terminal contact is partially arranged on the first P-type region and the fourth N-type region in the middle region.
[0013] A first thyristor is formed in the first region, and a second thyristor is formed in the second region. The first thyristor is formed by a first N-type region, a first P-type region, a second N-type region, and a second P-type region. The second thyristor is formed by a third N-type region, a second P-type region, a second N-type region, and a first P-type region. A gate terminal contact is connected to the first P-type region and the fourth N-type region to control the flow of current between the first main terminal contact and the second main terminal contact by modulating the operation of the first thyristor and the second thyristor within the TRIAC. The fifth N-type region is located between the first N-type region and the fourth N-type region and serves as a series resistor between the gate terminal contact and the first main terminal contact, thereby improving the sensitivity and commutation of the TRIAC under certain operating conditions without causing a significant reduction in the sensitivity of the TRIAC under other operating conditions.
[0014] The first thyristor and the second thyristor are configured to operate in the first quadrant, the second quadrant, the third quadrant, and the fourth quadrant based on the polarity of the voltage applied across the first main terminal and the second main terminal and the polarity of the current applied between the gate terminal and the first main terminal. The presence of the fifth N-type region reduces the gate trigger current in the second and third operating quadrants, and increases the critical rise rate of the off-state current of the TRIAC when the TRIAC operates with a negative power current through Th2, thereby increasing the sensitivity and improving the commutation when the TRIAC operates in the I-V+ region.
[0015] The first N-type region, the third N-type region, the fourth N-type region and the fifth N-type region are heavily doped, the first P-type region and the second P-type region are moderately doped, and the second N-type region is lightly doped.
[0016] A TRIAC is also disclosed herein, comprising a first main terminal contact, a second main terminal contact, and a gate terminal contact. The TRIAC also includes a first thyristor, the first thyristor including a PNP transistor and an NPN transistor, wherein the base of the NPN transistor is connected to the collector of the PNP transistor, and the base of the PNP transistor is connected to the collector of the NPN transistor. The emitter-base junction of the NPN transistor has a forward biased behavior modeled by a parallel diode and a pinch-off resistor. Like the first thyristor, the second thyristor is formed by a PNP transistor and an NPN transistor, wherein the base of the NPN transistor is connected to the collector of the PNP transistor, and the base of the PNP transistor is connected to the collector of the NPN transistor. In both cases, a shared semiconductor region forms the collector of the NPN transistor and the base of the PNP transistor. The gate terminal contact is connected to the base of the NPN transistor included in the first thyristor, thereby allowing the current flow between the first main terminal contact and the second main terminal contact to be controlled by modulating the operation of the NPN transistor and the PNP transistor. A series resistance is formed between the gate terminal contact and the first main terminal contact, thereby improving the sensitivity and commutation of the TRIAC under certain operating conditions without causing a significant reduction in sensitivity under other operating conditions.
[0017] The first thyristor is formed in the first semiconductor region, the second thyristor is formed in the second semiconductor region, and a shared semiconductor region is formed in a third semiconductor region between the first semiconductor region and the second semiconductor region.
[0018] The first thyristor is a two-lead thyristor, the second thyristor is a two-lead thyristor, and the shared semiconductor region is a common base region of the first thyristor and the second thyristor.
[0019] A TRIAC may be used in a system for controlling AC power. The system may include a TRIAC having a first main terminal contact connected to an AC power source and a second main terminal contact connected to a load, wherein a control circuit is coupled to a gate terminal contact of the TRIAC. The control circuit is configured to modulate the operation of the TRIAC and control the delivery of power from the AC power source to the load based on a set of operating conditions of the load. The load may be at least one of a motor, a motor starter, a solid-state relay, an AC switching transistor device, or a lighting system.
[0020] Also disclosed herein is a TRIAC comprising a first layer doped with a first conductivity type, a first region doped with a second conductivity type at a surface of the first layer, wherein the first region forms a cathode of a first thyristor of the TRIAC, and the first layer forms a gate of the first thyristor. A cathode metal layer contacts the first region. A second region is doped with the second conductivity type at a surface of the first layer. A gate metal layer contacts the second region and contacts the surface of the first layer. A third region is doped with the second conductivity type and extends from the second region in a position between the first region and the position where the gate metal layer contacts the surface of the first layer.
[0021] The first region, the second region and the third region of the second conductivity type are heavily doped. The first layer of the first conductivity type is moderately doped.
[0022] A TRIAC is also disclosed herein, comprising a semiconductor substrate, a second P-type region formed in the semiconductor substrate, and a third N-type region formed in the semiconductor substrate adjacent to the second P-type region. The TRIAC also comprises a second N-type region formed in the semiconductor substrate on the second P-type region, a first P-type region formed in the semiconductor substrate on the second N-type region, a first N-type region formed in the semiconductor substrate adjacent to the first P-type region; and a fourth N-type region formed in the semiconductor substrate adjacent to the first P-type region at the same level as the first N-type region and spaced apart therefrom. A fifth N-type region is formed in the semiconductor substrate, the fifth N-type region being at the same level as the first N-type region and the fourth N-type region and being located between the first N-type region and the fourth N-type region but spaced apart therefrom, and adjacent to the first P-type region. The first main terminal contact has a first portion arranged on the first N-type region and a second portion arranged on the first P-type region. The second main terminal contact is arranged on the second P-type region and the third N-type region. The gate terminal contact is partially arranged on the first P-type region and partially arranged on the fourth N-type region.
[0023] The first N-type region, the third N-type region, the fourth N-type region and the fifth N-type region are heavily doped, the first P-type region and the second P-type region are moderately doped, and the second N-type region is lightly doped.
[0024] The fifth N-type region is formed as a finger extending from the fourth N-type region.
[0025] Also disclosed herein is a method of manufacturing an improved TRIAC device, the method comprising forming a TRIAC device. The formation of the TRIAC device is performed by doping a first layer with a first conductivity type, the concentration of the doping of the first layer being greater toward an upper portion thereof than toward a lower portion thereof. The formation of the TRIAC device further comprises doping a first region with a second conductivity type at a surface of the first layer, such that the first region forms a cathode of a first thyristor of the TRIAC and the first layer forms a gate of the first thyristor. The formation of the TRIAC device also comprises forming a cathode metal layer in contact with the first region, doping a second region with a second conductivity type at a surface of the first layer, and forming a gate metal layer in contact with the second region and in contact with a surface of the first layer. The method comprises improving the sensitivity and commutation of the TRIAC under certain operating conditions by forcing a current to pass through a lower portion of the first layer to increase the resistance along a current path between the gate metal layer and the cathode metal layer, without causing a significant reduction in sensitivity under other operating conditions.
[0026] By doping the third region with the second conductivity type so that the third region extends from the second region at a position between the first region and the position where the gate metal layer contacts the surface of the first layer, current can be forced to pass through a lower portion of the first layer as it travels along a current path between the gate metal layer and the cathode metal layer.
[0027] The doping level of the third region having the second conductivity type may optionally be greater than the doping level of the second region having the second conductivity type.
[0028] The first region may be moderately doped, an upper portion of the first layer may be moderately doped, and the second region may be heavily doped, wherein the third region is heavily doped.
[0029] Thus, in some embodiments, an improved TRIAC is provided. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figure 1 It is a schematic diagram of TRIAC.
[0031] Figure 2A yes Figure 1 Cross-sectional view of a TRIAC design.
[0032] Figure 2B is a cross-sectional view of the TRIAC design disclosed in this article.
[0033] Figure 2C yes Figure 2A A close-up view of the layout of the gate and surrounding area of a TRIAC design.
[0034] Figure 2D yes Figure 2BA close-up view of the layout of the gate and surrounding area of a TRIAC design.
[0035] Figure 2E yes Figure 2A A perspective view of the layout of the gate and surrounding area of a TRIAC design.
[0036] Figure 2F yes Figure 2B A perspective view of the layout of the gate and surrounding area of a TRIAC design.
[0037] Figure 3 yes Figure 1 The equivalent BJT model of the SCR (thyristor Th1 or thyristor Th2) design.
[0038] Figure 4A yes Figure 2A The equivalent parallel diode / resistor circuit of the gate to first main terminal path in a TRIAC design.
[0039] Figure 4B yes Figure 2B The equivalent parallel diode / resistor circuit of the gate to first main terminal path in a TRIAC design.
[0040] Figure 5 is a graph showing Q2 sensitivity and commutation performance of the TRIAC design of FIG. 2 when operating in the I-V+ mode of operation.
[0041] Figure 6 is a graph showing Q3 sensitivity and commutation performance of the TRIAC design of FIG. 2 when operating in the I+V- mode of operation.
[0042] Figure 7 is to use Figure 2B Schematic diagram of the TRIAC designed system. DETAILED DESCRIPTION
[0043] The following disclosure enables those skilled in the art to make and use the subject matter described herein. The general principles outlined in this disclosure can be applied to embodiments and applications other than those described in detail above without departing from the spirit and scope of the disclosure. It is not intended to limit the disclosure to the embodiments shown, but rather to give it the widest scope consistent with the principles and features disclosed or proposed herein.
[0044] In this disclosure, various semiconductor regions will be described as “lightly doped,” “moderately doped,” or “heavily doped.” A sample doping concentration of a lightly doped region may be 1×10 14 Up to 1×10 17 Atom / cm 3 The sample doping concentration in the medium doping region can be 1×10 17 Up to 5×1018 Atom / cm 3 The sample doping concentration in the heavily doped region can be 5×10 18 Up to 1×10 21 Atom / cm 3 However, other doping concentrations may be used.
[0045] The present disclosure may be best understood by comparing the TRIAC designs herein to conventional TRIAC designs. Figure 2A , which is a cross-sectional view of a conventional TRIAC formed using double mesa technology. Figure 2B Shown in FIG. 1 is a cross-sectional view of a TRIAC disclosed herein that is also formed using dual-mesa technology.
[0046] First, we will describe Figure 2A and Figure 2B The common areas of the various designs will then be discussed. Figure 2A and Figure 2B A cross-sectional view of a TRIAC, in which it can be seen that the TRIAC is formed by various doped regions of a semiconductor substrate stacked between a first main terminal and a second main terminal. The device is constructed using a double mesa technology process, which involves creating two separate flat-top structures or mesas within the n-type region N2 of the semiconductor substrate. A passivation glass layer 1 is formed over the sidewalls of the mesas. The various doped regions in the substrate are created by adding specific impurities to obtain different charge carrier concentrations. The cross-section of the TRIAC is divided into the left side (thyristor 1, called Th1), the middle (gate region), and the right side (thyristor 2, called Th2). Th1 has the anode at the bottom and the cathode at the top, while Th2 has the cathode at the bottom and the anode at the top.
[0047] From the bottom up, the TRIAC starts with the metal layer that forms the MT2 contact, which serves as the main terminal 2 (MT2) or anode 2 (A2) and is the common terminal of the two thyristors in the TRIAC. On top of it, in the center part and to the right, is the N3 region - an N-type region of the semiconductor substrate heavily doped with donor impurities - forming the cathode region of Th2. The P2 region, a P-type region of the semiconductor substrate moderately doped with acceptor impurities, is located on top of the MT2 contact in the center part and to the left, and extends over the N3 region in the other part of the center and to the right. The N2 region, another N-type region of the semiconductor substrate lightly doped with donor impurities, is located on the P2 region and extends completely through from left to right. The P1 region, a P-type region of the semiconductor substrate moderately doped with acceptor impurities, also extends completely through from left to right. The N1 region, an N-type region of the semiconductor substrate heavily doped with donor impurities, is located at the top of the left side of the P1 region. The N4 region, an N-type region of the semiconductor heavily doped with donor impurities, is located at the top of the middle of the P1 region. At the very top of the TRIAC is the metal layer that forms the MT1 contact.
[0048] In the bipolar junction transistor (BJT) model of a silicon controlled rectifier (SCR), Figure 3 As shown in , the base of the NPN transistor is connected to the collector of the PNP transistor, and the base of the PNP transistor is connected to the collector of the NPN transistor. The emitter of each transistor is connected to one of the two main terminals of the SCR. To trigger the SCR into conduction, a positive current is injected between the gate (G) and one of the main terminals (MT1). This positive gate current directly polarizes the base-emitter junction of the NPN transistor, causing the device to activate.
[0049] A TRIAC can be conceptualized as two SCRs (or thyristors Th1 and Th2) connected in parallel but with opposite polarity. This configuration allows the TRIAC to conduct in both directions. However, the gate of Th2 is not directly accessible, so its control is based on the ability to inject carriers from the gate through the PN junction into the main conduction region.
[0050] Figure 4A The equivalent circuit model shown in Figure 1 illustrates the Figure 2A The gate-to-MT1 characteristics of a prior art TRIAC. The model has two PN junctions, D1 and D2, which participate in triggering quadrants Q1 and Q4 and Q2 and Q3 respectively.
[0051] Resistor Rpp represents a power pinched resistor, which is a resistance associated with the controlled current flow through the base-emitter junction of the NPN transistor. Resistor Rl represents a leakage resistor, which is associated with the small amount of leakage current that does not flow through the base-emitter junction when the TRIAC is turned off. These resistors (Rpp and Rl) are connected in parallel with diode D1. These resistors are similar to the off-state resistances between the base and emitter of the NPN transistor.
[0052] Diode D1 illustrates the forward biased behavior of the base-emitter junction of the NPN transistor. The anode of diode D1 is connected to the gate terminal G and its cathode is connected to MT1.
[0053] Additionally, a parallel combination of resistor Rpg and diode D2 is connected in series between gate terminal G and MT1. Resistor Rpg represents the gate pinch resistance, which is related to the resistance encountered when the TRIAC is triggered by a negative gate signal, affecting the current flowing through the base-emitter junction of the NPN transistor.
[0054] Figure 4B The equivalent circuit model shown in Figure 1 illustrates the Figure 2B The gate to MT1 characteristics of a TRIAC. The model has two PN junctions D1 and D2, which participate in triggering quadrants Q1 and Q4 and Q2 and Q3 respectively.
[0055] In this model, a resistor Rs representing the resistance associated with the N5 region is connected in series between the gate terminal G and the parallel combination of resistors Rpp, R1 and diode D1. This resistance Rs associated with the N5 region corresponds to the base-emitter path of the NPN transistor in the off state of the TRIAC. The N5 region affects the sensitivity of the gate signal and its resistance directly affects the performance characteristics of the TRIAC.
[0056] Resistor Rpp represents the power pinch resistor, which is the resistance associated with the controlled current flow through the base-emitter junction of the NPN transistor. Resistor Rl represents the leakage resistor, which is associated with the small amount of leakage current that does not flow through the base-emitter junction when the TRIAC is turned off. These resistors (Rpp and Rl) are connected in parallel with diode D1 between resistor Rs (N5 region) and MT1. These resistors are similar to the off-state resistance between the base and emitter of the NPN transistor.
[0057] Diode D1 illustrates the forward biased behavior of the base-emitter junction of the NPN transistor. The anode of diode D1 is connected to resistor Rs (N5 region) and its cathode is connected to MT1.
[0058] Additionally, a parallel combination of resistor Rpg and diode D2 is connected in series between gate terminal G and MT1. Resistor Rpg represents the gate pinch resistance, which is related to the resistance encountered when the TRIAC is triggered by a negative gate signal, affecting the current flowing through the base-emitter junction of the NPN transistor.
[0059] Figure 2C Shows Figure 2A A close-up view of the layout of a prior art TRIAC. Figure 2A and Figure 2C , note that, Figure 2A is a cross-sectional view along line AB (wherein the origin O is shown), and Figure 2C is a top view of a prior art TRIAC, where line OA is Figure 2C The X axis of the line OB is Figure 2C Observe the Y axis in particular, N1 and N4. Figure 2A Another close-up view of the layout of a prior art TRIAC can be seen at Figure 2E , here is shown the above Figure 3 and Figure 4A Description of various resistors.
[0060] and Figure 2B Compared to the conventional layout of the TRIAC shown in Figure 2D Provided Figure 2B A close-up view of the layout of the TRIAC design. Note Figure 2B is a cross-sectional view along line AB (wherein the origin O is shown), and Figure 2D A top view of the TRIAC is shown, wherein line OA forms the X-axis and line OB forms the Y-axis. Figure 2B Another close-up view of the layout of a prior art TRIAC can be seen at Figure 2F , here is shown the above Figure 4B Description of various resistors.
[0061] Pay special attention to the N1 and N4 regions, especially the newly introduced N5 region. Note that the N4 and N5 regions constitute a single continuous region, with N5 acting as an extension or finger from N4. This configuration forms a resistive current path, accounting for the resistance Rs.
[0062] In other words, Figure 2B The N+ band, N5 region, is added to the TRIAC, thus changing the current path. Figure 2AUnlike the conventional design where current flows along the surface of P1, the addition of the N5 region forces the current to pass through the lower P-doped region below the N5 band (e.g., the upper part of P1 is more highly doped than the lower part of P1). This change increases the resistance, effectively closing the direct path between the gate and the MT1 electrode. Therefore, the value of the resistor Rs is combined with the drain resistance Rl (yielding Rs+Rl), providing a Figure 2B The present invention provides greater control over the sensitivity and performance characteristics of the TRIAC. In fact, it has been found that the placement of this N+ region N5 advantageously increases the sensitivity of the TRIAC under certain operating conditions and improves the commutation of the TRIAC under certain operating conditions without causing the consequence of reduced sensitivity under other operating conditions. This will now be explained in detail.
[0063] TRIAC has four different operating regions or quadrants. The quadrant in which the TRIAC operates depends on the polarity of the voltage across the first main terminal (MT1) and the second main terminal (MT2) relative to MT1 and the polarity of the voltage applied between the gate terminal (G) and MT1. The sensitivity of the TRIAC varies in the four quadrants, mainly due to differences in semiconductor region interactions and internal device structures. The four quadrants are usually labeled Q1, Q2, Q3, and Q4, and they correspond to different combinations of voltage polarity and gate signal polarity, as follows:
[0064] Q1 (quadrant 1, or I+V+) operation occurs when both the gate and MT2 are positive with respect to MT1. The TRIAC turns on when sufficient gate current flows (injected directly from the gate into MT1), polarizing the PN junction D1 and triggering the power thyristor. The voltage across the main terminals is positive. The TRIAC remains on until the load current through it drops below the holding current, at which point it turns off. Q1 is the most sensitive quadrant because the positive gate signal and direct triggering that enhances the positive voltage across the main terminals helps activate the TRIAC with a small gate current.
[0065] Q2 (Quadrant 2 or I-V+) operation occurs when the gate is negative with respect to MT1 and MT2 is positive with respect to MT1. In this quadrant, the triggering of the thyristor is indirect: a negative gate current is applied to the gate from MT1, polarizing a PN junction (D2 in the schematic) located in the gate region. The injection from this diode then triggers the power thyristor. Since D2 is not part of the power thyristor, this triggering is considered indirect. When sufficient gate current flows, the TRIAC turns on, and the voltage across the main terminals is positive. The TRIAC remains on until the current through it drops below the holding current, at which point it turns off. Therefore, due to this indirect triggering, the sensitivity in Q2 is lower than that in Q1.
[0066] Q3 (Quadrant 3, or IV-) operates similarly to Q2 in that the triggering of the thyristor is also indirect, with the gate and MT2 being negative with respect to MT1. Again, a negative gate current is applied to the gate from MT1, first polarizing the PN junction (D2) in the gate region, which then indirectly triggers the power thyristor. When sufficient gate current flows, the TRIAC turns on, and the voltage across the main terminals is negative. The TRIAC remains on until the current through it drops below the holding current, at which point it turns off. Therefore, the sensitivity in Q3 is almost similar to that in Q2 due to the same indirect triggering mechanism.
[0067] Q4 (Quadrant 4 or I+V-) operation occurs when the gate is positive with respect to MT1 and MT2 is negative with respect to MT1. When sufficient gate current flows, the TRIAC turns on, and the voltage across the main terminals is negative. The TRIAC remains on until the current through it drops below the holding current, at which point it turns off. Q4 is the least sensitive quadrant and requires a larger gate current to trigger the TRIAC.
[0068] TRIAC can be switched on in all four quadrants, but the sensitivity and triggering characteristics differ between them. In particular, quadrants Q2 and Q3 are most commonly used due to the convenience they offer: only a single polarity of gate current is required to manage switching, regardless of the voltage polarity.
[0069] The sensitivity of a TRIAC is a function of the gate trigger current (IGT), which is the minimum current required at the gate of the TRIAC to turn the TRIAC on and trigger conduction. The lower the IGT, the higher the sensitivity, while the higher the IGT, the lower the sensitivity.
[0070] During commutation, the critical rate of rise of off-state current (dI / dt_c) parameter specifies the maximum rate of current change that the TRIAC can safely handle during the off period.
[0071] Now let’s discuss the effect of the N+ layer N5 on sensitivity – the addition of the N+ layer (N5) affects the gate trigger current (IGT) required to turn on the TRIAC. Figure 5 As shown in , IGT decreased significantly in Q2, indicating a significant increase in sensitivity. Figure 5 As observed in Figure 2, IGT in Q3 also decreases, indicating that sensitivity in this quadrant has also increased. The increased sensitivity means that the TRIAC can be triggered with smaller gate currents in Q2 and Q3, which is beneficial for efficient control of a variety of loads.
[0072] Now let’s discuss the effect of N+ layer N5 on commutation. The presence of N+ layer (N5) has an effect on the critical rate of rise of off-state current (dI / dt_c) during commutation. In Q2, if Figure 5 As shown in , the dI / dt_c in I-V+ operation increases slightly, indicating a slight improvement in commutation performance. Figure 6 As shown in , dI / dt_c in I+V- operation remains essentially unchanged. These results indicate that the additional N5 layer helps the TRIAC handle the maximum current change rate during turn-off in I-V+ operation without compromising its performance.
[0073] The N+ layer (N5) helps balance the performance of the TRIAC across the Q2 and Q3 quadrants. Although the IGT increases when operating in Q1, meaning the sensitivity in Q1 is reduced, this is not significant because Q1 is already the most sensitive quadrant. By adding the N5 layer, the TRIAC becomes more versatile in a variety of applications in controlling both resistive and inductive loads because the sensitivity and commutation performance become more consistent across quadrants.
[0074] Finally, it will be apparent that modifications and variations may be made to what is described and illustrated herein without departing from the scope of the present disclosure. Although the present disclosure has been described with respect to a TRIAC formed using a dual mesa technique, it is noted that the basic principles presented herein are not limited to this particular manufacturing method. The TRIAC disclosed herein may also be implemented using other semiconductor manufacturing techniques, such as planar techniques in which flat layers of material are built on a substrate. Similarly, top glass processes or other techniques employing glass layers or coatings may also be suitable for implementing the TRIAC designs disclosed herein.
[0075] The above-mentioned TRIAC offers advantages in high voltage handling, making it suitable for a variety of devices and applications. These include but are not limited to power supply circuits, motor control systems and dimming circuits.
[0076] Another notable application of TRIAC is motor starter. These devices typically require robust and efficient components capable of handling high voltages, such as the 1200V capability of the TRIAC disclosed herein. In a motor starter, a TRIAC is used to control the power supply, thereby achieving smooth starting and operation of the motor.
[0077] Solid-state relays (SSRs) also benefit greatly from the TRIAC implementation described in this article. In an SSR, the TRIAC acts as a switch, properly controlling the flow of power without the use of additional mechanical parts, thereby improving reliability and durability.
[0078] In addition, a gate opener system may use such a TRIAC in its control circuitry. In such a system, the TRIAC is used to manage the power supply to the motor, thereby providing efficient and reliable operation of the gate opener mechanism.
[0079] Furthermore, TRIAC can be integrated into ACST (AC Switching Transistor) devices used in various electrical and industrial applications.
[0080] Figure 7 An example is shown in FIG, in which the MT1 terminal of the TRIAC is connected to an AC power source 101, and the MT2 terminal of the TRIAC is connected to a load 102. The load 102 may be, for example, a motor, a motor starter, a solid-state relay, an AC switching transistor device, a lighting system, or other suitable load. The control circuit 103 is connected to the gate terminal G of the TRIAC and modulates the operation of the TRIAC by controlling the voltage applied to the gate terminal G. In turn, this regulates the power supplied to the load 102, helping to ensure that it operates within specified parameters.
[0081] In an embodiment, a method for manufacturing an improved TRIAC device includes: forming a TRIAC device by: doping a first layer with a first conductivity type, the doping of the first layer being greater in concentration toward an upper portion thereof than toward a lower portion thereof; doping a first region with a second conductivity type at a surface of the first layer so that the first region forms a cathode of a first thyristor of the TRIAC device and the first layer forms a gate of the first thyristor; forming a cathode metal layer in contact with the first region; doping a second region with the second conductivity type at the surface of the first layer; and forming a gate metal layer in contact with the second region and in contact with the surface of the first layer; and improving the sensitivity and commutation of the TRIAC device under certain operating conditions by forcing current to pass through a lower portion of the first layer, without causing a significant reduction in sensitivity under other operating conditions.
[0082] In some embodiments, by doping the third region with the second conductivity type so that the third region extends from the second region in a position between the first region and the position where the gate metal layer contacts the surface of the first layer, the current is forced to pass through the lower portion of the first layer as it travels along the current path between the gate metal layer and the cathode metal layer.
[0083] In some embodiments, a doping level of the third region having the second conductivity type is equal to a doping level of the second region having the second conductivity type.
[0084] In some embodiments, the first region is heavily doped; wherein the upper portion of the first layer is moderately doped; wherein the second region is heavily doped; and wherein the third region is heavily doped.
[0085] Although the present disclosure has been described using a limited number of embodiments, those skilled in the art having benefit of the present disclosure may conceive of other embodiments that do not depart from the scope of the disclosure. In addition, those skilled in the art may conceive of embodiments that represent various combinations of the embodiments disclosed herein in various ways.
Claims
1. A TRIAC device, characterized in that: include: a first main terminal contact and a second main terminal contact, and a gate terminal contact; a plurality of semiconductor regions stacked along a first axis and extending laterally along an intersecting second axis, defining a first region, a second region, and an intermediate region; The plurality of semiconductor regions include: a third N-type region overlying the second main terminal contact and extending laterally through the second region and partially through the intermediate region; a second P-type region overlying the second main terminal contact, extending laterally through the first region, partially located above the third N-type region in the middle region, and located above the third N-type region in the second region; a second N-type region overlying the second P-type region and extending laterally across the first region, the middle region, and the second region; A first P-type region overlying the second N-type region and extending laterally across the first region, the middle region, and the second region; a first N-type region partially overlying the first P-type region and partially extending laterally through the first region; a fourth N-type region partially overlying the first P-type region and partially extending laterally through the middle region; and a fifth N-type region partially overlying the first P-type region and partially extending laterally through the first region and the middle region; Wherein a portion of the first main terminal contact is arranged on the first N-type region in the first zone, and another portion is arranged on the first P-type region in the second zone; wherein the gate terminal contact is partially arranged on the first P-type region and the fourth N-type region in the middle zone.
2. The TRIAC device according to claim 1, wherein a first thyristor is formed in the first region, and a second thyristor is formed in the second region; wherein the first thyristor is formed by the first N-type region, the first P-type region, the second N-type region and the second P-type region; wherein the second thyristor is formed by the third N-type region, the second P-type region, the second N-type region and the first P-type region; wherein the gate terminal contact is connected to the first P-type region and the fourth N-type region to control current flow between the first main terminal contact and the second main terminal contact by modulating operation of the first and second thyristors within the TRIAC device; and The fifth N-type region is located between the first N-type region and the fourth N-type region, and serves as a series resistor between the gate terminal contact and the first main terminal contact, thereby improving the sensitivity and commutation of the TRIAC device under certain operating conditions without causing a significant decrease in the sensitivity of the TRIAC device under other operating conditions.
3. The TRIAC device according to claim 2, wherein the first and second thyristors are configured to operate in a first quadrant, a second quadrant, a third quadrant, and a fourth quadrant based on the polarity of a voltage applied across the first and second main terminals and the polarity of a voltage applied between the gate terminal and the first main terminal; The presence of the fifth N-type region reduces the gate trigger current in the second quadrant and the third quadrant, and increases the critical rise rate of the off-state current of the TRIAC device when the TRIAC device operates with a negative power current through the second thyristor, thereby increasing the sensitivity and improving the commutation when the TRIAC device operates in the I-V+ region. 4 . The TRIAC device of claim 1 , wherein the first N-type region, the third N-type region, the fourth N-type region and the fifth N-type region are heavily doped; and wherein the first P-type region and the second P-type region are moderately doped.
5. A TRIAC device, characterized in that: include: Semiconductor substrates; a second P-type region formed in the semiconductor substrate; a third N-type region formed in the semiconductor substrate and adjacent to the second P-type region; a second N-type region formed in the semiconductor substrate on the second P-type region; a first P-type region formed in the semiconductor substrate on the second N-type region; a first N-type region formed in the semiconductor substrate and adjacent to the first P-type region; a fourth N-type region formed in the semiconductor substrate, adjacent to the first P-type region, at the same level as the first N-type region and spaced apart therefrom; as well as a fifth N-type region formed in the semiconductor substrate, adjacent to the first P-type region, at the same level as the first N-type region and the fourth N-type region and between but spaced apart from the first N-type region and the fourth N-type region; a first main terminal contact having a first portion disposed on the first N-type region and a second portion disposed on the first P-type region; a second main terminal contact, arranged on the second P-type region and the third N-type region; as well as A gate terminal contact is partially disposed on the first P-type region and partially disposed on the fourth N-type region.
6. The TRIAC device of claim 5, wherein the first N-type region and the third N-type region are heavily doped; wherein the first P-type region and the second P-type region are moderately doped; wherein the second N-type region and the fourth N-type region are heavily doped; and wherein the fifth N-type region is heavily doped. 7 . The TRIAC device of claim 5 , wherein the fifth N-type region is formed as a finger extending from the fourth N-type region.