SiC VDMOSFET structure with improved dynamic characteristics

Abstract

The utility model relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a SiC VDMOSFET (Vertical Double-diffused Metal Oxide Semiconductor Field Effect Transistor) structure for improving dynamic characteristics, which comprises a SiC VDMOSFET structure formed by mutually connecting a plurality of VDMOS cells in parallel, each VDMOS cell comprises a drain electrode, a metal source electrode, a grid electrode and a semiconductor epitaxial layer; the semiconductor epitaxial layer comprises a substrate layer, a diffusion layer, an N well layer, a P well layer and a depletion layer; wherein the N well layer is isolated from the diffusion layer by the P well layer, and the N well layer is in ohmic short circuit with the metal source electrode. According to the utility model, the charge conduction performance of the depletion layer is changed by doping phosphorus elements with different concentrations in the depletion layer region, the depletion layer has a better charge attraction effect in a conduction state, and the JFET region is reduced to the third region of the depletion layer along with the increase of the grid voltage, so that the conductivity of a charge channel is multiplied, and the conductivity of the charge channel is improved. Therefore, bidirectional optimization of switching loss and switching EMI noise can be realized, and the purpose of improving the dynamic characteristics of the device is achieved.

Description

Technical Field

[0001] The utility model relates to the technical field of MOS semiconductors, in particular to a SiCVDMOSFET structure for improving dynamic characteristics. Background Art

[0002] SiC VDMOSFET is a siliconized carbon vertical double diffused metal oxide semiconductor field effect transistor. It uses siliconized carbon (SiC) as a semiconductor material and has a vertical structure and double diffusion characteristics, which makes SiC VDMOSFET increasingly used in power electronics, automobiles, aerospace, renewable energy and other fields.

[0003] The existing patent discloses a shielded gate MOSFET structure with improved dynamic characteristics (publication number CN216597597U), including a semiconductor substrate, the semiconductor substrate includes a first conductive type epitaxial layer and a groove arranged inside the semiconductor substrate, the upper part of the groove includes a gate polysilicon and a gate oxide layer, the lower part includes a shielded gate polysilicon and a thick oxide layer, a first floating polysilicon is provided between the gate polysilicon and the shielded gate polysilicon, the first floating polysilicon is isolated from the gate polysilicon and the shielded gate polysilicon by an oxide layer, and / or a second floating polysilicon is provided between the gate polysilicon and the source metal, and the second floating polysilicon is isolated from the gate polysilicon by an oxide layer. In the technology disclosed in the patent, when the depletion layer of the JFET region is formed, when the gate voltage is increased or decreased by changing, the width of the JFET region does not change significantly, which will make the formed channel insufficient to control the current size, and at this time, the VDMOS semiconductor switch response time is slow and the current conduction effect is insufficient. Summary of the invention

[0004] The main technical problem solved by the utility model is to provide a SiC VDMOSFET structure with improved dynamic characteristics, which solves the problems in the above-mentioned background technology.

[0005] To solve the above technical problems, according to one aspect of the utility model, more specifically, a SiC VDMOSFET structure with improved dynamic characteristics includes a SiC VDMOSFET structure composed of a plurality of VDMOS cells connected in parallel, wherein the VDMOS cells include a drain, a metal source, a gate, and a semiconductor epitaxial layer; the semiconductor epitaxial layer includes a substrate layer, a diffusion layer, an N-well layer, a P-well layer, and a depletion layer;

[0006] The N-well layer and the diffusion layer are isolated by the P-well layer, and the N-well layer is ohmically short-circuited with the metal source electrode;

[0007] The depletion layer includes a depletion layer 1, a depletion layer 2 and a depletion layer 3;

[0008] The substrate layer in a single VDMOS cell is prepared by ion implantation with a small amount in the middle and an excess amount on both sides, and the cross-sectional profile of the substrate layer is concave in the middle; wherein the concave area of ​​the substrate layer corresponds to the position of the second depletion layer and has the same profile ratio.

[0009] Furthermore, a gate oxide layer is deposited between the surface of the gate and the metal source and the semiconductor epitaxial layer.

[0010] Furthermore, the P-well layer includes a lightly doped P-well layer one, a lightly doped P-well layer three, a heavily doped P-well layer four, a heavily doped P-well layer one, a heavily doped P-well layer two, a heavily doped P-well layer three and a lightly doped P-well layer two.

[0011] Furthermore, the doping concentrations of the heavily doped P-well layer 1, the heavily doped P-well layer 2, and the heavily doped P-well layer 3 are increased step by step.

[0012] Furthermore, the heavily doped P-well layer 1, the heavily doped P-well layer 2, the heavily doped P-well layer 3 and the lightly doped P-well layer 2 between adjacent VDMOS cells are in contact with each other and are integrated as one.

[0013] Furthermore, the cross-sectional profiles of the lightly doped P-well layer 3 and the heavily doped P-well layer 4 are both in an 'L' shape.

[0014] Furthermore, when the gate is connected to a gate voltage, charges inside the lightly doped P-well layer move under the intervention of the gate electric field and form a charge channel, and the charge channel connects the depletion layer and the N-well layer.

[0015] Furthermore, the doping concentrations of the second depletion layer, the third depletion layer and the first depletion layer increase step by step.

[0016] Furthermore, the depletion layer 1 and the N-well layer have the same phosphorus doping concentration, and the depletion layer 1 and the lightly doped P-well layer 1 have the same cross-sectional profile thickness.

[0017] Furthermore, the cross-sectional areas of the second depletion layer, the third depletion layer and the first depletion layer decrease exponentially.

[0018] The beneficial effects of the SiC VDMOSFET structure with improved dynamic characteristics of the utility model are as follows:

[0019] 1. The utility model changes the charge conduction performance of the JFET region by doping phosphorus elements of different concentrations into the JFET region. In the on state, the JFET region has a better charge attraction effect. At this time, the conductivity of the charge channel will increase exponentially, so that the switching loss and the switching EMI noise can be optimized in both directions, thereby achieving the purpose of improving the dynamic characteristics of the device.

[0020] 2. The utility model designs a multi-level P-well layer between adjacent VDMOS cells, which can reduce the diffusion of charges in the P-well layer into adjacent VDMOS cells and increase the charge conduction stability performance of the SiC VDMOSFET.

[0021] 3. In the present invention, the doping concentration of the JFET region changes with different depths, so that the N-well layer connected by the formed charge channel and the JFET region have the advantage of minimum on-resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The utility model is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0023] Figure 1 This is a schematic diagram of the structure of SiC VDMOSFET in the utility model;

[0024] Figure 2 It is a schematic diagram of the structure of a single VDMOS cell in the utility model;

[0025] Figure 3 It is a partial schematic diagram of a single VDMOS cell in the present invention.

[0026] In the figure: 1. drain; 2. substrate layer; 3. diffusion layer; 4. metal source; 5. gate oxide layer; 6. gate; 7. N-well layer; 8. depletion layer one; 9. lightly doped P-well layer one; 10. heavily doped P-well layer one; 11. heavily doped P-well layer two; 12. heavily doped P-well layer three; 13. lightly doped P-well layer two; 14. depletion layer two; 15. depletion layer three; 16. lightly doped P-well layer three; 17. heavily doped P-well layer four. DETAILED DESCRIPTION

[0027] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other without conflict.

[0028] like Figure 1-3As shown, according to one aspect of the utility model, a SiCVDMOSFET structure with improved dynamic characteristics is provided, including a SiC VDMOSFET structure composed of a plurality of VDMOS cells connected in parallel, the VDMOS cell including a drain 1, a metal source 4, a gate 6 and a semiconductor epitaxial layer; the semiconductor epitaxial layer includes a substrate layer 2, a diffusion layer 3, an N-well layer 7, a P-well layer and a depletion layer, and phosphorus elements of different concentrations are doped in the depletion layer region, thereby changing the charge conduction performance of the depletion layer, and the depletion layer has a better charge attraction effect in the on state, and as the gate voltage increases, its JFET region will be reduced to the depletion layer three 15 region, at which time the conductivity of the charge channel will be doubled. Among them, the N-well layer 7 and the diffusion layer 3 are isolated by the P-well layer, and the N-well layer 7 and the metal source 4 are ohmically shorted, so that when the gate 6 is connected to the gate voltage state, the P-well layer will form a channel, and the channel will connect the N-well layer and the diffusion layer 3 to achieve conduction between the drain 1 and the metal source 4.

[0029] The depletion layer includes a first depletion layer 8 , a second depletion layer 14 and a third depletion layer 15 .

[0030] Among them, the doping concentration of the depletion layer 8 and the N-well layer 7 is 6-7×10 18 mol / cm 3 ;

[0031] The doping concentration of the depletion layer 214 is 2 to 4×10 17 mol / cm 3 ;

[0032] The doping concentration of depletion layer 315 is 7~9×10 17 mol / cm 3 ;

[0033] The doping concentration of the diffusion layer 3 is 5 to 9×10 16 mol / cm 3 .

[0034] The substrate layer 2 in a single VDMOS cell is prepared by ion implantation with a small amount in the middle and an excess amount on both sides, and the cross-sectional profile of the substrate layer 2 is concave in the middle; wherein the concave region of the substrate layer 2 corresponds to the position of the depletion layer 214, and the proportion of the profile is the same (e.g. Figure 2 As shown), the depletion layer 2 14 is similarly embedded in the concave portion, but a diffusion layer 3 is provided between the depletion layer 2 14 and the substrate layer 2. This spacing ensures that the gate-drain will not be easily broken down after the voltage is connected.

[0035] In this embodiment, a gate oxide layer 5 is deposited between the surface of the gate 6 and the metal source 4 and the semiconductor epitaxial layer.

[0036] In this embodiment, the P-well layer includes a lightly doped P-well layer 19, a lightly doped P-well layer 3 16, a heavily doped P-well layer 4 17, a heavily doped P-well layer 10, a heavily doped P-well layer 2 11, a heavily doped P-well layer 3 12 and a lightly doped P-well layer 2 13, and the doping concentrations of the heavily doped P-well layer 10, the heavily doped P-well layer 2 11 and the heavily doped P-well layer 3 12 increase step by step, and the heavily doped P-well layer 10, the heavily doped P-well layer 2 11, the heavily doped P-well layer 3 12 and the lightly doped P-well layer 2 13 between adjacent VDMOS cells are in contact with each other and are integrated as a whole.

[0037] The doping concentration of the heavily doped P well layer 10 is 2 to 4×10 18 mol / cm 3 ;

[0038] The doping concentration of the heavily doped P well layer 11 is 3.8 to 7×10 18 mol / cm 3 ;

[0039] The doping concentration of the heavily doped P well layer 12 is 6 to 7×10 18 mol / cm 3 ;

[0040] The doping concentration of the lightly doped P well layer 9 is 7.6 to 9×10 16 mol / cm 3 ;

[0041] The doping concentration of the lightly doped P well layer 16 is 5 to 8×10 16 mol / cm 3 ;

[0042] The doping concentration of the heavily doped P well layer 17 is 1 to 4×10 18 mol / cm 3 .

[0043] In this embodiment, the cross-sectional profiles of the lightly doped P-well layer 3 16 and the heavily doped P-well layer 4 17 are both in an 'L' shape, and when the gate 5 is connected to the gate voltage, the internal charges of the lightly doped P-well layer 1 9 move under the intervention of the gate electric field and form a charge channel, and the charge channel connects the depletion layer and the N-well layer 7. When the gate voltage is increased, the width of the JFET region is reduced, resulting in the formation of the channel and enhanced conductivity.

[0044] In this embodiment, the doping concentrations of the depletion layer 14, the depletion layer 15 and the depletion layer 18 increase step by step, the depletion layer 18 has the same phosphorus doping concentration as the N-well layer 7, and the cross-sectional profile thickness of the depletion layer 18 is the same as that of the lightly doped P-well layer 9. The cross-sectional profile areas of the depletion layer 14, the depletion layer 15 and the depletion layer 18 decrease exponentially. Since the doping concentration of the depletion layer 18 is the same as that of the N-well layer 7, and the profile height of the depletion layer 18 is similar to that of the lightly doped P-well layer 9, the N-well layer 7 connected by the formed charge channel and the depletion layer have the advantage of minimum on-resistance.

[0045] Of course, the above description is not a limitation of the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions or substitutions made by ordinary technicians in this technical field within the essential scope of the present invention also fall within the protection scope of the present invention.

Claims

1. A SiC VDMOSFET structure with improved dynamic characteristics, characterized in that: The invention comprises a SiC VDMOSFET structure composed of a plurality of VDMOS cells connected in parallel, wherein the VDMOS cell comprises a drain (1), a metal source (4), a gate (6) and a semiconductor epitaxial layer; the semiconductor epitaxial layer comprises a substrate layer (2), a diffusion layer (3), an N-well layer (7), a P-well layer and a depletion layer; The N-well layer (7) and the diffusion layer (3) are isolated by a P-well layer, and the N-well layer (7) and the metal source electrode (4) are ohmically short-circuited; The depletion layer comprises a depletion layer 1 (8), a depletion layer 2 (14) and a depletion layer 3 (15); The substrate layer (2) in a single VDMOS cell is prepared by ion implantation with a small amount in the middle and an excess amount on both sides, and the cross-sectional profile of the substrate layer (2) is concave in the middle; wherein the concave region of the substrate layer (2) corresponds to the position of the second depletion layer (14) and has the same profile ratio.

2. The SiC VDMOSFET structure with improved dynamic characteristics according to claim 1, characterized in that: A gate oxide layer (5) is deposited between the surface of the gate (6), the metal source (4) and the semiconductor epitaxial layer.

3. The SiC VDMOSFET structure with improved dynamic characteristics according to claim 1, characterized in that: The P-well layer includes a lightly doped P-well layer one (9), a lightly doped P-well layer three (16), a heavily doped P-well layer four (17), a heavily doped P-well layer one (10), a heavily doped P-well layer two (11), a heavily doped P-well layer three (12) and a lightly doped P-well layer two (13).

4. The SiC VDMOSFET structure with improved dynamic characteristics according to claim 3, characterized in that: The doping concentrations of the heavily doped P-well layer 1 (10), the heavily doped P-well layer 2 (11), and the heavily doped P-well layer 3 (12) are increased step by step.

5. The SiC VDMOSFET structure with improved dynamic characteristics according to claim 4, characterized in that: The heavily doped P well layer 1 (10), the heavily doped P well layer 2 (11), the heavily doped P well layer 3 (12) and the lightly doped P well layer 2 (13) between adjacent VDMOS cells are in contact with each other and are integrated as a whole.

6. The SiC VDMOSFET structure with improved dynamic characteristics according to claim 3, characterized in that: The cross-sectional profiles of the lightly doped P-well layer three (16) and the heavily doped P-well layer four (17) are both in an 'L' shape.

7. The SiC VDMOSFET structure with improved dynamic characteristics according to claim 3, characterized in that: When the gate (6) is connected to a gate voltage state, the internal charges of the lightly doped P-well layer (9) move under the intervention of the gate electric field and form a charge channel, wherein the charge channel connects the depletion layer and the N-well layer (7).

8. The SiC VDMOSFET structure with improved dynamic characteristics according to claim 1, characterized in that: The doping concentrations of the depletion layer 2 (14), the depletion layer 3 (15) and the depletion layer 1 (8) increase step by step.

9. The SiC VDMOSFET structure with improved dynamic characteristics according to claim 1, characterized in that: The depletion layer 1 (8) has the same phosphorus doping concentration as the N-well layer (7), and the depletion layer 1 (8) has the same cross-sectional thickness as the lightly doped P-well layer 1 (9).

10. The SiC VDMOSFET structure with improved dynamic characteristics according to claim 1, characterized in that: The cross-sectional areas of the depletion layer 2 (14), the depletion layer 3 (15) and the depletion layer 1 (8) decrease exponentially.

Images