Signal processing system

Abstract

The utility model provides a signal processing system which comprises an S5000C-64 processor, an FPGA chip, a gigabit network controller, a CPLD chip, an optical module unit and a network communication connector, a first data transmission interface of the S5000C-64 processor is electrically connected with the FPGA chip, a second data transmission interface of the S5000C-64 processor is electrically connected with the gigabit network controller, and the CPLD chip is electrically connected with the optical module unit. A general input / output interface of the S5000C-64 processor is electrically connected with the CPLD chip, the optical module unit is electrically connected with the FPGA chip, and the network communication connector is electrically connected with the gigabit network controller. Due to the fact that the main processor adopts the high-performance Fengyun S5000C-64 processor, the requirement for beyond-visual-range and high-resolution radar signal processing can be better met, the device is a domestic device, the safety and reliability of data processing can be effectively guaranteed, meanwhile, through connection with the FPGA chip, a plurality of optical ports can be provided outwards, different optical fiber transmission requirements can be met, and the device has the advantages of being simple in structure, convenient to use and high in practicability. A reliable network communication function is provided for the system by connecting the gigabit network controller, and a control function is provided for the system by connecting the CPLD chip.

Description

Technical Field

[0001] The utility model relates to the technical field of processors, in particular to a signal processing system. Background Art

[0002] Over-the-horizon radar (OTHR) can detect and track targets beyond the horizon with high resolution. This radar system is widely used in ocean monitoring, scientific research, production and other fields. With the emergence of over-the-horizon and high-resolution radars, the amount of data that needs to be collected is increasing, and the requirements for data real-time are also increasing. This puts higher demands on high-performance and highly reliable signal processing systems. However, the signal processing systems in related technologies are often based on central processing units (CPUs) and graphics processing units (GPUs), which are suitable for general signal processing needs and cannot meet the signal processing needs of over-the-horizon and high-resolution radars. Therefore, it is necessary to develop a high-performance and highly reliable signal processing system. Utility Model Content

[0003] The utility model provides a signal processing system, aiming to solve the problem that the signal processing system in the related technology cannot well meet the requirements of over-the-horizon and high-resolution radar signal processing.

[0004] In order to solve the above technical problems, the first aspect of the utility model provides a signal processing system, including: an S5000C-64 processor, an FPGA chip, a gigabit network controller, a CPLD chip, multiple optical modules and a network communication connector, the first data transmission interface of the S5000C-64 processor is electrically connected to the FPGA chip, the second data transmission interface of the S5000C-64 processor is electrically connected to the gigabit network controller, the general input and output interface of the S5000C-64 processor is electrically connected to the CPLD chip, the multiple optical module units are all electrically connected to the FPGA chip, and the network communication connector is electrically connected to the gigabit network controller.

[0005] Furthermore, the signal processing system also includes a plurality of network transformers, and the plurality of network transformers are electrically connected to the Gigabit network controller and the network communication connector respectively.

[0006] Furthermore, it includes an MPO optical module and multiple LC optical modules, the MPO optical module is electrically connected to the FPGA chip through an Aurora bus, and the multiple LC optical modules are electrically connected to the FPGA chip through a RocketIO bus.

[0007] Furthermore, the signal processing system also includes a storage unit electrically connected to the S5000C-64 processor.

[0008] Furthermore, the storage unit includes a first DDR5 memory, a second DDR5 memory, a third DDR5 memory, a fourth DDR5 memory, a fifth DDR5 memory, a sixth DDR5 memory, a seventh DDR5 memory and an eighth DDR5 memory, which are electrically connected to the S5000C-64 processor respectively.

[0009] Furthermore, the signal processing system also includes an M.2 hard disk connector, and the third data transmission interface of the S5000C-64 processor is electrically connected to the M.2 hard disk connector.

[0010] From the above description, it can be seen that the utility model adopts S5000C-64 processor, Gigabit network controller, FPGA chip, CPLD chip and optical module to form a signal processing system. Among them, the main processor adopts the high-performance Tengyun S5000C-64 processor, which can better meet the beyond-visual-range and high-resolution radar signal processing requirements. The device is a domestic device, which can effectively ensure the security and reliability of data processing. At the same time, the optical module is connected through the FPGA chip, and multiple optical ports are provided to the outside to adapt to different optical fiber transmission requirements. The network communication connector is connected through the Gigabit network controller, and a Gigabit network interface is provided to the outside to provide the system with reliable network communication functions. The CPLD chip is connected to provide more controllable functions for the signal processing system. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a structural schematic diagram of a signal processing system according to an embodiment of the utility model;

[0012] Figure 2 It is a structural schematic diagram of another signal processing system according to an embodiment of the utility model;

[0013] Figure 3 This is a circuit schematic diagram of a power supply module according to an embodiment of the utility model. DETAILED DESCRIPTION

[0014] In order to make the purpose, technical scheme and advantages of the utility model clearer, the utility model is further described in detail below in conjunction with the accompanying drawings and embodiments, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. It should be understood that the specific embodiments described herein are only used to explain the utility model and are not used to limit the utility model. In addition, the technical features involved in the various embodiments of the utility model described below can be combined with each other as long as they do not conflict with each other.

[0015] Before describing in detail the signal processing system provided in the embodiment of the present application, the abbreviations or custom terms appearing below are explained as follows:

[0016] PCIE (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard); MDI (Media Dependent Interface, uplink port); DDR5 memory (DDR5 SDRAM); FPGA (Field-Programmable Gate Array, field programmable gate array); CPLD (Complex Programmable Logic Device, complex programmable logic device); Aurora (a scalable lightweight link layer protocol for moving data between point-to-point serial links); RocketIO (a hardware bus, typically used to achieve high-speed data transmission between FPGAs and PCs).

[0017] In the related art, since there is a problem that the autonomous controllability of the signal processing system is low and cannot meet the requirements of over-the-horizon and high-resolution radar signal processing, an embodiment of the utility model provides a signal processing system.

[0018] like Figure 1 The figure shows a structural schematic diagram of a signal processing system provided by an embodiment of the utility model, the signal processing system includes: an S5000C-64 processor 10, an FPGA chip 20, a gigabit network controller 30, a CPLD chip 40, multiple optical modules 50 and a network communication connector 60, the first data transmission interface of the S5000C-64 processor 10 is electrically connected to the FPGA chip 20, the second data transmission interface of the S5000C-64 processor 10 is electrically connected to the gigabit network controller 30, the general input and output interface of the S5000C-64 processor 10 is electrically connected to the CPLD chip 40, the multiple optical modules 50 are electrically connected to the FPGA chip 20, and the network communication connector 60 is electrically connected to the gigabit network controller 30.

[0019] Specifically, in this embodiment, the S5000C-64 processor 10 adopts the Tengyun S5000C-64 processor. The Tengyun S5000C-64 processor is a new generation of high-performance processor of Feiteng. It has great advantages in signal / data acquisition and processing based on this processor, and can provide high-performance signal acquisition and processing functions for over-the-horizon and high-resolution radars, and can better meet the signal processing requirements of over-the-horizon and high-resolution radars. The signal processing system implemented by using the Tengyun processor as the S5000C-64 processor 10 and combining the FPGA chip 20, the optical module unit 50, the CPLD chip 40 and the Gigabit network controller 30, each device can use domestic devices to achieve the purpose of nationalization design, and can replace the signal processing module based on foreign DSP, effectively ensuring the security of radar data and the autonomous control of data processing. The first data transmission interface of the Tengyun S5000C-64 processor in this embodiment is connected to the FPGA chip 20 through a high-speed PCIE3.0x8 bus, and the second data transmission interface of the Tengyun S5000C-64 processor is connected to the Gigabit network controller 30 through a high-speed PCIE2.0x4 bus. The Gigabit network controller 30 is connected to the network communication connector 60 to provide a Gigabit network interface to the outside. The general input and output interface GPIO of the Tengyun S5000C-64 processor is connected to the CPLD chip 40. The CPLD chip 40 communicates with the Tengyun S5000C-64 processor through the GPIO port to control the Tengyun S5000C-64 processor. The optical module unit 50 can be used to provide an optical port to the outside. Among them, the FPGA chip 20 can adopt the FPGA of Fudan Micro JFM7VX690T80, the CPLD chip 40 can adopt the CPLD of EF2L45BG256B, the Gigabit network controller 30 can adopt the Gigabit network controller of Netcom WX1860AL2, and the optical module unit 50 can adopt the MPO optical module and the LC optical module.

[0020] like Figure 2 The following is a schematic diagram of the structure of another signal processing system. Figure 2 The signal processing system further comprises a plurality of network transformers, each of which is electrically connected to the Gigabit network controller C (30) and the network communication connector G (60). Further, the signal processing system comprises a first network transformer E and a second network transformer F, and the MDI Gigabit network interfaces of the first network transformer E and the second network transformer F are electrically connected to the network communication connector G; the network communication connector G is a double-layer RJ45 connector.

[0021] In this embodiment, the upstream of the Gigabit network controller C is connected to the Tengyun S5000C-64 processor A (10), and the downstream is connected to two network transformers, and the network transformer is connected to the double-layer RJ45 connector G through a 2-way MDI Gigabit network interface. The Gigabit network controller C is a network interface controller for connecting and managing a Gigabit Ethernet network; the MDI Gigabit network interface is used in Ethernet devices to connect to a network transmission medium (such as an optical fiber or a twisted pair), and the MDI Gigabit network interface is usually connected to a twisted pair network cable using an RJ45 plug for data communication. The network transformer can be a network transformer of model LTS020111A. By using the network transformer, the function of isolating and protecting the network device from electrical interference can be provided, and the voltage conversion function can be provided to adapt the signal to devices of different voltage levels for communication.

[0022] For further information, see Figure 2 The signal processing system includes an MPO optical module H and multiple LC optical modules. The MPO optical module H is electrically connected to the FPGA chip B (20) via an Aurora bus, and the multiple LC optical modules are electrically connected to the FPGA chip via a RocketIO bus. The signal processing system includes a first LC optical module J and a second LC optical module K. The first LC optical module J and the second LC optical module K are electrically connected to the FPGA chip B via the RocketIO bus.

[0023] In this embodiment, the upstream of FPGA chip B is connected to Tengyun S5000C-64 processor A, and the downstream is connected to MPO optical module H through 12-way Aurora bus to provide 12-way Aurora optical ports to the outside, and is connected to LC optical module through 2-way RocketIO bus to provide 2-way RocketIO optical ports to the outside. Among them, MPO optical module H is a high-density fiber optic connector, which is usually used in data centers, supercomputers and other occasions that require high-speed and large-capacity transmission; it usually has multiple fiber optic channels (12 or 24 channels) and can transmit multiple data streams at the same time, improving transmission efficiency and bandwidth capacity. LC optical module is a small fiber optic connector, which is usually used in communication equipment, fiber optic transceivers, network switches and other equipment, and is easy to install and disassemble.

[0024] For further information, see Figure 2 The signal processing system further includes a storage unit D electrically connected to the S5000C-64 processor 10. The storage unit D includes a first DDR5 memory, a second DDR5 memory, a third DDR5 memory, a fourth DDR5 memory, a fifth DDR5 memory, a sixth DDR5 memory, a seventh DDR5 memory, and an eighth DDR5 memory electrically connected to the S5000C-64 processor 10, respectively.

[0025] Further, see Figure 2 The signal processing system also includes an M.2 hard disk connector O, and the third data transmission interface of the S5000C-64 processor 10 is electrically connected to the M.2 hard disk connector O.

[0026] In this embodiment, the third data transmission interface of the Tengyun S5000C-64 processor A is connected to the M.2 hard disk connector O through a high-speed PCIE3.0x4 bus, so that the S5000C-64 processor 10 is connected to the storage disk, that is, the M.2 connector is set to provide a hard disk interface to the outside. The DDR5 memory bus of the Tengyun S5000C-64 processor A is connected to the storage unit D, which contains 8 DDR5 memories and can provide 8 channels of 64GB of memory capacity for the signal processing system.

[0027] In addition, the signal processing system also includes a power connector N, which is connected to a power module L inside the system, and the power module L is used to supply power to various devices and connectors in the system, such as Figure 3 The circuit schematic diagram of the power supply module L shown in the figure, wherein the CPLD chip M (40) can control the power-on timing of each power supply.

[0028] The signal processing system provided by the embodiment of the utility model is implemented by using an S5000C-64 processor, a gigabit network controller, an FPGA chip, a CPLD chip and an optical module. Each device can be a domestic device. For example, the S5000C-64 processor uses the Tengyun S5000C-64 processor, and the FPGA chip uses the Fudan Micro JFM7VX690T80 FPGA, etc., so that the radar signal system can be domestically produced, effectively ensuring the security of data processing. At the same time, signal processing based on a high-performance processor such as the Tengyun S5000C-64 can better meet the needs of over-the-horizon and high-resolution radar signal processing.

[0029] It should be noted that the various embodiments in the present invention are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referenced to each other.

[0030] It should also be noted that, in the present invention, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0031] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined in the present invention may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown in the present invention, but will conform to the widest range consistent with the principles and novel features disclosed in the present invention.

Claims

1. A signal processing system, characterized in that: include: S5000C-64 processor, FPGA chip, Gigabit network controller, CPLD chip, multiple optical modules and network communication connector, the first data transmission interface of the S5000C-64 processor is electrically connected to the FPGA chip, the second data transmission interface of the S5000C-64 processor is electrically connected to the Gigabit network controller, the general input and output interface of the S5000C-64 processor is electrically connected to the CPLD chip, the multiple optical modules are all electrically connected to the FPGA chip, and the network communication connector is electrically connected to the Gigabit network controller.

2. The signal processing system according to claim 1, characterized in that It also includes a plurality of network transformers, each of which is electrically connected to the Gigabit network controller and the network communication connector.

3. The signal processing system according to claim 2, characterized in that It comprises a first network transformer and a second network transformer, wherein the MDI gigabit network interfaces of the first network transformer and the second network transformer are both electrically connected to the network communication connector.

4. The signal processing system according to claim 2, characterized in that The network communication connector is a double-layer RJ45 connector.

5. The signal processing system according to claim 1, characterized in that: It includes an MPO optical module and multiple LC optical modules. The MPO optical module is electrically connected to the FPGA chip via an Aurora bus, and the multiple LC optical modules are electrically connected to the FPGA chip via a RocketIO bus.

6. The signal processing system according to claim 5, characterized in that It includes a first LC optical module and a second LC optical module, and the first LC optical module and the second LC optical module are electrically connected to the FPGA chip through a RocketIO bus respectively.

7. The signal processing system according to claim 1, characterized in that: Also included is a storage unit electrically connected to the S5000C-64 processor.

8. The signal processing system according to claim 7, characterized in that: The storage unit includes a first DDR5 memory, a second DDR5 memory, a third DDR5 memory, a fourth DDR5 memory, a fifth DDR5 memory, a sixth DDR5 memory, a seventh DDR5 memory and an eighth DDR5 memory which are electrically connected to the S5000C-64 processor respectively.

9. The signal processing system according to claim 1, characterized in that: It also includes an M.2 hard disk connector, and the third data transmission interface of the S5000C-64 processor is electrically connected to the M.2 hard disk connector.

10. The signal processing system according to any one of claims 1 to 9, characterized in that: The FPGA chip is a JFM7VX690T80 FPGA chip.

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