FPGA-based SIP control circuit

Abstract

The utility model relates to the field of chip integration, and particularly discloses an SIP control circuit based on an FPGA. Comprising a microcontroller which is electrically connected with an FPGA chip and a motor and is used for obtaining communication information of the FPGA and outputting a corresponding driving signal to the motor; the FPGA chip is connected with the microcontroller and is used for communicating with the microcontroller; the control module is connected with the microcontroller and the FPGA chip and is used for outputting a control instruction to the microcontroller and feeding back a position instruction to the FPGA chip; the motor is mechanically connected with the FPGA chip and the encoder and is used for feeding back an open-phase signal to the FPGA chip; and the encoder is connected with the FPGA chip and is used for feeding back the speed position to the FPGA chip. The microcontroller and the FPGA chip are packaged on the base, so that highly integrated circuit design is realized, and the number of external connection and components is reduced. The microcontroller receives a control instruction and outputs a driving signal to the motor through the TM interface, so that accurate motor control is realized.

Description

Technical Field

[0001] The utility model relates to the field of chip integration, in particular to a SIP control circuit based on FPGA. Background Art

[0002] SIP technology is an advanced electronic packaging technology that integrates multiple electronic components into one package to achieve highly integrated and miniaturized electronic product design. SIP technology has significant advantages in improving product performance, reducing costs and shortening product time to market.

[0003] As electronic devices develop towards higher performance, smaller size and lower power consumption, SIP technology has become one of the key technologies to promote the development of the industry. SIP technology improves the integration and performance density of circuits by integrating multiple functional components in a miniaturized package, thereby achieving more efficient electronic system design.

[0004] In high-performance control applications, such as industrial automation, automotive electronics, and aerospace, the performance requirements for control circuits are getting higher and higher. These fields require control circuits to operate stably under extreme conditions to ensure the accuracy, response speed, and reliability of the system. With the development of technology and the increase in demand, the design and optimization of control circuits have become particularly critical to meet the stringent requirements and performance indicators of complex systems. Utility Model Content

[0005] In order to overcome the above technical problems existing in the prior art, the embodiment of the utility model provides a SIP control circuit based on FPGA, which realizes a highly integrated circuit design by encapsulating a microcontroller and an FPGA chip on a base, and reduces the number of external connections and components. The microcontroller receives control instructions and outputs a drive signal to the motor through the TM interface, thereby realizing precise motor control.

[0006] In order to achieve the above-mentioned purpose, an embodiment of the utility model provides a SIP control circuit based on FPGA, including: a microcontroller, electrically connected to an FPGA chip and a motor, for obtaining communication information of the FPGA and outputting a corresponding drive signal to the motor; the FPGA chip, connected to the microcontroller, for communicating with the microcontroller; a control module, connected to the microcontroller and the FPGA chip, for outputting control instructions to the microcontroller and feeding back position instructions to the FPGA chip; the motor, mechanically connected to the FPGA chip and an encoder, for feeding back a phase loss signal to the FPGA chip; the encoder, connected to the FPGA chip, for feeding back a speed position to the FPGA chip.

[0007] Preferably, the microcontroller is communicatively connected to the control module via a CAN interface and a USART interface; the ADC interface of the microcontroller is connected to the control module for receiving the control instructions; the TM interface of the microcontroller is connected to the motor for outputting the drive signal.

[0008] Preferably, the model of the microcontroller is APM32F407.

[0009] Preferably, the FPGA chip is connected to the FSMC interface of the microcontroller via an IO interface.

[0010] Preferably, the model of the FPGA chip is: GW1N-4K.

[0011] Preferably, the microcontroller and the FPGA chip are connected to external devices via corresponding JTAG interfaces respectively.

[0012] Preferably, the motor is an IPM motor.

[0013] Preferably, the microcontroller and the FPGA chip are packaged in a PBGA441 packaging manner.

[0014] Through the technical solution provided by the utility model, the utility model has at least the following technical effects:

[0015] By packaging the microcontroller and FPGA chip, a highly integrated circuit design is achieved, reducing the number of external connections and components. The microcontroller communicates with the control module through the CAN and USART interfaces, providing flexible communication options to adapt to different communication protocols and application requirements. The microcontroller receives control instructions and outputs drive signals to the motor through the TM interface, achieving precise motor control. The tight integration of the FPGA chip and the microcontroller provides powerful data processing capabilities, which can process the speed and position feedback signals from the encoder in real time.

[0016] Other features and advantages of the embodiments of the present invention will be described in detail in the subsequent specific implementation section. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings are used to provide a further understanding of the embodiments of the present utility model and constitute a part of the specification. Together with the following specific implementations, they are used to explain the embodiments of the present utility model, but do not constitute a limitation on the embodiments of the present utility model. In the accompanying drawings:

[0018] Figure 1 It is a structural schematic diagram of a SIP control circuit based on FPGA provided by an embodiment of the utility model. DETAILED DESCRIPTION

[0019] The specific implementation of the embodiment of the utility model is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described here is only used to illustrate and explain the embodiment of the utility model, and is not used to limit the embodiment of the utility model.

[0020] The terms "system" and "network" in the embodiments of the present invention can be used interchangeably. "Multiple" refers to two or more than two. In view of this, in the embodiments of the present invention, "multiple" can also be understood as "at least two". "And / or" describes the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / ", unless otherwise specified, generally indicates that the previous and subsequent associated objects are in an "or" relationship. In addition, it should be understood that in the description of the embodiments of the present invention, words such as "first" and "second" are only used to distinguish the purpose of description, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order.

[0021] See also Figure 1 The utility model embodiment is a FPGA-based SIP control circuit, including: a microcontroller, electrically connected to an FPGA chip and a motor, for obtaining communication information of the FPGA and outputting a corresponding drive signal to the motor; the FPGA chip, connected to the microcontroller, for communicating with the microcontroller; a control module, connected to the microcontroller and the FPGA chip, for outputting control instructions to the microcontroller and feeding back position instructions to the FPGA chip; the motor, mechanically connected to the FPGA chip and an encoder, for feeding back a phase loss signal to the FPGA chip; the encoder, connected to the FPGA chip, for feeding back a speed position to the FPGA chip.

[0022] Preferably, the microcontroller is communicatively connected to the control module via a CAN interface and a USART interface; the ADC interface of the microcontroller is connected to the control module for receiving the control instructions; the TM interface of the microcontroller is connected to the motor for outputting the drive signal.

[0023] In one possible implementation, the microcontroller is electrically connected to the FPGA chip to achieve high-speed data transmission. The TM interface of the microcontroller is connected to the motor to output accurate PWM signals to control the motor speed and torque. The microcontroller communicates with the control module via the CAN and USART interfaces to receive control instructions. The ADC interface of the microcontroller is connected to the control module to receive analog control signals and convert them into digital signals. The control module sends the position command information to the IO interface of the FPGA chip. The motor is mechanically connected to the FPGA chip and the encoder, which improves the performance and reliability of the motor drive. The motor and the encoder provide real-time feedback to the FPGA chip, including phase loss signals and speed and position information, making the control more precise and the response faster.

[0024] In the embodiment of the utility model, the model of the microcontroller is APM32F407, and the microcontroller adopts a domestic chip.

[0025] Preferably, the FPGA chip is connected to the FSMC interface of the microcontroller via an IO interface.

[0026] In a possible implementation, the APM32F407 adopts a 32-bit architecture, has a powerful processing capability, is suitable for processing complex algorithms and multi-tasking operations, and integrates a variety of peripherals and interfaces, such as multiple UARTs, SPIs, I2C interfaces, as well as timers and ADC / DAC, etc., to meet the needs of various applications. Further, the microcontroller is connected to the FPGA chip through the FSMC interface to achieve high-speed data transmission.

[0027] In the embodiment of the utility model, the model of the FPGA chip is: GW1N-4K.

[0028] Preferably, the microcontroller and the FPGA chip are connected to external devices via corresponding JTAG interfaces respectively.

[0029] In one possible implementation, FPGA chips allow users to reprogram their internal logic according to specific needs, so they are extremely flexible and customizable. GW1N-4K is usually designed as a low-power chip, suitable for applications that require long-term operation or battery power. While meeting performance requirements, it can effectively manage and optimize power consumption. Furthermore, the JTAG interface is used for debugging and program downloading of microcontrollers and FPGA chips. Developers can connect a debugger or programmer through the JTAG interface to monitor and debug the operating status of the device in real time, view the internal register status and data during program execution.

[0030] In an embodiment of the present invention, the motor is an IPM motor.

[0031] Preferably, the microcontroller and the FPGA chip are packaged in a PBGA441 packaging manner.

[0032] In one possible implementation, the IPM motor adopts an IPM motor design with internal permanent magnets to provide high power density and optimized energy conversion efficiency. Furthermore, the PBGA441 package provides reliable electrical connections through solder ball connections, reducing crosstalk and signal loss in the circuit, and helping to improve the overall reliability and performance of the system.

[0033] The optional implementation modes of the embodiments of the utility model are described in detail above in conjunction with the accompanying drawings. However, the embodiments of the utility model are not limited to the specific details in the above implementation modes. Within the technical concept of the embodiments of the utility model, the technical scheme of the embodiments of the utility model can be subjected to various simple modifications, and these simple modifications all belong to the protection scope of the embodiments of the utility model.

[0034] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, the embodiments of the utility model will not further describe various possible combinations.

[0035] Those skilled in the art can understand that all or part of the steps in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a program, and the program is stored in a storage medium, including a number of instructions to enable a single-chip microcomputer, a chip or a processor to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.

[0036] In addition, various implementations of the embodiments of the present utility model can also be arbitrarily combined, as long as they do not violate the concept of the embodiments of the present utility model, they should also be regarded as the contents disclosed in the embodiments of the present utility model.

Claims

1. A SIP control circuit based on FPGA, characterized in that: include: A microcontroller, electrically connected to the FPGA chip and the motor, for acquiring communication information of the FPGA and outputting a corresponding drive signal to the motor; The FPGA chip is connected to the microcontroller and is used to communicate with the microcontroller; A control module, connected to the microcontroller and the FPGA chip, for outputting control instructions to the microcontroller and feeding back position instructions to the FPGA chip; The motor is mechanically connected to the FPGA chip and the encoder, and is used to feed back a phase loss signal to the FPGA chip; The encoder is connected to the FPGA chip and is used to feed back speed and position to the FPGA chip.

2. The FPGA-based SIP control circuit according to claim 1, characterized in that: The microcontroller is connected to the control module through a CAN interface and a USART interface; The ADC interface of the microcontroller is connected to the control module for receiving the control instruction; The TM interface of the microcontroller is connected to the motor for outputting the driving signal.

3. The FPGA-based SIP control circuit according to claim 2, characterized in that: The model of the microcontroller is APM32F407.

4. The FPGA-based SIP control circuit according to claim 1, characterized in that: The FPGA chip is connected to the FSMC interface of the microcontroller via an IO interface.

5. The FPGA-based SIP control circuit according to claim 1, characterized in that: The model of the FPGA chip is: GW1N-4K.

6. The FPGA-based SIP control circuit according to claim 1, characterized in that: The microcontroller and the FPGA chip are connected to external devices via corresponding JTAG interfaces respectively.

7. The FPGA-based SIP control circuit according to claim 1, characterized in that: The motor is an IPM motor.

8. A SIP control circuit based on FPGA according to any one of claims 1 to 5, characterized in that: The microcontroller and the FPGA chip are packaged in a PBGA441 packaging manner.

Images