Three-dimensional capacitor structure
By stacking multiple capacitor structures on the substrate in parallel and increasing the dielectric layer area by forming a stack structure, the problem of deformation of existing capacitors under high voltage is solved, and a three-dimensional capacitance structure with high capacity and high stability is realized.
Patent Information
- Application Number
- CN202420650303.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-01
- Publication Date
- 2025-05-16
- Estimated Expiration
- 2034-04-01
AI Technical Summary
When existing capacitors use high dielectric constant materials under high voltage, deformation problems are prone to occur, which affects the stability of the capacitor and is difficult to effectively increase the capacity of the capacitor.
Using a three-dimensional capacitance structure, by stacking a plurality of capacitor structures on the substrate and electrically connecting the first and second electrodes of two adjacent capacitor structures, a parallel structure is formed to increase the capacitance, and by forming the stack structure, the area of the dielectric layer is increased to increase the capacitance density.
On the premise of ensuring the stability of the capacitor, the capacity of the capacitor is effectively improved and the capacitance density is not required, and the high dielectric constant material is not required to ensure the stability of the capacitor.
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Figure CN222883394U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of electronic and electrical technology, and in particular to a three-dimensional capacitor structure. Background Art
[0002] Capacitors play a vital role in the family of electronic components and are widely used in various circuits and devices. Known for their ability to store and release electric charges, capacitors provide indispensable functions for electronic systems. In order to increase the capacity of capacitors, researchers have made many attempts. A common strategy is to use materials with high dielectric constants as the dielectric layer of capacitors. However, although the use of high dielectric constant materials can increase the capacity of capacitors, high dielectric constant materials will produce significant deformation under high voltage, which will affect the stability of the capacitor. Utility Model Content
[0003] In view of this, the present application provides a three-dimensional capacitor structure to effectively increase the capacity of the capacitor while ensuring the stability of the capacitor.
[0004] Specifically, the present application is implemented through the following technical solutions:
[0005] In a first aspect, the present application provides a three-dimensional capacitor structure, the three-dimensional capacitor structure comprising a substrate and a plurality of capacitor structures; wherein:
[0006] The plurality of capacitor structures are sequentially formed on the substrate in a direction away from the substrate;
[0007] Each of the capacitor structures comprises a stacked structure, an isolation layer, a first electrode and a second electrode; wherein,
[0008] At least one of the first side surface and the second side surface of the stacked structure is in a step-shaped structure; the stacked structure comprises n+1 electrode layers and n dielectric layers alternately stacked, where n is a positive integer; the first side surface and the second side surface are two side surfaces on a designated side of the stacked structure; the designated side is a long side or a short side;
[0009] The isolation layer is formed on the stacked structure and forms a plane with the stacked structure;
[0010] A first electrode wire group and a second electrode wire group are formed inside the isolation layer, the first electrode wire group is connected to the odd-numbered electrode layers of the stacked structure through the step-shaped structure, and the second electrode wire group is connected to the even-numbered electrode layers of the stacked structure through the step-shaped structure;
[0011] The first electrode is connected to the odd-numbered electrode layers through the first electrode wire group;
[0012] The second electrode is connected to the even-numbered electrode layer through the second electrode wire group;
[0013] The first electrodes of two adjacent capacitor structures are electrically connected, and the second electrodes of two adjacent capacitor structures are electrically connected.
[0014] The three-dimensional capacitor structure provided by the present application is formed by stacking a plurality of capacitor structures on a substrate, and then electrically connecting the first electrodes of two adjacent capacitor structures, and electrically connecting the second electrodes of two adjacent capacitor structures, so that the capacitance of the three-dimensional capacitor structure can be increased by connecting the plurality of capacitor structures in parallel. In addition, by forming a stacked structure, the area of the dielectric layer can be increased, a very high capacitance density can be achieved, and the capacitance of the three-dimensional capacitor structure can be increased, and it is not necessary to use a material with a high dielectric constant as the dielectric layer, so as to ensure the stability of the three-dimensional capacitor structure.
[0015] Further, the specific number of capacitor structures that can be stacked can be selected according to the actual needs of the capacitance parameters to obtain the actual capacity of the assembled capacitor as needed. In this case, it is not necessary to set the capacitance value of a single capacitor structure too high. Further, the height of the stacked structure of a single capacitor structure can be appropriately reduced, the process margin of a single capacitor structure can be increased, and the reliability of a single capacitor structure can be improved.
[0016] Furthermore, the capacitor structures stacked sequentially may have different sizes, especially in the direction of the connection between the first electrode and the second electrode. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 A schematic diagram of a three-dimensional capacitor structure shown in an exemplary embodiment of the present application;
[0018] Figure 2 A schematic diagram of a capacitor structure shown as an exemplary embodiment of the present application;
[0019] Figure 3 A schematic diagram of a capacitor structure shown in another exemplary embodiment of the present application;
[0020] Figure 4 This is a schematic diagram of a stacking structure shown in yet another exemplary embodiment of the present application;
[0021] Figure 5 A top view of a capacitor structure shown as an exemplary embodiment of the present application;
[0022] Figure 6 A top view of a capacitor structure is shown in yet another exemplary embodiment of the present application.
[0023] Description of reference numerals:
[0024] 10: base;
[0025] 20: Capacitor structure;
[0026] 2: Stacked structure;
[0027] 21: electrode layer;
[0028] 22: dielectric layer;
[0029] 3: Isolation layer;
[0030] 31: first electrode wire group;
[0031] 311: first wire group;
[0032] 312: second wire group;
[0033] 32: second electrode wire group;
[0034] 321: third wire group;
[0035] 322: fourth wire group;
[0036] 4: first electrode;
[0037] 5: Second electrode. DETAILED DESCRIPTION
[0038] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.
[0039] The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used in this article refers to and includes any or all possible combinations of one or more associated listed items.
[0040] It should be understood that although the terms first, second, third, etc. may be used in the present application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".
[0041] Specific embodiments are given below to introduce the technical solution of the present application in detail.
[0042] Figure 1 This is a schematic diagram of a three-dimensional capacitor structure shown in an exemplary embodiment of the present application. Figure 1 This embodiment provides a three-dimensional capacitor structure, including a substrate 10 and a plurality of capacitor structures 20; wherein,
[0043] The plurality of capacitor structures 20 are sequentially formed on the substrate 10 in a direction away from the substrate 10;
[0044] Each of the capacitor structures 20 comprises a stacked structure 2, an isolation layer 3, a first electrode 4 and a second electrode 5; wherein,
[0045] At least one of the first side surface and the second side surface of the stacking structure 2 is in a step-like structure;
[0046] The stacked structure 2 includes n+1 electrode layers 21 and n dielectric layers 22 that are alternately stacked, where n is a positive integer; the first side surface and the second side surface are two side surfaces on a specified edge of the stacked structure 2;
[0047] The designated side is a long side or a short side;
[0048] The isolation layer 3 is formed on the stacked structure 2 and forms a plane with the stacked structure 2;
[0049] A first electrode wire group 31 and a second electrode wire group 32 are formed inside the isolation layer 3. The first electrode wire group 31 is connected to the odd-numbered electrode layers of the stacked structure 2 through the step-shaped structure, and the second electrode wire group 32 is connected to the even-numbered electrode layers of the stacked structure 2 through the step-shaped structure.
[0050] The first electrode 4 is connected to the odd-numbered electrode layers through the first electrode wire group 31;
[0051] The second electrode 5 is connected to the even-numbered electrode layer through the second electrode wire group 32;
[0052] The first electrodes 4 of two adjacent capacitor structures 20 are electrically connected, and the second electrodes 5 of two adjacent capacitor structures 20 are electrically connected.
[0053] It should be noted that the substrate 10 can be a semiconductor material substrate, such as a silicon substrate, a Ge substrate, a SiGe substrate, an SOI substrate or a GOI substrate, etc.; it can also be an insulating substrate, such as silicon nitride, silicon dioxide, silicon oxynitride, a flexible polymer substrate, a glass substrate, a sapphire substrate, a silicon carbide substrate, etc.; it can also be a III-V group substrate, such as a gallium nitride substrate, a gallium arsenide substrate, etc., which is not limited in this embodiment. In specific implementation, a suitable material can be selected as the substrate according to the actual needs of the three-dimensional capacitor structure, which is not limited here.
[0054] Specifically, the three-dimensional capacitor structure includes multiple capacitor structures, and the specific number of the multiple capacitor structures is set according to actual needs, and is not limited in this embodiment. For example, the three-dimensional capacitor structure may include 2 capacitor structures, 3 capacitor structures, etc.
[0055] Furthermore, a plurality of capacitor structures 20 are sequentially formed on the substrate 10 in a direction away from the substrate 10. Figure 1 As shown, for example, in one possible implementation, the three-dimensional capacitor structure may include two capacitor structures 20, and the two capacitor structures 20 are sequentially formed on the substrate 10 in a direction away from the substrate 10. For another example, in another possible implementation, the three-dimensional capacitor structure may include three capacitor structures 20, and the three capacitor structures are sequentially formed on the substrate 10 in a direction away from the substrate 10.
[0056] It should be noted that the specific structural forms of each capacitor structure in the multiple capacitor structures may be the same or different, and this application does not limit them. The following takes a capacitor structure as an example to introduce the specific structure of the capacitor structure.
[0057] Specifically, Figure 2 This is a schematic diagram of a capacitor structure shown in an exemplary embodiment of the present application. Figure 3 This is a schematic diagram of a capacitor structure shown in another exemplary embodiment of the present application. Please also refer to Figure 2 and reference Figure 3 The capacitor structure 20 includes a stacked structure 2, an isolation layer 3, a first electrode 4, and a second electrode 5. At least one of the first side surface and the second side surface of the stacked structure 2 is a step-shaped structure. Figure 2 In the example shown, the first side surface and the second side surface of the stacking structure 2 are both step-shaped structures; for another example, Figure 3 In the example shown, the first side surface of the stacked structure 2 is a step-shaped structure.
[0058] It should be noted that the first side surface and the second side surface may be two side surfaces on the long side of the stacking structure, or may be two side surfaces on the short side of the stacking structure, which is not limited in this embodiment.
[0059] Specifically, the width of the step in the stepped structure is set according to actual needs. In this embodiment, the width of the step is not limited. For example, in a possible implementation, the width of the step is between 50 nanometers and 2 micrometers.
[0060] For further information, please also refer to Figure 2 and Figure 3 The stacked structure 2 includes n+1 electrode layers 21 and n dielectric layers 22 alternately stacked, where n is a positive integer. The specific value of n is set according to actual needs. In this embodiment, the specific value of n is not limited. In specific implementation, by controlling the number of stacked layers, a very high capacitance density can be achieved.
[0061] Specifically, the material of the electrode layer 21 is composed of one or more combinations of doped polysilicon, TiN, TaN, Ti, Ta, Al, Cu, Au, Ag, and W, and the material of the dielectric layer 22 is composed of one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, magnesium oxide, aluminum oxide, hafnium oxide, and tantalum oxide.
[0062] It should be noted that the thickness of the dielectric layer 22 is determined by the withstand voltage of the capacitor. Generally, a high withstand voltage capacitor requires a thicker dielectric layer. The thickness of the electrode layer 21 determines the equivalent series resistance and equivalent series inductance of the capacitor. Different materials and thicknesses can be selected according to different needs. In this embodiment, the material and thickness of the electrode layer 21 and the material and thickness of the dielectric layer 22 are not limited. For example, in one embodiment, the thickness of the electrode layer 21 is 5nm to 1mm, and the thickness of the dielectric layer 22 is 1nm to 10μm.
[0063] Please continue to refer to Figure 2 and Figure 3 , the isolation layer 3 is formed on the stacked structure 2 and forms a plane with the stacked structure 2. Among them, the isolation layer 3 is usually made of a material with a low dielectric constant to prevent electromagnetic interference between different layers in the three-dimensional capacitor structure. Specifically, the material of the isolation layer 3 can be selected according to actual needs and is not limited in this embodiment. For example, in one embodiment, the material of the isolation layer 3 can be a SiO2 material with a low dielectric constant.
[0064] In a specific implementation, after the isolation layer 3 is formed, the isolation layer 3 covers the stepped structure. In this embodiment, a first electrode wire group and a second electrode wire group can be formed in the isolation layer 3 by a through-hole process, so that the first electrode wire group is connected to the odd-numbered electrode layers in the stacked structure through the stepped structure; and the second electrode wire group is connected to the even-numbered electrode layers in the stacked structure through the stepped structure.
[0065] It should be noted that, refer to Figure 3 When the first side surface of the stack structure of the capacitor structure is a step-shaped structure, the odd-numbered electrode layers and the even-numbered electrode layers of the stack structure are both located on the first side surface of the stack structure.
[0066] Figure 4 This is a schematic diagram of a stacking structure shown in another exemplary embodiment of the present application. Figure 1 and Figure 4 , the first side and the second side of the stacked structure of the capacitor structure are both stepped structures; the odd-numbered electrode layers and the even-numbered electrode layers of the stacked structure are located on different sides or the same side of the stacked structure. Figure 1 In the example shown, the first side and the second side of the stacked structure of the capacitor structure are both step-shaped structures; the odd-numbered electrode layers and the even-numbered electrode layers of the stacked structure are located on different sides of the stacked structure. Figure 4 In the example shown, the first side surface and the second side surface of the stacked structure of the capacitor structure are both step-shaped structures; the odd-numbered electrode layers and the even-numbered electrode layers of the stacked structure are located on the same side of the stacked structure.
[0067] Specifically, the wire group connected to one electrode layer may be a wire group consisting of a linear connection line, or may be a wire group consisting of a plurality of point-shaped connection holes, which is not limited in this embodiment.
[0068] Specifically, the first electrode and the second electrode may be formed by processes such as evaporation, sputtering, and chemical vapor deposition, and the materials of the first electrode and the second electrode may be Cu, Al, Au, Ag, and the like.
[0069] Please continue to refer to Figure 1 The first electrodes 4 of two adjacent capacitor structures 20 are electrically connected, and the second electrodes 5 of two adjacent capacitor structures 20 are electrically connected, so that multiple capacitor structures are connected in parallel to increase the capacitance of the three-dimensional capacitor structure.
[0070] Referring to the above introduction, it can be understood that, in a possible implementation, among the multiple capacitor structures, the first side of the stacked structure of at least one capacitor structure is a step-shaped structure; the odd-numbered electrode layers and the even-numbered electrode layers of the stacked structure are both located on the first side of the stacked structure. In other words, among the multiple capacitor structures, the specific structural form of at least one capacitor structure is as follows: Figure 3 shown.
[0071] Similarly, in another possible implementation, the first side and the second side of the stacked structure of at least one capacitor structure are both stepped structures; the odd-numbered electrode layers and the even-numbered electrode layers of the stacked structure are located on different sides or the same side of the stacked structure. In other words, among the multiple capacitor structures, the specific structure of at least one capacitor structure is as follows: Figure 2 or Figure 4 shown.
[0072] It should be noted that each capacitor structure in the plurality of capacitor structures may be the same. For example, the specific structures of each capacitor structure are as follows: Figure 2 , Figure 3 or Figure 4 As shown. Of course, each capacitor structure in the plurality of capacitor structures may also be different. For example, one of the capacitor structures in the plurality of capacitor structures is as follows Figure 2 As shown, the remaining capacitor structures are as shown in 3 or Figure 4 That is, Figure 2 , Figure 3 , Figure 4 A specific structural form of a capacitor structure is given. When the three-dimensional capacitor structure includes multiple capacitor structures, the specific structural form of each capacitor structure can be Figure 2 , Figure 3 or Figure 4 For example, in one embodiment, the three-dimensional capacitor structure includes two capacitor structures, wherein the specific structural form of one capacitor structure is as follows: Figure 2 As shown, the specific structure of another capacitor structure is as follows Figure 3 For another example, in another embodiment, the three-dimensional capacitor structure includes two capacitor structures, and the specific structural forms of the two capacitor structures are as follows: Figure 2 shown.
[0073] It should be noted that the odd-numbered electrode layers and the even-numbered electrode layers are arranged on the same side, so that the currents of two adjacent electrode layers flow in opposite directions, thereby reducing or even canceling the equivalent series inductance.
[0074] The three-dimensional capacitor structure provided by the present application is formed by stacking a plurality of capacitor structures on a substrate, and then electrically connecting the first electrodes of two adjacent capacitor structures, and electrically connecting the second electrodes of two adjacent capacitor structures, so that the capacitance of the three-dimensional capacitor structure can be increased by connecting the plurality of capacitor structures in parallel. In addition, by forming a stacked structure, the area of the dielectric layer can be increased, a very high capacitance density can be achieved, and the capacitance of the three-dimensional capacitor structure can be increased, and it is not necessary to use a material with a high dielectric constant as the dielectric layer, so as to ensure the stability of the three-dimensional capacitor structure.
[0075] Optional, Figure 5This is a top view of a capacitor structure shown in an exemplary embodiment of the present application. Figure 5 In a possible implementation of the present application, the aspect ratio of the stacking structure of each capacitor is greater than 1, and the first side and the second side of the stacking structure of each capacitor are two sides of the stacking structure on the long side.
[0076] Please continue to refer to Figure 5 The first electrode wire group 31 connected to one electrode layer and the second electrode wire group 32 connected to one electrode layer can be a wire group consisting of a linear connecting wire. Figure 5 By making the first side surface and the second side surface of the stacking structure of each capacitor the two sides of the stacking structure on the long side, the odd-numbered electrode layers and the even-numbered electrode layers can be located in the long side direction of the stacking structure, so that the current flows along the short side, the path through which the current flows can be shorter, and the series resistance of the capacitor can be effectively reduced.
[0077] Figure 6 FIG. 1 is a top view of a capacitor structure shown in another exemplary embodiment of the present application. Figure 6 In a possible implementation, the first side and the second side of the stack structure 2 of at least one capacitor structure are both stepped structures; wherein,
[0078] The first wire group 311 in the first electrode wire group 31 is connected to the odd-numbered electrode layers on the first side of the stacked structure 2, and the second wire group 312 in the first electrode wire group 31 is connected to the odd-numbered electrode layers on the second side of the stacked structure 2; the third wire group 321 in the second electrode wire group 32 is connected to the even-numbered electrode layers on the first side of the stacked structure 2, and the fourth wire group 322 in the second electrode wire group 32 is connected to the even-numbered electrode layers on the second side of the stacked structure 2; the wire groups connected to the same electrode layer include a plurality of dot-shaped connection holes, and from the first direction indicated by the designated edge, the connection holes of the first wire group 311 and the connection holes of the third wire group 321 are alternately arranged, and the connection holes of the fourth wire group 322 and the connection holes of the second wire group 312 are alternately arranged; from the second direction perpendicular to the first direction, the connection holes of the first wire group 311 and the connection holes of the fourth wire group 322 are arranged opposite to each other, and the connection holes of the third wire group 321 and the connection holes of the second wire group 312 are arranged opposite to each other;
[0079] The first electrode 4 is connected to the odd-numbered electrode layers on the first side and the second side of the stacked structure 2 through the first electrode wire group 31;
[0080] The second electrode 5 is connected to the even-numbered electrode layers on the first side surface and the second side surface of the stacked structure through the second electrode wire group 32 .
[0081] Specifically, the conductive material filled in the first electrode wire group 31 and the second electrode wire group 32 includes tungsten.
[0082] It can be understood that the first electrode wire group 31 allows electrical signals to be transmitted between odd-numbered electrode layers through the stacking structure 2. The second electrode wire group 32 allows electrical signals to be transmitted between even-numbered electrode layers through the stacking structure 2. This layered wire group design can effectively manage the electrical connection between different electrode layers in the three-dimensional capacitor structure, making it more orderly and controllable.
[0083] Please continue to refer to Figure 6 The wire group connected to the same electrode layer includes a plurality of point-shaped connection holes. It should be noted that the distance between two adjacent connection holes is between 50 nanometers and 600 nanometers. For example, in a possible implementation, the distance between two adjacent connection holes can be 100 nanometers, 300 nanometers, etc.
[0084] For further information, please refer to Figure 6 , viewed from a first direction indicated by the designated edge, the connection holes of the first wire group 311 and the connection holes of the third wire group 321 are alternately arranged, and the connection holes of the fourth wire group 322 and the connection holes of the second wire group 312 are alternately arranged; viewed from a second direction perpendicular to the first direction, the connection holes of the first wire group 311 and the connection holes of the fourth wire group 322 are oppositely arranged, and the connection holes of the third wire group 321 and the connection holes of the second wire group 312 are oppositely arranged.
[0085] Specifically, refer to Figure 6 The first electrode wire group 31 refers to the wire group connected to the odd-numbered electrode layers, which includes the first wire group 311 connected to the odd-numbered electrode layers on the first side, and the second wire group 312 connected to the odd-numbered electrode layers on the second side; similarly, the second electrode wire group 32 refers to the wire group connected to the even-numbered electrode layers, which includes the third wire group 321 connected to the even-numbered electrode layers on the first side, and the fourth wire group 322 connected to the even-numbered electrode layers on the second side.
[0086] For further information, please refer to Figure 6Taking the first electrode layer as an example, it can be seen that the wire group connected to the same electrode layer includes a plurality of point-shaped connection holes. Furthermore, viewed from the second direction, on any cross section parallel to the second direction, different electrode wire groups are distributed on the two side surfaces. For example, on the first cross section (viewed from top to bottom), the first side surface is distributed with the first electrode wire group, and the second side surface is distributed with the second electrode wire group. On the second cross section, the first side surface is distributed with the second electrode wire group, and the second side surface is distributed with the first electrode wire group. In other words, viewed from the first direction, in any one of the first side surface and the second side surface, the first electrode wire group and the second electrode wire group are alternately arranged, and viewed from the second direction, the first electrode wire group and the second electrode wire group are relatively arranged.
[0087] For further information, please refer to Figure 6 In one possible implementation, the direction of the current in the capacitor structure is as follows: Figure 6 As shown by the arrows in , at this time, the currents in the two adjacent cross sections flow in opposite directions, so that the equivalent series inductance ESL (Equivalent Series Inductance, referred to as ESL) can be reduced or even offset.
[0088] It should be noted that the specific structural form of at least one capacitor structure in the three-dimensional capacitor structure can be as follows: Figure 6 As shown, in this embodiment, it is not limited.
[0089] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.
Claims
1. A three-dimensional capacitor structure, characterized in that: The three-dimensional capacitor structure includes a substrate and a plurality of capacitor structures; wherein, The plurality of capacitor structures are sequentially formed on the substrate in a direction away from the substrate; Each of the capacitor structures comprises a stacked structure, an isolation layer, a first electrode and a second electrode; wherein, At least one of the first side surface and the second side surface of the stacked structure is in a step-shaped structure; the stacked structure comprises n+1 electrode layers and n dielectric layers alternately stacked, where n is a positive integer; the first side surface and the second side surface are two side surfaces on a designated side of the stacked structure; the designated side is a long side or a short side; The isolation layer is formed on the stacked structure and forms a plane with the stacked structure; A first electrode wire group and a second electrode wire group are formed inside the isolation layer, the first electrode wire group is connected to the odd-numbered electrode layers of the stacked structure through the step-shaped structure, and the second electrode wire group is connected to the even-numbered electrode layers of the stacked structure through the step-shaped structure; The first electrode is connected to the odd-numbered electrode layers through the first electrode wire group; The second electrode is connected to the even-numbered electrode layer through the second electrode wire group; The first electrodes of two adjacent capacitor structures are electrically connected, and the second electrodes of two adjacent capacitor structures are electrically connected; The aspect ratio of the stack structure of each capacitor is greater than 1, and the first side surface and the second side surface of the stack structure of each capacitor are two side surfaces on the long side of the stack structure; The first side and the second side of the stacked structure of at least one capacitor structure are both stepped structures; wherein, The first wire group in the first electrode wire group is connected to the odd-numbered electrode layers on the first side of the stacked structure, and the second wire group in the first electrode wire group is connected to the odd-numbered electrode layers on the second side of the stacked structure; the third wire group in the second electrode wire group is connected to the even-numbered electrode layers on the first side of the stacked structure, and the fourth wire group in the second electrode wire group is connected to the even-numbered electrode layers on the second side of the stacked structure; the wire groups connected to the same electrode layer include a plurality of dot-shaped connection holes, and from the first direction indicated by the designated edge, the connection holes of the first wire group and the connection holes of the third wire group are alternately arranged, and the connection holes of the fourth wire group and the connection holes of the second wire group are alternately arranged; from the second direction perpendicular to the first direction, the connection holes of the first wire group and the connection holes of the fourth wire group are arranged oppositely, and the connection holes of the third wire group and the connection holes of the second wire group are arranged oppositely; The first electrode is connected to the odd-numbered electrode layers on the first side and the second side of the stacked structure through the first electrode wire group; The second electrode is connected to the even-numbered electrode layers on the first side surface and the second side surface of the stacked structure through the second electrode wire group.
2. The three-dimensional capacitor structure according to claim 1, characterized in that: The wire group connected to one electrode layer is a wire group consisting of a linear connecting wire; or, The conductive line group connected to one electrode layer is a conductive line group composed of a plurality of point-shaped connection holes.
3. The three-dimensional capacitor structure according to claim 1, characterized in that: The thickness of the electrode layer is 5 nm to 1 mm.
4. The three-dimensional capacitor structure according to claim 1, characterized in that: The thickness of the dielectric layer is 1 nm to 10 μm.