Multi-base-island DIP lead frame and photoelectric packaging module

Abstract

According to the multi-base-island DIP lead frame and the photoelectric packaging module, a plurality of pins are arranged on the two sides of a frame unit, a plurality of base islands arranged at intervals are arranged in the middle of the frame unit, the base islands are correspondingly connected with different pins on one side, and the pins on the other side and the base islands are arranged at intervals; a first base island, a second base island, a third base island and a fourth base island are sequentially arranged in the middle of the frame unit at intervals, a first pin, a second pin, a third pin and a fourth pin are sequentially arranged on one side of the frame unit at intervals, and a fifth pin, a sixth pin, a seventh pin and an eighth pin are sequentially arranged on the other side of the frame unit at intervals. The first base island and the fourth base island respectively extend towards the middle part of the frame unit to form a first expansion base island and a second expansion base island, the first base island is connected with an eighth pin, the second base island is connected with a seventh pin, the third base island is connected with a sixth pin, and the fourth base island is connected with a fifth pin. According to the scheme, multiple base islands are reasonably arranged in a DIP packaging form, and the requirement of multi-chip packaging is met.

Description

Technical Field

[0001] The utility model relates to the technical field of multi-chip integrated packaging, in particular to a multi-island DIP lead frame and a photoelectric packaging module. Background Art

[0002] Multi-chip module packaging is an important trend in electronic manufacturing inventions. It integrates more different chips into the same package to realize the functions of the module. Compared with discrete devices, modular packaging can reduce related parasitic impedance and greatly reduce the line parasitic inductance between devices, which is conducive to high-frequency operation. At present, in response to the market demand for multi-chip packaging such as integrated driver chips, LED chips, and MOS chips, how to build a base island in a narrow DIP package and facilitate subsequent bonding wires has become a technical problem that needs to be solved. Utility Model Content

[0003] In order to solve the above-mentioned deficiencies in the related prior art, the utility model provides a multi-island DIP lead frame and an optoelectronic packaging module, which realize the reasonable layout of multiple islands in the limited space under the DIP packaging form and meet the needs of multi-chip packaging.

[0004] In order to achieve the purpose of this utility model, the following scheme is proposed:

[0005] A multi-island DIP lead frame comprises a plurality of frame units arrayed on a frame body, wherein the frame units have a plurality of pins on both sides respectively, and the middle of the frame units has a plurality of intervally arranged base islands, each base island is respectively connected to a different pin on one side, and each pin on the other side is intervally arranged with the base island.

[0006] Furthermore, the middle part of the frame unit has a first base island, a second base island, a third base island, and a fourth base island arranged in sequence, one side of the frame unit has a first pin, a second pin, a third pin, and a fourth pin arranged in sequence, and the other side has a fifth pin, a sixth pin, a seventh pin, and an eighth pin arranged in sequence, the first base island is connected to the eighth pin, the second base island is connected to the seventh pin, the third base island is connected to the sixth pin, and the fourth base island is connected to the fifth pin.

[0007] Furthermore, the first base island and the fourth base island extend toward the middle of the frame unit to form a first extended base island and a second extended base island respectively.

[0008] Further, the first pin is arranged opposite to the eighth pin, the second pin is arranged opposite to the seventh pin, the third pin is arranged opposite to the sixth pin, and the fourth pin is arranged opposite to the fifth pin.

[0009] Furthermore, the first base island is symmetrically arranged with the fourth base island, the second base island is symmetrically arranged with the third base island, the first pin is symmetrically arranged with the fourth pin, the second pin is symmetrically arranged with the third pin, the fifth pin is symmetrically arranged with the eighth pin, and the sixth pin is symmetrically arranged with the seventh pin.

[0010] An optoelectronic packaging module is obtained by packaging with the multi-island DIP lead frame, wherein a chip is arranged on the island, each frame unit is respectively wrapped by a plastic package, and each pin extends out from two sides of the plastic package.

[0011] Furthermore, MOS chips are respectively arranged on the first base island, the second base island, the third base island and the fourth base island, and IC driver chips and LED chips are respectively arranged on the first extended base island and the second extended base island.

[0012] Beneficial effects of the utility model:

[0013] 1. Through the lead frame structure design, the structure realizes the reasonable layout of multiple base islands in the DIP packaging form, and the pins are reasonably distributed on both sides. Multiple chips can be set up, and even two half-bridge circuits are compatible, which better meets the needs of multi-chip integrated packaging under limited packaging size / space;

[0014] 2. The overall frame adopts the existing DIP8 row layout, making the existing tooling and fixtures compatible, avoiding the investment in equipment and fixtures caused by the frame design;

[0015] 3. Specifically, the first extended base island and the second extended base island are added by extending the first base island and the fourth base island, which can be reasonably used to set the IC driver chip, so as to facilitate the setting of MOS chips on the remaining base islands to form a multi-chip integrated package and facilitate the formation of bonding leads, which is beneficial to the packaging realization and batch preparation of such functional modules, so as to meet the sealing of the main control chip and the device, and realize a system-level packaging function of comprehensive power management, signal control and terminal processing. Compared with discrete devices, the area of ​​the printed circuit board on the device terminal can be greatly reduced, thereby realizing system integration and helping the miniaturization and multi-functionality of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A schematic diagram of the multi-island DIP lead frame structure of an embodiment of the present application is shown.

[0017] Figure 2 A schematic diagram of the frame unit structure of an embodiment of the present application is shown. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solutions and advantages of the embodiments of the utility model clearer, the implementation methods of the utility model are described in detail below in conjunction with the accompanying drawings, but the embodiments described in the utility model are only part of the embodiments of the utility model, rather than all the embodiments.

[0019] In one aspect of an embodiment of the present application, a multi-island DIP lead frame is provided, such as Figure 1 As shown, it includes a plurality of frame units 1 arrayed on the frame body, and the frame units 1 have multiple rows and columns on the frame body, for example, 5 rows in each column. The frame units 1 have multiple pins on both sides, and the middle of the frame units 1 has multiple base islands arranged at intervals, each base island is connected to a different pin on one side, and each pin on the other side is arranged at intervals with the base island.

[0020] Specifically, Figure 2 As shown, the middle part of the frame unit 1 has a first base island 31, a second base island 32, a third base island 33, and a fourth base island 34 arranged in sequence, one side of the frame unit 1 has a first pin 21, a second pin 22, a third pin 23, and a fourth pin 24 arranged in sequence, and the other side has a fifth pin 25, a sixth pin 26, a seventh pin 27, and an eighth pin 28 arranged in sequence, the first base island 31 is connected to the eighth pin 28, the second base island 32 is connected to the seventh pin 27, the third base island 33 is connected to the sixth pin 26, and the fourth base island 34 is connected to the fifth pin 25, and the first pin 21, the second pin 22, the third pin 23, and the fourth pin 24 are independent. The first base island 31 and the fourth base island 34 extend toward the middle part of the frame unit 1 to form a first extended base island 35 and a second extended base island 36, respectively.

[0021] The above structure realizes the formation of 6 reasonably laid out base islands in the DIP8 package form, which can be equipped with 6 chips and compatible with two half-bridge circuits, and can better meet the needs of multi-chip integrated packaging under limited package size / space. The overall frame adopts the existing DIP8 row layout, making the existing tooling and fixtures compatible, avoiding the investment in equipment and fixtures caused by the frame design.

[0022] The first pin 21 is arranged opposite to the eighth pin 28, the second pin 22 is arranged opposite to the seventh pin 27, the third pin 23 is arranged opposite to the sixth pin 26, and the fourth pin 24 is arranged opposite to the fifth pin 25. The first base island 31 is arranged symmetrically with the fourth base island 34, the second base island 32 is arranged symmetrically with the third base island 33, the first pin 21 is arranged symmetrically with the fourth pin 24, the second pin 22 is arranged symmetrically with the third pin 23, the fifth pin 25 is arranged symmetrically with the eighth pin 28, and the sixth pin 26 is arranged symmetrically with the seventh pin 27.

[0023] By arranging the pins and the base island positions, a symmetrical structure is formed, which can well balance the stress on the structure and make the stress uniform and symmetrical.

[0024] The base island and the adjacent side edges of the base island are formed with a locking glue structure 43, such as Figure 2 In the example shown, the glue locking structure 43 is formed on the adjacent sides of the second base island 32 and the third base island 33, and the glue locking structure 43 is a half hole formed on the side of the base island. It can also be set to other shapes according to actual processing convenience or glue locking requirements, thereby enhancing the bonding stability between the base island and the plastic package body and improving the anti-delamination ability.

[0025] In order to improve the stability after packaging, a pin locking hole 41 can be provided on the pin. Figure 2 As shown, since the first pin 21, the second pin 22, the third pin 23, and the fourth pin 24 are spaced apart from the base island, pin locking holes 41 can be provided on them to improve the stability of the pins on this side after packaging.

[0026] The first base island 31 and the fourth base island 34 are connected to the frame body by connecting ribs. Since the first base island 31 and the fourth base island 34 have a long extension area extending toward the middle, in order to improve their strength and flatness, base island glue locking holes 42 can be provided between the first base island 31 and the first extended base island 35 and between the fourth base island 34 and the second extended base island 36 to further reduce the risk of delamination.

[0027] Another aspect of the embodiments of the present application provides an optoelectronic packaging module, which is packaged using the multi-island DIP lead frame described in the previous embodiments, wherein a chip is arranged on the island, each frame unit 1 is respectively wrapped by a plastic package, and each pin extends out from both sides of the plastic package.

[0028] When the base island is the first base island 31, the second base island 32, the third base island 33, the fourth base island 34, and the first base island 31 and the fourth base island 34 are extended to form a first extended base island 35 and a second extended base island 36, the chips can be integrated as follows: MOS chips are respectively arranged on the first base island 31, the second base island 32, the third base island 33, and the fourth base island 34, and IC driver chips are respectively arranged on the first extended base island 35 and the second extended base island 36, and an LED chip is stacked and soldered on each of the IC driver chips. One side of the LED chip on the first extended base island 35 is bonded to the first pin 21 and the second pin 22; the IC driver chip on the first extended base island 35 is bonded to the MOS chips on the first base island 31 and the second base island 32 respectively; one side of the LED chip on the second extended base island 36 is bonded to the third pin 23 and the fourth pin 24; the IC driver chip on the second extended base island 36 is bonded to the MOS chips on the third base island 33 and the fourth base island 34 respectively. Since the first extended base island 35 and the second extended base island 36 are respectively located at the center of the first base island 31, the second base island 32 and the third base island 33, the fourth base island 34, and the two groups are mirror-symmetrical, it is easy to make the gate and source bonding wires of each MOS chip consistent in length, thereby improving the electrical performance of the product.

[0029] This example can reduce the number of components required for terminal integration, thereby greatly reducing investment costs.

[0030] The above is only a preferred embodiment of the utility model, and does not mean that it is the only one or limit the utility model. Those skilled in the art should understand that various changes or equivalent replacements made to the utility model without departing from the scope of the utility model are within the scope of protection of the utility model.

Claims

1. A multi-island DIP lead frame, comprising a plurality of frame units (1) arrayed on a frame body, characterized in that: The frame unit (1) has a plurality of pins on both sides, and a plurality of base islands arranged at intervals in the middle of the frame unit (1), each base island correspondingly connected to a different pin on one side, and each pin on the other side is arranged at intervals from the base island; The frame unit (1) has a first base island (31), a second base island (32), a third base island (33), and a fourth base island (34) arranged in sequence at intervals in the middle; one side of the frame unit (1) has a first pin (21), a second pin (22), a third pin (23), and a fourth pin (24) arranged in sequence at intervals; the other side of the frame unit (1) has a fifth pin (25), a sixth pin (26), a seventh pin (27), and an eighth pin (28) arranged in sequence at intervals; the first base island (31) is connected to the eighth pin (28), the second base island (32) is connected to the seventh pin (27), the third base island (33) is connected to the sixth pin (26), and the fourth base island (34) is connected to the fifth pin (25).

2. The multi-island DIP lead frame according to claim 1, characterized in that: The first base island (31) and the fourth base island (34) respectively extend toward the middle of the frame unit (1) to form a first extended base island (35) and a second extended base island (36).

3. The multi-island DIP lead frame according to claim 1, characterized in that: The first pin (21) is arranged opposite to the eighth pin (28), the second pin (22) is arranged opposite to the seventh pin (27), the third pin (23) is arranged opposite to the sixth pin (26), and the fourth pin (24) is arranged opposite to the fifth pin (25).

4. The multi-island DIP lead frame according to claim 1, characterized in that: The first base island (31) and the fourth base island (34) are symmetrically arranged, the second base island (32) and the third base island (33) are symmetrically arranged, the first pin (21) and the fourth pin (24) are symmetrically arranged, the second pin (22) and the third pin (23) are symmetrically arranged, the fifth pin (25) and the eighth pin (28) are symmetrically arranged, and the sixth pin (26) and the seventh pin (27) are symmetrically arranged.

5. The multi-island DIP lead frame according to claim 1, characterized in that: The base island and the side edges adjacent to the base island are formed with a glue locking structure (43).

6. The multi-island DIP lead frame according to claim 1, characterized in that: At least one pin is provided with a pin glue locking hole (41).

7. The multi-island DIP lead frame according to claim 2, characterized in that: A base island glue locking hole (42) is provided between the first base island (31) and the first extended base island (35) and / or between the fourth base island (34) and the second extended base island (36).

8. An optoelectronic packaging module, characterized in that: The multi-island DIP lead frame according to any one of claims 1 to 7 is used for packaging, a chip is arranged on the island, each frame unit (1) is respectively wrapped by a plastic package, and each pin extends out from both sides of the plastic package.

9. An optoelectronic packaging module, characterized in that: The multi-island DIP lead frame according to claim 2 or 7 is used for packaging, wherein each frame unit (1) is respectively wrapped by a plastic package, each pin extends out from two sides of the plastic package, and MOS chips are respectively arranged on the first base island (31), the second base island (32), the third base island (33), and the fourth base island (34), and an IC driver chip and an LED chip are both arranged on the first extended base island (35) and the second extended base island (36).

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