Voltage buffer and voltage buffer system

Abstract

The utility model discloses a voltage buffer and a voltage buffer system, and relates to the field of voltage buffering, and the voltage buffer is composed of a first amplifier, a first front-end amplification circuit, a second front-end amplification circuit, a second amplifier and a feedback circuit. Wherein the first front-end amplification circuit is high in amplification factor and the number of amplifiers included in the first front-end amplification circuit is smaller than that of the second front-end amplification circuit, so that electric energy transmitted by the reference power supply is transmitted to the second amplifier through the first amplifier and the first front-end amplification circuit, the establishment speed of the output voltage is increased, and meanwhile, the output voltage is increased. And the feedback circuit feeds back the voltage of the output end of the second amplifier to the common output end of the two front-end amplification circuits so as to stabilize the voltage of the output end of the second amplifier. According to the invention, a large capacitor does not need to be connected to an off-chip pin of a chip bonding pad, the number of switching tubes in the amplifier does not need to be increased, the establishment speed of the output voltage can be increased, the stabilization time of the output voltage can be shortened, and the power consumption and the area of a chip are reduced.

Description

Technical Field

[0001] The utility model relates to the field of voltage buffering, in particular to a voltage buffer and a voltage buffer system. Background Art

[0002] The reference voltage has high precision and low temperature drift, and is widely used in analog-to-digital conversion circuits and some precision data acquisition systems. However, the reference voltage has weak driving capability. It is used in high-speed and high-precision analog-to-digital conversion circuits, cannot drive large capacitors, and it is difficult to ensure the stability of the output voltage in a short time under current input and output conditions. In order to compensate for this defect, a voltage buffer is usually added to the chip to improve the driving capability of the reference voltage. However, the existing voltage buffer only includes one output branch and one feedback branch, which is composed of several amplifiers. The output branch is responsible for generating the output voltage, and the feedback branch is responsible for stabilizing the output voltage. In order to ensure that the reference voltage can be quickly established and maintained stable, two methods are generally adopted in the prior art. The first method is to connect a large capacitor to the off-chip pin of the chip pad with the help of a chip pad on the basis of several amplifiers. Although this method has the advantage of low power consumption, the parasitic capacitance and inductance generated by the chip packaging stress, pin welding and other processes are uncertain and may cause oscillation. The second method is to increase the gain and bandwidth of the output branch and the feedback branch, that is, to increase the number of switching tubes in each amplifier. This method is relatively stable, but it requires additional compensation circuits, which will increase the chip area and power consumption. Utility Model Content

[0003] The purpose of the utility model is to provide a voltage buffer and a voltage buffer system. The application does not require the connection of a large capacitor to the off-chip pins of the chip pad, nor does it require an increase in the number of switching tubes in each amplifier, thereby speeding up the output voltage establishment speed and reducing the output voltage stabilization time, thereby reducing the power consumption and area of ​​the chip.

[0004] In order to solve the above technical problems, the utility model provides a voltage buffer, comprising: a first amplifier, a first front-end amplifier circuit, a second front-end amplifier circuit, a second amplifier, and a feedback circuit;

[0005] The input end of the first amplifier is connected to a reference power supply and is used to amplify a reference voltage transmitted by the reference power supply;

[0006] The common input end of the first front-end amplifier circuit and the second front-end amplifier circuit connected in parallel is connected to the output end of the first amplifier, and the common output end is connected to the input end of the second amplifier, and is used to amplify the first voltage transmitted by the first amplifier, and the number of amplifiers included in the second front-end amplifier circuit is greater than the number of amplifiers included in the first front-end amplifier circuit;

[0007] The output end of the second amplifier is connected to the load and the first amplifier, and is used to amplify the second voltage output by the first front-end amplifier circuit and the third voltage output by the second front-end amplifier circuit;

[0008] The input end of the feedback circuit is connected to the output end of the second amplifier, and the output end is connected to the common output end, and is used to feedback the fourth voltage of the output end of the second amplifier to the common output end to control the magnitude of the fourth voltage.

[0009] Optionally, the first front-end amplifier circuit includes a front-end amplifier branch.

[0010] Optionally, the front-end amplification branch includes a third amplifier, and the second front-end amplification circuit includes: a fourth amplifier and a fifth amplifier;

[0011] The fourth amplifier and the fifth amplifier are connected in series and then connected in parallel with the third amplifier. The common input terminal is connected to the output terminal of the first amplifier, and the common output terminal is connected to the input terminal of the second amplifier.

[0012] Optionally, the feedback circuit includes: a sixth amplifier, a seventh amplifier, and an eighth amplifier;

[0013] The input end of the sixth amplifier is connected to the output end of the second amplifier, and the output end is connected to the input end of the seventh amplifier;

[0014] The output end of the seventh amplifier is connected to the input end of the eighth amplifier;

[0015] An output terminal of the eighth amplifier is connected to the common output terminal.

[0016] Optionally, the feedback circuit further includes:

[0017] A ninth amplifier, wherein the input end of the ninth amplifier is connected to the output end of the eighth amplifier, and the output end is connected to the input end of the first front-end amplifier circuit, and is used to feedback the fourth voltage to the input end of the first front-end amplifier circuit to control the magnitude of the fourth voltage.

[0018] Optionally, the first amplifier includes: a first P-type MOS transistor, a second P-type MOS transistor, a third P-type MOS transistor, a fourth P-type MOS transistor, a first N-type MOS transistor, a first current source, a second current source, and a third current source;

[0019] The source of the first P-type MOS transistor is connected to the reference power supply, the gate is connected to the drain of the second P-type MOS transistor, and the drain is connected to the ground;

[0020] The source of the second P-type MOS transistor is connected to the output end of the second amplifier, the gate is connected to the reference power supply, and the drain is connected to the positive electrode of the first current source;

[0021] The negative electrode of the first current source is grounded;

[0022] The source of the third P-type MOS transistor is connected to the output end of the second amplifier, the gate is connected to the reference power supply, and the drain is connected to the positive electrode of the second current source and the source of the fourth P-type MOS transistor;

[0023] The gate of the fourth P-type MOS transistor is connected to the first bias power supply, and the drain is connected to the positive electrode of the third current source and the drain of the first N-type MOS transistor;

[0024] The negative electrode of the second current source is connected to the ground;

[0025] The negative electrode of the third current source is connected to the ground;

[0026] The source of the first N-type MOS transistor is connected to the ground, and the gate is connected to the drain of the first N-type MOS transistor and the common input end of the first front-end amplifier circuit and the second front-end amplifier circuit connected in parallel.

[0027] Optionally, the third amplifier includes: a fifth P-type MOS transistor, a sixth P-type MOS transistor, a second N-type MOS transistor, and a third N-type MOS transistor;

[0028] The source of the second N-type MOS transistor is connected to the ground, the gate is connected to the output end of the first amplifier, and the drain is connected to the drain of the fifth P-type MOS transistor and the gate of the fifth P-type MOS transistor;

[0029] The source of the fifth P-type MOS transistor is connected to a power source, and the gate is connected to the gate of the sixth P-type MOS transistor;

[0030] The source of the sixth P-type MOS transistor is connected to the power supply, and the drain is connected to the drain of the third N-type MOS transistor and the input end of the second amplifier;

[0031] The source of the third N-type MOS tube is connected to the ground, and the gate is connected to the output end of the ninth amplifier.

[0032] Optionally, the fourth amplifier includes: a fourth N-type MOS transistor, a fourth current source, a fifth N-type MOS transistor, a variable current source, a sixth N-type MOS transistor, and a seventh N-type MOS transistor;

[0033] The source of the fourth N-type MOS transistor is connected to the ground, and the gate is connected to the output end of the first amplifier;

[0034] The positive electrode of the fourth current source is connected to the power supply, and the negative electrode is connected to the drain of the fourth N-type MOS tube, the drain of the fifth N-type MOS tube, and the gate of the fifth N-type MOS tube;

[0035] The source of the fifth N-type MOS transistor is connected to the negative electrode of the variable current source, the drain of the sixth N-type MOS transistor and the gate of the sixth N-type MOS transistor;

[0036] The positive electrode of the variable current source is connected to the power supply;

[0037] The source of the sixth N-type MOS transistor is connected to the drain of the seventh N-type MOS transistor, and the gate is connected to the gate of the seventh N-type MOS transistor;

[0038] The source of the seventh N-type MOS transistor is connected to the ground, and the gate is connected to the input end of the fifth amplifier;

[0039] Correspondingly, the fifth amplifier includes: an eighth N-type MOS transistor, a ninth N-type MOS transistor, a seventh P-type MOS transistor, an eighth P-type MOS transistor, a ninth P-type MOS transistor, and a resistor;

[0040] The source of the eighth N-type MOS transistor is connected to the ground, the gate is connected to the gate of the seventh N-type MOS transistor, and the drain is connected to the output end of the feedback circuit, the input end of the second amplifier, and the source of the ninth N-type MOS transistor;

[0041] The gate of the ninth N-type MOS transistor is connected to the second bias power supply, and the drain is connected to the drain of the seventh P-type MOS transistor, the gate of the seventh P-type MOS transistor, the drain of the eighth P-type MOS transistor, and the gate of the eighth P-type MOS transistor;

[0042] The source of the seventh P-type MOS tube is connected to the first end of the resistor;

[0043] The source of the eighth P-type MOS transistor is connected to the second end of the resistor and the drain of the ninth P-type MOS transistor;

[0044] The source of the ninth P-type MOS transistor is connected to the power supply, and the gate is connected to the input end of the second amplifier and the gate of the eighth P-type MOS transistor.

[0045] Optionally, the second amplifier includes: a tenth P-type MOS transistor and a tenth N-type MOS transistor;

[0046] The source of the tenth P-type MOS transistor is connected to the power supply, the gate is connected to the output end of the second front-end amplifier circuit, and the drain is connected to the first amplifier, the drain of the tenth N-type MOS transistor and the input end of the feedback circuit;

[0047] The source of the tenth N-type MOS transistor is connected to the ground, and the gate is connected to the common output terminal.

[0048] In order to solve the above technical problem, the utility model further provides a voltage buffer system, comprising: a load and the voltage buffer as described above, wherein the load is connected to the voltage buffer.

[0049] The purpose of the utility model is to provide a voltage buffer and a voltage buffer system, wherein the voltage buffer is composed of a first amplifier, a first front-end amplifier circuit, a second front-end amplifier circuit, a second amplifier and a feedback circuit, wherein the first front-end amplifier circuit contains fewer amplifiers than the second front-end amplifier circuit, so the electric energy transmitted by the reference power supply is first transmitted to the second amplifier through the first amplifier and the first front-end amplifier circuit, thereby improving the speed of the output voltage establishment process, and at the same time, the feedback circuit can feed back the voltage at the output end of the second amplifier to the common output end of the two front-end amplifier circuits to stabilize the voltage at the output end of the second amplifier. The present application does not require the connection of a large capacitor to the off-chip pin of the chip pad, nor does it require the increase of the number of switch tubes in each amplifier, thereby speeding up the output voltage establishment speed and reducing the output voltage stabilization time, thereby reducing the power consumption and area of ​​the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0051] Figure 1 A schematic diagram of the structure of a voltage buffer provided by the utility model;

[0052] Figure 2 A schematic diagram of the structure of another voltage buffer provided by the utility model;

[0053] Figure 3 This is a schematic structural diagram of another voltage buffer provided by the utility model. DETAILED DESCRIPTION

[0054] The core of the utility model is to provide a voltage buffer and a voltage buffer system. The application does not require the connection of a large capacitor to the off-chip pins of the chip pad, nor does it require an increase in the number of switching tubes in each amplifier. It can speed up the output voltage establishment speed and reduce the output voltage stabilization time, thereby reducing the power consumption and area of ​​the chip.

[0055] In order to make the purpose, technical solution and advantages of the embodiment of the utility model clearer, the technical solution in the embodiment of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiment of the utility model. Obviously, the described embodiment is a part of the embodiment of the utility model, not all of the embodiments. Based on the embodiment of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0056] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the structure of a voltage buffer provided by the utility model. The voltage buffer comprises: a first amplifier 1, a first front-end amplifier circuit 2, a second front-end amplifier circuit 3, a second amplifier 4, and a feedback circuit 5;

[0057] The input terminal of the first amplifier 1 is connected to the reference power supply and is used to amplify the reference voltage transmitted by the reference power supply;

[0058] The common input end of the first front-end amplifier circuit 2 and the second front-end amplifier circuit 3 connected in parallel is connected to the output end of the first amplifier 1, and the common output end is connected to the input end of the second amplifier 4, which is used to amplify the first voltage transmitted by the first amplifier 1, and the number of amplifiers included in the second front-end amplifier circuit 3 is greater than the number of amplifiers included in the first front-end amplifier circuit 2;

[0059] The output end of the second amplifier 4 is connected to the load and the first amplifier 1, and is used to amplify the second voltage output by the first front-end amplifier circuit 2 and the third voltage output by the second front-end amplifier circuit 3;

[0060] The input end of the feedback circuit 5 is connected to the output end of the second amplifier 4 , and the output end is connected to the common output end, and is used to feed back the fourth voltage at the output end of the second amplifier 4 to the common output end to control the magnitude of the fourth voltage.

[0061] In the present invention, there are two paths for establishing the voltage at the output end of the second amplifier 4, the first path is composed of the first amplifier 1, the first front-end amplifier circuit 2 and the second amplifier 4, and the second path is composed of the first amplifier 1, the second front-end amplifier circuit 3 and the second amplifier 4. Because the number of amplifiers included in the second front-end amplifier circuit 3 is greater than the number of amplifiers included in the first front-end amplifier circuit 2, and the first front-end amplifier circuit 2 has a high amplification factor, the first path will generate an output voltage faster than the second path, and the second path, although containing more amplifiers, can have a higher gain and bandwidth. In addition, the feedback circuit 5 provided in the voltage buffer can also feedback the output voltage of the second amplifier 4 to the common output end of the first front-end amplifier circuit 2 and the second front-end amplifier circuit 3 by feedback, and adjust the output voltage of the second amplifier 4 through the action of the two amplifier circuits, thereby stabilizing the output voltage. Compared with the traditional voltage buffer, the voltage buffer of the present application adds a fast signal path (the first front-end amplifier circuit 2) and a feedback loop, speeds up the establishment time of the reference voltage, and after the output voltage of the second amplifier 4 is stabilized, its feedback loop is turned off to reduce current consumption. In addition, the voltage buffer of the present application adopts a step-by-step amplification (multi-stage amplifier) ​​method, which saves additional compensation circuits while ensuring the stability of the output voltage. There is no need to connect a large capacitor to the off-chip pins of the chip pad, nor is there a need to increase the number of switch tubes in each amplifier, which can speed up the output voltage establishment speed and reduce the output voltage stabilization time. Therefore, the voltage buffer provided by the present application reduces the power consumption and area of ​​the chip.

[0062] The present embodiment provides a voltage buffer, wherein the voltage buffer is composed of a first amplifier 1, a first front-end amplifier circuit 2, a second front-end amplifier circuit 3, a second amplifier 4 and a feedback circuit 5. Since the first front-end amplifier circuit 2 has a high amplification factor and contains fewer amplifiers than the second front-end amplifier circuit 3, the electric energy transmitted by the reference power supply is first transmitted to the second amplifier 4 through the first amplifier 1 and the first front-end amplifier circuit 2, thereby improving the speed of the output voltage establishment process. At the same time, the feedback circuit 5 can feed back the voltage at the output end of the second amplifier 4 to the common output end of the two front-end amplifier circuits to stabilize the voltage at the output end of the second amplifier 4. The present application does not require the connection of a large capacitor to the off-chip pin of the chip pad, nor does it require the increase of the number of switch tubes in each amplifier, thereby accelerating the speed of establishing the output voltage and reducing the stabilization time of the output voltage, thereby reducing the power consumption and area of ​​the chip.

[0063] Based on the above embodiments:

[0064] Please refer to Figure 2 , Figure 2A schematic diagram of the structure of a voltage buffer provided by the utility model. As an optional embodiment, the first front-end amplifier circuit 2 includes a front-end amplifier branch.

[0065] In the utility model, only one front-end amplification branch is provided in the first front-end amplification circuit 2, which can further improve the establishment speed of the output voltage of the second amplifier 4 and reduce the stabilization time of the output voltage of the second amplifier 4.

[0066] As an optional embodiment, the front-end amplification branch includes a third amplifier, and the second front-end amplification circuit 3 includes: a fourth amplifier and a fifth amplifier;

[0067] The fourth amplifier and the fifth amplifier are connected in series and in parallel with the third amplifier, the common input end is connected to the output end of the first amplifier 1 , and the common output end is connected to the input end of the second amplifier 4 .

[0068] In the utility model, the front-end amplifier branch only includes the third amplifier, that is, the first front-end amplifier circuit 2 includes only one amplifier, and the second front-end amplifier circuit 3 includes two amplifiers, which are the fourth amplifier and the fifth amplifier. Because the first front-end amplifier circuit 2 has a high amplification factor and the number of amplifiers it contains is less than the number of amplifiers included in the second front-end amplifier circuit 3, the first front-end amplifier circuit 2 can make the output voltage of the second amplifier 4 establish faster, and the second front-end amplifier circuit 3 contains more amplifiers and also provides greater gain and bandwidth, thereby ensuring the reliability of the solution.

[0069] As an optional embodiment, the feedback circuit 5 includes: a sixth amplifier, a seventh amplifier, and an eighth amplifier;

[0070] The input end of the sixth amplifier is connected to the output end of the second amplifier 4, and the output end is connected to the input end of the seventh amplifier;

[0071] The output terminal of the seventh amplifier is connected to the input terminal of the eighth amplifier;

[0072] An output terminal of the eighth amplifier is connected to the common output terminal.

[0073] In the utility model, a sixth amplifier, a seventh amplifier, and an eighth amplifier are provided in the feedback circuit 5. The reason for providing three amplifiers is that considering the gain and bandwidth of the feedback circuit 5, the voltage at the output end of the second amplifier 4 can be more stably fed back to the common output end of the first front-end amplifier circuit 2 and the second front-end amplifier circuit 3, thereby reducing the stabilization time of the voltage at the output end of the second amplifier 4.

[0074] As an optional embodiment, the feedback circuit 5 further includes:

[0075] A ninth amplifier, the input end of the ninth amplifier is connected to the output end of the eighth amplifier, and the output end is connected to the input end of the first front-end amplifier circuit 2, and is used to feedback the fourth voltage to the input end of the first front-end amplifier circuit 2 to control the magnitude of the fourth voltage.

[0076] In the utility model, in order to ensure stable regulation of the voltage at the output end of the second amplifier 4, a ninth amplifier is further provided in the feedback circuit 5. The output voltage of the second amplifier 4 is amplified by the sixth amplifier, the seventh amplifier, the eighth amplifier and the ninth amplifier in sequence, and then the amplified voltage is output to the input end of the first front-end amplifier circuit 2 through the ninth amplifier. Then, through the regulation of the first front-end amplifier circuit 2, the voltage at the output end of the second amplifier 4 can be stabilized, thereby improving the stability of the solution.

[0077] As an optional embodiment, the first amplifier 1 includes: a first P-type MOS transistor MP1, a second P-type MOS transistor MP2, a third P-type MOS transistor MP3, a fourth P-type MOS transistor MP4, a first N-type MOS transistor MN1, a first current source I1, a second current source I2, and a third current source I3;

[0078] The source of the first P-type MOS transistor MP1 is connected to the reference power supply, the gate is connected to the drain of the second P-type MOS transistor MP2, and the drain is connected to the ground;

[0079] The source of the second P-type MOS transistor MP2 is connected to the output end of the second amplifier 4, the gate is connected to the reference power supply, and the drain is connected to the positive electrode of the first current source I1;

[0080] The negative electrode of the first current source I1 is grounded;

[0081] The source of the third P-type MOS transistor MP3 is connected to the output end of the second amplifier 4, the gate is connected to the reference power supply, and the drain is connected to the positive electrode of the second current source I2 and the source of the fourth P-type MOS transistor MP4;

[0082] The gate of the fourth P-type MOS transistor MP4 is connected to the first bias power supply, and the drain is connected to the positive electrode of the third current source I3 and the drain of the first N-type MOS transistor MN1;

[0083] The negative electrode of the second current source I2 is connected to the ground;

[0084] The negative electrode of the third current source I3 is connected to the ground;

[0085] The source of the first N-type MOS transistor MN1 is connected to the ground, and the gate is connected to the drain of the first N-type MOS transistor MN1 and the common input terminal of the first front-end amplifier circuit 2 and the second front-end amplifier circuit 3 connected in parallel.

[0086] In the utility model, the first amplifier 1 is provided with a first P-type MOS transistor MP1, a second P-type MOS transistor MP2, a third P-type MOS transistor MP3, a fourth P-type MOS transistor MP4, a first N-type MOS transistor MN1, a first current source I1, a second current source I2, and a third current source I3, wherein the first P-type MOS transistor MP1, the second P-type MOS transistor MP2 and the first current source I1 form a negative feedback loop, that is, when the voltage provided by the reference power supply increases, the gate voltage of the second P-type MOS transistor MP2 increases, and the drain voltage of the second P-type MOS transistor MP2 decreases. Because the drain of the second P-type MOS transistor MP2 is connected to the gate of the first P-type MOS transistor MP1, the first P-type MOS transistor MP 1, the source voltage of the first P-type MOS tube MP1 is reduced, and the stability of the input voltage provided by the reference power supply can be controlled by this negative feedback method, and the third P-type MOS tube MP3 and the fourth P-type MOS tube MP4 are a common source and common gate structure, which can improve the amplification factor. In addition, the first N-type MOS tube MN1, the fourth N-type MOS tube MN4, and the second N-type MOS tube MN2 all form a current mirror, which can convert the voltage provided by the reference power supply into a current, and transmit it to the first front-end amplifier circuit 2 and the second front-end amplifier circuit 3 in a mirroring manner, wherein most of the drain current of the third P-type MOS tube MP3 flows to the ground through the second current source I2 and the third current source I3 to avoid consuming too much current.

[0087] As an optional embodiment, the third amplifier includes: a fifth P-type MOS transistor MP5, a sixth P-type MOS transistor MP6, a second N-type MOS transistor MN2, and a third N-type MOS transistor MN3;

[0088] The source of the second N-type MOS transistor MN2 is connected to the ground, the gate is connected to the output end of the first amplifier 1, and the drain is connected to the drain of the fifth P-type MOS transistor MP5 and the gate of the fifth P-type MOS transistor MP5;

[0089] The source of the fifth P-type MOS transistor MP5 is connected to the power supply, and the gate is connected to the gate of the sixth P-type MOS transistor MP6;

[0090] The source of the sixth P-type MOS transistor MP6 is connected to the power supply, and the drain is connected to the drain of the third N-type MOS transistor MN3 and the input end of the second amplifier 4;

[0091] The source of the third N-type MOS transistor MN3 is connected to the ground, and the gate is connected to the output end of the ninth amplifier.

[0092] In the utility model, the third amplifier is provided with a fifth P-type MOS transistor MP5, a sixth P-type MOS transistor MP6, a second N-type MOS transistor MN2, and a third N-type MOS transistor MN3, wherein the fifth P-type MOS transistor MP5 and the sixth P-type MOS transistor MP6 form a current mirror, the second N-type MOS transistor MN2 is used as an amplifier, and the third N-type MOS transistor MN3 receives a feedback signal transmitted by a feedback circuit 5. When the voltage output by the first amplifier 1 increases, the second N-type MOS transistor MN2 is turned on, and the gate potential of the sixth P-type MOS transistor MP6 is quickly pulled down through the action of the current mirror, so that the sixth P-type MOS transistor MP6 is turned on, and then the tenth N-type MOS transistor in the second amplifier 4 is turned on, and an output voltage is generated. When the output voltage of the second amplifier 4 is too large, the third N-type MOS transistor MN3 is turned on through the feedback of the feedback circuit 5, and then the gate potential of the third N-type MOS transistor MN3, that is, the input potential of the second amplifier 4 is pulled to a stable state. In addition, when the voltage buffer works normally, that is, the output voltage of the second amplifier 4 is stable, the third N-type MOS transistor MN3 is turned off, and the feedback circuit 5 is disconnected.

[0093] As an optional embodiment, the fourth amplifier includes: a fourth N-type MOS transistor MN4, a fourth current source I4, a fifth N-type MOS transistor MN5, a variable current source IS, a sixth N-type MOS transistor MN6, and a seventh N-type MOS transistor MN7;

[0094] The source of the fourth N-type MOS transistor MN4 is connected to the ground, and the gate is connected to the output end of the first amplifier 1;

[0095] The positive electrode of the fourth current source I4 is connected to the power supply, and the negative electrode is connected to the drain of the fourth N-type MOS transistor MN4, the drain of the fifth N-type MOS transistor MN5, and the gate of the fifth N-type MOS transistor MN5;

[0096] The source of the fifth N-type MOS transistor MN5 is connected to the negative electrode of the variable current source IS, the drain of the sixth N-type MOS transistor MN6 and the gate of the sixth N-type MOS transistor MN6;

[0097] The positive electrode of the variable current source IS is connected to the power supply;

[0098] The source of the sixth N-type MOS transistor MN6 is connected to the drain of the seventh N-type MOS transistor MN7, and the gate of the sixth N-type MOS transistor MN6 is connected to the gate of the seventh N-type MOS transistor MN7;

[0099] The source of the seventh N-type MOS transistor MN7 is connected to the ground, and the gate is connected to the input end of the fifth amplifier;

[0100] Correspondingly, the fifth amplifier includes: an eighth N-type MOS transistor MN8, a ninth N-type MOS transistor MN9, a seventh P-type MOS transistor MP7, an eighth P-type MOS transistor MP8, a ninth P-type MOS transistor MP9, and a resistor R;

[0101] The source of the eighth N-type MOS transistor MN8 is connected to the ground, the gate is connected to the gate of the seventh N-type MOS transistor MN7, and the drain is connected to the output end of the feedback circuit 5, the input end of the second amplifier 4, and the source of the ninth N-type MOS transistor MN9;

[0102] The gate of the ninth N-type MOS transistor MN9 is connected to the second bias power supply, and the drain is connected to the drain of the seventh P-type MOS transistor MP7, the gate of the seventh P-type MOS transistor MP7, the drain of the eighth P-type MOS transistor MP8, and the gate of the eighth P-type MOS transistor MP8;

[0103] The source of the seventh P-type MOS transistor MP7 is connected to the first end of the resistor R;

[0104] The source of the eighth P-type MOS transistor MP8 is connected to the second end of the resistor R and the drain of the ninth P-type MOS transistor MP9;

[0105] The source of the ninth P-type MOS transistor MP9 is connected to the power supply, and the gate is connected to the input end of the second amplifier 4 and the gate of the eighth P-type MOS transistor MP8.

[0106] In the utility model, the fourth amplifier is provided with a fourth N-type MOS tube MN4, a fourth current source I4, a fifth N-type MOS tube MN5, a variable current source IS, a sixth N-type MOS tube MN6, and a seventh N-type MOS tube MN7, wherein the current value of the variable current source IS can be changed by adjusting the fuse, the fourth N-type MOS tube MN4 is used as an amplifier, the current difference between the fourth current source I4 and the drain current of the fourth N-type MOS tube MN4 will flow out through the fifth N-type MOS tube MN5, this part of the current difference will also be superimposed with the current of the variable current source IS, and flow into the sixth N-type MOS tube MN6 and the seventh N-type MOS tube MN7, and finally will be output to the fifth amplifier through the seventh N-type MOS tube MN7 in a current mirror mode. The fifth amplifier is provided with an eighth N-type MOS tube MN8, a ninth N-type MOS tube MN9, a seventh P-type MOS tube MP7, an eighth P-type MOS tube MP8, a ninth P-type MOS tube MP9, and a resistor R, wherein the eighth N-type MOS tube MN8 is used as an amplifier, and the ninth N-type MOS tube MN9 is used to increase the gain. The seventh P-type MOS transistor MP7 , the eighth P-type MOS transistor MP8 , the ninth P-type MOS transistor MP9 and the resistor R constitute a micro-current source. The main function of the fifth amplifier is to increase the gain and bandwidth of the second front-end amplifier circuit 3 .

[0107] As an optional embodiment, the second amplifier 4 includes: a tenth P-type MOS transistor MP10 and a tenth N-type MOS transistor MN10;

[0108] The source of the tenth P-type MOS transistor MP10 is connected to the power supply, the gate is connected to the output end of the second front-end amplifier circuit 3, and the drain is connected to the first amplifier 1, the drain of the tenth N-type MOS transistor MN10 and the input end of the feedback circuit 5;

[0109] The source of the tenth N-type MOS transistor MN10 is connected to the ground, and the gate is connected to the common output terminal.

[0110] In the present invention, the second amplifier 4 is provided with a tenth P-type MOS transistor MP10 and a tenth N-type MOS transistor MN10. The drain of the tenth P-type MOS transistor MP10 is actually connected to the source of the second P-type MOS transistor MP2 and the source of the third P-type MOS transistor MP3 of the first amplifier 1. The tenth P-type MOS transistor MP10 and the tenth N-type MOS transistor MN10 belong to class AB output (class A and B amplifier circuit), that is, Class-AB. This circuit can avoid the problem of crossover distortion (dead zone when the input absolute value is less than Vth) of the class B amplifier, and can also avoid the problem of large distortion of the class A amplifier. DC power consumption. In addition, when the tenth N-type MOS transistor MN10 is turned on, the output voltage of the second amplifier 4 is established first. However, because the output end of the second amplifier 4, that is, the drain of the tenth P-type MOS transistor MP10 is also connected to the source of the second P-type MOS transistor MP2 in the first amplifier 1, the source of the third P-type MOS transistor MP3 and the feedback circuit 5, the drain voltage of the tenth P-type MOS transistor MP10 (the output voltage of the second amplifier 4) can also be stabilized through the second P-type MOS transistor MP2, the third P-type MOS transistor MP3 and the feedback circuit 5 in the first amplifier 1.

[0111] It should be noted that if Figure 3 As shown, in actual application, the fast signal path (first amplifier 1, first front-end amplifier circuit 2, second amplifier 4) is first used to accelerate the start-up and generate the output voltage, and then the feedback circuit 5 between the output and the fast signal path is used to complete a preliminary establishment process for the output voltage, and then the feedback circuit 5 between the output and the fast signal path is turned off and no longer works; the feedback loop between the output and the last amplifier (second amplifier 4) inside the main signal path (first amplifier 1, second front-end amplifier circuit 3, second amplifier 4) detects the output voltage, and when the load current at the output end changes, this loop can respond quickly to ensure the stability of the output voltage; the main signal path adopts a step-by-step amplification method to gradually increase the loop gain and bandwidth, and does not require redundant compensation circuits; the output is fed back to the first amplifier 1 as a power supply to ensure that a V is always maintained between the input and the output GSof pressure difference.

[0112] It should also be noted that if Figure 3 As shown, in actual application, the sixth amplifier is generally provided with an eleventh P-type MOS transistor MP11, a twelfth P-type MOS transistor MP12, and an eleventh N-type MOS transistor MN11. The connection relationship is: the source of the eleventh P-type MOS transistor MP11 is connected to the output end of the second amplifier 4, and the gate is connected to the gate of the twelfth P-type MOS transistor MP12 and the input end of the seventh amplifier; the source of the twelfth P-type MOS transistor MP12 is connected to the drain of the eleventh P-type MOS transistor MP11, and the drain is connected to the input end of the seventh amplifier and the drain of the eleventh N-type MOS transistor MN11; the source of the eleventh N-type MOS transistor MN11 is grounded, and the gate is connected to the third bias power supply. In addition, because the source of the eleventh P-type MOS transistor MP11 is connected to the drain of the tenth P-type MOS transistor MP10 (the output end of the second amplifier 4), the output end voltage of the second amplifier 4 will be reduced by one V GS The size of the output is then output to the seventh amplifier, and the eleventh N-type MOS tube MN11 is used to provide tail current.

[0113] It should also be noted that if Figure 3As shown, in actual application, the seventh amplifier is generally provided with a thirteenth P-type MOS transistor MP13, a fourteenth P-type MOS transistor MP14, a fifteenth P-type MOS transistor MP15, a fifth current source I5, and a sixth current source I6. The connection relationship is as follows: the source of the thirteenth P-type MOS transistor MP13 is connected to the power supply, the gate is connected to the third reference power supply, and the drain is connected to the source of the fourteenth P-type MOS transistor MP14 and the source of the fifteenth P-type MOS transistor MP15; the gate of the fourteenth P-type MOS transistor MP14 is connected to the output end of the sixth amplifier, and the drain is connected to the positive electrode of the fifth current source I5; the negative electrode of the fifth current source I5 is grounded; the gate of the fifteenth P-type MOS transistor MP15 is connected to the output end of the sixth amplifier, and the drain is connected to the input end of the eighth amplifier and the positive electrode of the sixth current source I6; the negative electrode of the sixth current source I6 is grounded. In addition, the fifteenth P-type MOS transistor MP15 is used as an amplifier, and the current of the thirteenth P-type MOS transistor MP13 is equivalent to that obtained by the ninth P-type MOS transistor MP9. In order to ensure the gain of the seventh amplifier, the sixth current source I6 is generally greater than the fifth current source I5. When the load current of the output terminal of the second amplifier 4 to the ground is too large, the output voltage of the second amplifier 4 will be pulled down. At the same time, the output voltage of the sixth amplifier will be reduced. Because the output terminal of the sixth amplifier is connected to the gate of the fifteenth P-type MOS transistor MP15, when the output voltage of the sixth amplifier is reduced, the drain current of the fifteenth P-type MOS transistor MP15 is increased. The voltage (output voltage of the seventh amplifier) ​​will also increase, thereby turning on the thirteenth N-type MOS transistor MN13 and the fourteenth N-type MOS transistor MN14 in the eighth amplifier, increasing the gate voltage of the tenth N-type MOS transistor MN10, increasing the decreasing speed of the output voltage of the second amplifier 4, and forming positive feedback between the sixth amplifier, the seventh amplifier, and the eighth amplifier, thereby accelerating the voltage response speed at the output end of the second amplifier 4; similarly, when the output voltage of the second amplifier 4 is too large for the load current of the power supply, the output voltage of the second amplifier 4 increases, and the sixth amplifier, the seventh amplifier, and the eighth amplifier accelerate the voltage increase speed at the output end of the second amplifier 4. In a normal state, the drain current of the thirteenth P-type MOS transistor MP13 is less than the current of the sixth current source I6, so the drain voltage of the fifteenth P-type MOS transistor MP15 is relatively low, and the thirteenth N-type MOS transistor MN13 and the fourteenth N-type MOS transistor MN14 in the eighth amplifier are in the off state.

[0114] It should also be noted that if Figure 3As shown, in practical applications, the eighth amplifier is generally provided with a twelfth N-type MOS transistor MN12, a thirteenth N-type MOS transistor MN13, a fourteenth N-type MOS transistor MN14, a fifteenth N-type MOS transistor MN15, a sixteenth N-type MOS transistor MN16, and a seventeenth N-type MOS transistor MN17. The connection relationship is as follows: the source of the twelfth N-type MOS transistor MN12 is connected to the drain of the thirteenth N-type MOS transistor MN13 and the drain of the fourteenth N-type MOS transistor MN14, the gate is connected to the fourth bias power supply, and the drain is connected to the power supply; the source of the thirteenth N-type MOS transistor MN13 is connected to the drain of the fifteenth N-type MOS transistor MN15 and the common output terminal of the first front-end amplifier circuit 2 and the second front-end amplifier circuit 3, and the gate is connected to the output terminal of the seventh amplifier; the source of the fourteenth N-type MOS transistor MN14 is connected to the drain of the sixteenth N-type MOS transistor MN16, and the gate is connected to the output terminal of the seventh amplifier; the source of the fifteenth N-type MOS transistor MN15 is connected to the drain of the seventeenth N-type MOS transistor MN17, and the gate is connected to the output terminal of the second front-end amplifier circuit 3; the source of the sixteenth N-type MOS transistor MN16 is connected to the ground, and the gate is connected to the fifth bias power supply; the source of the seventeenth N-type MOS transistor MN17 is connected to the ground, and the gate is connected to the common output terminal of the first front-end amplifier circuit 2 and the second front-end amplifier circuit 3 and the input terminal of the ninth amplifier.

[0115] It should also be noted that if Figure 3As shown, in actual application, the ninth amplifier is generally provided with a sixteenth P-type MOS transistor MP16, a seventeenth P-type MOS transistor MP17, an eighteenth P-type MOS transistor MP18, a nineteenth P-type MOS transistor MP19, an eighteenth N-type MOS transistor MN18, a nineteenth N-type MOS transistor MN19, and a seventh current source I7, and the connection relationship is as follows: the source of the sixteenth P-type MOS transistor MP16 is connected to the power supply, the gate is connected to the gate of the seventeenth P-type MOS transistor MP17, the gate of the eighteenth P-type MOS transistor MP18, and the gate of the nineteenth P-type MOS transistor MP19, and the drain is connected to the source of the eighteenth P-type MOS transistor MP18; the seventeenth P-type MOS transistor MP17 is connected to the power supply, the gate is connected to the gate of the seventeenth P-type MOS transistor MP17, the gate of the eighteenth P-type MOS transistor MP18, and the gate of the nineteenth P-type MOS transistor MP19, and the drain is connected to the source of the eighteenth P-type MOS transistor MP18; The source is connected to the power supply, and the drain is connected to the source of the nineteenth P-type MOS transistor MP19; the drain of the eighteenth P-type MOS transistor MP18 is connected to the gate of the eighteenth P-type MOS transistor MP18 and the drain of the eighteenth N-type MOS transistor MN18; the drain of the nineteenth P-type MOS transistor MP19 is connected to the positive electrode of the seventh current source I7 and the gate of the third N-type MOS transistor MN3; the source of the eighteenth N-type MOS transistor MN18 is connected to the drain of the nineteenth N-type MOS transistor MN19, and the gate is connected to the gate of the nineteenth N-type MOS transistor MN19; the source of the nineteenth N-type MOS transistor MN19 is grounded, and the gate is connected to the output end of the eighth amplifier; the negative electrode of the seventh current source I7 is grounded. In addition, when the gate voltage of the tenth N-type MOS transistor MN10 increases, the drain voltage of the nineteenth P-type MOS transistor MP19 also increases, the third N-type MOS transistor MN3 is turned on, and prevents the gate voltage of the tenth N-type MOS transistor MN10 from increasing, so the ninth amplifier and the third N-type MOS transistor MN3 form a negative feedback loop for stabilizing the gate voltage of the tenth N-type MOS transistor MN10.

[0116] The utility model also provides a corresponding embodiment of a voltage buffer system, comprising: a load and the voltage buffer as described above, wherein the load is connected to the voltage buffer.

[0117] The voltage buffer system provided in this embodiment corresponds to the above-mentioned voltage buffer, and thus has the same beneficial effects as the above-mentioned voltage buffer. Therefore, for the embodiments of the voltage buffer system, please refer to the description of the embodiments of the voltage buffer, which will not be described here.

[0118] It should be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0119] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A voltage buffer, characterized in that: include: A first amplifier, a first front-end amplifier circuit, a second front-end amplifier circuit, a second amplifier, and a feedback circuit; The input end of the first amplifier is connected to a reference power supply and is used to amplify a reference voltage transmitted by the reference power supply; The common input end of the first front-end amplifier circuit and the second front-end amplifier circuit connected in parallel is connected to the output end of the first amplifier, and the common output end is connected to the input end of the second amplifier, and is used to amplify the first voltage transmitted by the first amplifier, and the number of amplifiers included in the second front-end amplifier circuit is greater than the number of amplifiers included in the first front-end amplifier circuit; The output end of the second amplifier is connected to the load and the first amplifier, and is used to amplify the second voltage output by the first front-end amplifier circuit and the third voltage output by the second front-end amplifier circuit; The input end of the feedback circuit is connected to the output end of the second amplifier, and the output end is connected to the common output end, and is used to feedback the fourth voltage of the output end of the second amplifier to the common output end to control the magnitude of the fourth voltage.

2. The voltage buffer according to claim 1, wherein: The first front-end amplifier circuit includes a front-end amplifier branch.

3. The voltage buffer according to claim 2, characterized in that The front-end amplification branch includes a third amplifier, and the second front-end amplification circuit includes: a fourth amplifier and a fifth amplifier; The fourth amplifier and the fifth amplifier are connected in series and then connected in parallel with the third amplifier. The common input terminal is connected to the output terminal of the first amplifier, and the common output terminal is connected to the input terminal of the second amplifier.

4. The voltage buffer according to claim 1, wherein: The feedback circuit comprises: a sixth amplifier, a seventh amplifier, and an eighth amplifier; The input end of the sixth amplifier is connected to the output end of the second amplifier, and the output end is connected to the input end of the seventh amplifier; The output end of the seventh amplifier is connected to the input end of the eighth amplifier; An output terminal of the eighth amplifier is connected to the common output terminal.

5. The voltage buffer according to claim 4, characterized in that The feedback circuit further includes: A ninth amplifier, wherein the input end of the ninth amplifier is connected to the output end of the eighth amplifier, and the output end is connected to the input end of the first front-end amplifier circuit, and is used to feedback the fourth voltage to the input end of the first front-end amplifier circuit to control the magnitude of the fourth voltage.

6. The voltage buffer according to claim 1, wherein: The first amplifier includes: a first P-type MOS transistor, a second P-type MOS transistor, a third P-type MOS transistor, a fourth P-type MOS transistor, a first N-type MOS transistor, a first current source, a second current source, and a third current source; The source of the first P-type MOS transistor is connected to the reference power supply, the gate is connected to the drain of the second P-type MOS transistor, and the drain is connected to the ground; The source of the second P-type MOS transistor is connected to the output end of the second amplifier, the gate is connected to the reference power supply, and the drain is connected to the positive electrode of the first current source; The negative electrode of the first current source is grounded; The source of the third P-type MOS transistor is connected to the output end of the second amplifier, the gate is connected to the reference power supply, and the drain is connected to the positive electrode of the second current source and the source of the fourth P-type MOS transistor; The gate of the fourth P-type MOS transistor is connected to the first bias power supply, and the drain is connected to the positive electrode of the third current source and the drain of the first N-type MOS transistor; The negative electrode of the second current source is connected to the ground; The negative electrode of the third current source is connected to the ground; The source of the first N-type MOS transistor is connected to the ground, and the gate is connected to the drain of the first N-type MOS transistor and the common input end of the first front-end amplifier circuit and the second front-end amplifier circuit connected in parallel.

7. The voltage buffer according to claim 3, characterized in that The third amplifier includes: a fifth P-type MOS transistor, a sixth P-type MOS transistor, a second N-type MOS transistor, and a third N-type MOS transistor; The source of the second N-type MOS transistor is connected to the ground, the gate is connected to the output end of the first amplifier, and the drain is connected to the drain of the fifth P-type MOS transistor and the gate of the fifth P-type MOS transistor; The source of the fifth P-type MOS transistor is connected to a power source, and the gate is connected to the gate of the sixth P-type MOS transistor; The source of the sixth P-type MOS transistor is connected to the power supply, and the drain is connected to the drain of the third N-type MOS transistor and the input end of the second amplifier; The source of the third N-type MOS tube is connected to the ground, and the gate is connected to the output end of the ninth amplifier.

8. The voltage buffer according to claim 3, wherein: The fourth amplifier includes: a fourth N-type MOS transistor, a fourth current source, a fifth N-type MOS transistor, a variable current source, a sixth N-type MOS transistor, and a seventh N-type MOS transistor; The source of the fourth N-type MOS transistor is connected to the ground, and the gate is connected to the output end of the first amplifier; The positive electrode of the fourth current source is connected to the power supply, and the negative electrode is connected to the drain of the fourth N-type MOS tube, the drain of the fifth N-type MOS tube, and the gate of the fifth N-type MOS tube; The source of the fifth N-type MOS transistor is connected to the negative electrode of the variable current source, the drain of the sixth N-type MOS transistor and the gate of the sixth N-type MOS transistor; The positive electrode of the variable current source is connected to the power supply; The source of the sixth N-type MOS transistor is connected to the drain of the seventh N-type MOS transistor, and the gate is connected to the gate of the seventh N-type MOS transistor; The source of the seventh N-type MOS transistor is connected to the ground, and the gate is connected to the input end of the fifth amplifier; Correspondingly, the fifth amplifier includes: an eighth N-type MOS transistor, a ninth N-type MOS transistor, a seventh P-type MOS transistor, an eighth P-type MOS transistor, a ninth P-type MOS transistor, and a resistor; The source of the eighth N-type MOS transistor is connected to the ground, the gate is connected to the gate of the seventh N-type MOS transistor, and the drain is connected to the output end of the feedback circuit, the input end of the second amplifier, and the source of the ninth N-type MOS transistor; The gate of the ninth N-type MOS transistor is connected to the second bias power supply, and the drain is connected to the drain of the seventh P-type MOS transistor, the gate of the seventh P-type MOS transistor, the drain of the eighth P-type MOS transistor, and the gate of the eighth P-type MOS transistor; The source of the seventh P-type MOS tube is connected to the first end of the resistor; The source of the eighth P-type MOS transistor is connected to the second end of the resistor and the drain of the ninth P-type MOS transistor; The source of the ninth P-type MOS transistor is connected to the power supply, and the gate is connected to the input end of the second amplifier and the gate of the eighth P-type MOS transistor.

9. The voltage buffer according to any one of claims 1 to 8, characterized in that: The second amplifier includes: a tenth P-type MOS transistor and a tenth N-type MOS transistor; The source of the tenth P-type MOS transistor is connected to the power supply, the gate is connected to the output end of the second front-end amplifier circuit, and the drain is connected to the first amplifier, the drain of the tenth N-type MOS transistor and the input end of the feedback circuit; The source of the tenth N-type MOS transistor is connected to the ground, and the gate is connected to the common output terminal.

10. A voltage buffer system, characterized in that: include: A load and a voltage buffer according to any one of claims 1 to 9, wherein the load is connected to the voltage buffer.

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