Simple AND gate circuit
By using open-drain output circuits and resistors to build circuits in the AND gate circuit, the problem of high cost of existing AND gate circuits is solved, and circuit simplification and cost reduction are achieved.
Patent Information
- Application Number
- CN202421848307.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-31
- Publication Date
- 2025-05-16
- Estimated Expiration
- 2034-07-31
AI Technical Summary
The existing AND gate circuit is mainly constructed through dedicated integrated circuit chips, resulting in a high overall product cost.
By setting a first resistor on the first input branch and setting a second resistor on the second input branch, the input end of the second input branch is connected to the open-drain output circuit, the output end of the first input branch and the output end of the second input branch are connected to the output branch, and the resistance value of the first resistor is greater than the resistance value of the second resistor, the AND gate circuit is constructed using the characteristics of the open-drain output circuit.
The circuit structure is simplified and the cost is reduced. Only two resistors and one field effect transistor are required to build an AND gate circuit.
Smart Images
Figure CN222884664U_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present application relate to the field of electronic circuits, and in particular to a simple AND gate circuit. Background Art
[0002] The AND gate circuit is a basic logic gate circuit that performs the "AND" operation. The AND gate circuit can have multiple input terminals and one output terminal. When all inputs are high level (logic 1) at the same time, the output is high level, otherwise the output is low level (logic 0). The current AND gate circuit is mainly constructed by dedicated integrated circuit chips (Integrated Circuit Chip), which will increase the overall cost of the product. Utility Model Content
[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.
[0004] The purpose of the present application is to solve one of the technical problems existing in the related art to at least a certain extent. The embodiment of the present application provides a simple AND gate circuit to simplify the circuit and reduce the cost.
[0005] An embodiment of the first aspect of the present application, a simple AND gate circuit, includes:
[0006] at least one first input branch, wherein the first input branch is provided with a first resistor;
[0007] a second input branch, wherein the second input branch is provided with a second resistor, and a third end of the second input branch is connected to an open-drain output circuit;
[0008] an output branch, wherein the second end of the first input branch and the fourth end of the second input branch are connected to the fifth end of the output branch;
[0009] The resistance value of the first resistor is greater than the resistance value of the second resistor.
[0010] According to certain embodiments of the first aspect of the present application, the first end of the first input branch is a level input end, and the third end of the second input branch is a level input end.
[0011] According to certain embodiments of the first aspect of the present application, the open-drain output circuit includes a field effect transistor, a source of the field effect transistor is grounded, and a drain of the field effect transistor is connected to the third end of the second input branch.
[0012] According to certain embodiments of the first aspect of the present application, the field effect transistor includes at least one of a junction field effect transistor and an insulated gate field effect transistor.
[0013] According to certain embodiments of the first aspect of the present application, the resistance value of the first resistor is 110k ohms, and the resistance value of the second resistor is 0 ohms.
[0014] According to certain embodiments of the first aspect of the present application, the sixth end of the output branch is an AND gate output end.
[0015] According to certain embodiments of the first aspect of the present application, when the first input branch inputs a high level, the second input branch inputs a high level, the first resistor serves as a pull-up resistor of the open-drain output circuit, the fourth end of the second input branch outputs a high level, and the output branch outputs a high level.
[0016] According to certain embodiments of the first aspect of the present application, when the first input branch inputs a low level and the second input branch inputs a high level, the first resistor serves as a pull-down resistor of the open-drain output circuit, the fourth end of the second input branch outputs a low level, and the output branch outputs a low level.
[0017] According to certain embodiments of the first aspect of the present application, when the first input branch inputs a high level, the second input branch inputs a low level, the fourth end of the second input branch outputs a low level, and the output branch outputs a low level.
[0018] According to certain embodiments of the first aspect of the present application, when the first input branch inputs a low level, the second input branch inputs a low level, the fourth end of the second input branch outputs a low level, and the output branch outputs a low level.
[0019] The above scheme has at least the following beneficial effects: by setting a first resistor in the first input branch and a second resistor in the second input branch, the input end of the second input branch is connected to the open-drain output circuit, the output end of the first input branch and the output end of the second input branch are connected to the output branch, and the resistance value of the first resistor is greater than the resistance value of the second resistor; utilizing the characteristics of the open-drain output circuit, when the open-drain output circuit is open-drain, the first resistor acts as a pull-up resistor or a pull-down resistor to control the level of the second input branch, and then control the output level of the output branch, and only two resistors and one field effect transistor are needed to construct an AND gate circuit, which can simplify the circuit and reduce costs. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] The accompanying drawings are used to provide further understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.
[0021] Figure 1 It is a circuit diagram of an AND gate integrated circuit chip of model U1 F12;
[0022] Figure 2 is a circuit diagram of a simple AND gate circuit provided in an embodiment of the present application;
[0023] Figure 3 is a circuit diagram of an open-drain output circuit;
[0024] Figure 4 is another circuit diagram of the simple AND gate circuit provided by an embodiment of the present application. DETAILED DESCRIPTION
[0025] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.
[0026] It should be noted that, although the functional modules are divided in the device schematic diagram and the logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart. The terms "first", "second", etc. in the specification, claims or the above drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.
[0027] The AND gate circuit is a basic logic gate circuit that performs the "AND" operation. The AND gate circuit can have multiple input terminals and one output terminal. When all inputs are high level (logic 1) at the same time, the output is high level, otherwise the output is low level (logic 0). The current AND gate circuit is mainly constructed by dedicated integrated circuit chips, which will increase the overall cost of the product. For example, refer to Figure 1 , using the AND gate integrated circuit chip model U1 F12, pin 1 and pin 2 are input A and input B respectively, pin 5 is power supply VCC, pin 3 is power supply ground, and pin 4 is output Y. When input A and input B are both high level, output Y is high level, otherwise output Y is low level, that is, as long as any input of input A and B is low level, output Y is low level.
[0028] In order to solve the above problems, an embodiment of the present application proposes a simple AND gate circuit.
[0029] The embodiments of the present application are further described below in conjunction with the accompanying drawings.
[0030] Reference Figure 2 In an embodiment of the present application, the simple AND gate circuit includes: at least one first input branch, a second input branch and an output branch.
[0031] Among them, the first input branch is provided with a first resistor; the second input branch is provided with a second resistor, and the third end of the second input branch is connected to the open-drain output circuit 100; the second end of the first input branch and the fourth end of the second input branch are connected to the fifth end of the output branch; the resistance value of the first resistor is greater than the resistance value of the second resistor.
[0032] In this embodiment, when the first input branch inputs a high level, the second input branch inputs a high level, the first resistor serves as a pull-up resistor of the open-drain output circuit 100, the fourth end of the second input branch outputs a high level, and the output branch outputs a high level. When the first input branch inputs a low level, the second input branch inputs a high level, the first resistor serves as a pull-down resistor of the open-drain output circuit 100, the fourth end of the second input branch outputs a low level, and the output branch outputs a low level. When the first input branch inputs a high level, the second input branch inputs a low level, the fourth end of the second input branch outputs a low level, and the output branch outputs a low level. When the first input branch inputs a low level, the second input branch inputs a low level, the fourth end of the second input branch outputs a low level, and the output branch outputs a low level.
[0033] Reference Figure 4 The following is an explanation using a simple AND gate circuit including a first input branch PLT_RST_N, a second input branch WLAN_RST_N and an output branch WLAN_PERST_N.
[0034] The first end of the first input branch is a level input end, the second end of the first input branch is connected to the fifth end of the output branch, a first resistor R1 is arranged between the first end and the second end of the first input branch, the third end of the second input branch is a level input end, the fourth end of the second input branch is connected to the fifth end of the output branch, a second resistor R2 is arranged between the third end and the fourth end of the second input branch, and the sixth end of the output branch is an AND gate output end.
[0035] For the first resistor R1 and the second resistor R2, for example, the resistance value of the first resistor R1 is 110k ohms, and the resistance value of the second resistor R2 is 0 ohms. Of course, in other embodiments, the resistance values of the first resistor R1 and the second resistor R2 can be set according to actual needs.
[0036] Reference Figure 3 Specifically, the open-drain output circuit 100 includes a field effect transistor Q1, a source of the field effect transistor Q1 is grounded, and a drain of the field effect transistor Q1 is connected to the third end of the second input branch.
[0037] The field effect transistor Q1 includes at least one of a junction field effect transistor and an insulated gate field effect transistor. Specifically, in this embodiment, the field effect transistor Q1 is a junction field effect transistor.
[0038] The principle of the open-drain output circuit 100 is as follows: when the input to the open-drain output circuit 100 is high level, the field effect transistor Q1 is turned on, the output is connected to the power ground GND, and the output is low level; when the input to the open-drain output circuit 100 is low level, the field effect transistor Q1 is turned off, and the output of the open-drain output circuit 100 is in a floating state (high impedance state). At this time, the output is neither high level nor low level. Only by adding a pull-up resistor or a pull-down resistor to the output can the output maintain a certain state. Therefore, the characteristics of the open-drain output circuit 100 are: it can output a low level, but if it is to output a high level, a pull-up resistor needs to be added to the output end, and the output level is determined by VDD.
[0039] The open-drain output circuit 100 including a field effect transistor is applied to a simple AND gate circuit.
[0040] In this embodiment, the first end of the first input branch is a conventional input end, and a conventional input signal is input, and the second end of the first input branch can output a high level or a low level. The third end of the second input branch is connected to the open-drain output circuit 100; because the open-drain output circuit 100 is in a floating state when the input is low, the field effect transistor is turned off, and the output is in a floating state, the open-drain output circuit 100 cannot output a high level alone.
[0041] When a high level is input to the first end of the first input branch and a high level is input to the third end of the second input branch, the output of the output branch is a high level; the first resistor R1 is equivalent to a pull-up resistor of the open-drain output circuit 100, and the level of the output of the second input branch is determined by the input level of the first input branch. When a high level is input to the first end of the first input branch, and then a high level is output to the fourth end of the second input branch, the output of the output branch is a high level.
[0042] When a low level is input to the first end of the first input branch and a high level is input to the third end of the second input branch, the output of the output branch is a low level; the first resistor R1 is equivalent to a pull-down resistor of the open-drain output circuit 100, and the fourth end of the second input branch is pulled down to GND by the first resistor R1, the fourth end of the second input branch outputs a low level, and the output of the output branch is a low level.
[0043] When a high level is input to the first end of the first input branch and a low level is input to the third end of the second input branch, since the resistance value of the first resistor R1 is 110k ohms and the resistance value of the second resistor R2 is 0 ohms, the fourth end of the second input branch outputs a low level and the output branch outputs a low level.
[0044] When a low level is input to the first end of the first input branch, a low level is input to the third end of the second input branch; the first resistor R1 is equivalent to a pull-down resistor of the open-drain output circuit 100, the fourth end of the second input branch is pulled down to GND by the first resistor R1, the fourth end of the second input branch outputs a low level, and the output branch outputs a low level.
[0045] By utilizing the characteristics of the open-drain output circuit, only two resistors and one field-effect transistor are needed to construct an AND gate circuit, which can simplify the circuit and reduce costs.
[0046] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the embodiments. Technical personnel familiar with the field can make various equivalent modifications or substitutions without violating the spirit of the present application. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present application.
Claims
1. A simple AND gate circuit, characterized in that: include: at least one first input branch, wherein the first input branch is provided with a first resistor; a second input branch, wherein the second input branch is provided with a second resistor, and a third end of the second input branch is connected to an open-drain output circuit; an output branch, wherein the second end of the first input branch and the fourth end of the second input branch are connected to the fifth end of the output branch; The resistance value of the first resistor is greater than the resistance value of the second resistor.
2. A simple AND gate circuit according to claim 1, characterized in that: The open-drain output circuit includes a field effect transistor, a source of the field effect transistor is grounded, and a drain of the field effect transistor is connected to the third end of the second input branch.
3. A simple AND gate circuit according to claim 2, characterized in that: The field effect transistor includes at least one of a junction field effect transistor and an insulated gate field effect transistor.
4. A simple AND gate circuit according to claim 1, characterized in that: The resistance value of the first resistor is 110k ohms, and the resistance value of the second resistor is 0 ohms.
5. A simple AND gate circuit according to claim 1, characterized in that: The first end of the first input branch is a level input end, and the third end of the second input branch is a level input end.
6. A simple AND gate circuit according to claim 1, characterized in that: The sixth end of the output branch is the AND gate output end.
7. A simple AND gate circuit according to claim 1, characterized in that: When the first input branch inputs a high level, the second input branch inputs a high level, the first resistor serves as a pull-up resistor of the open-drain output circuit, the fourth end of the second input branch outputs a high level, and the output branch outputs a high level.
8. The simple AND gate circuit according to claim 1, characterized in that: When the first input branch inputs a low level and the second input branch inputs a high level, the first resistor serves as a pull-down resistor of the open-drain output circuit, the fourth end of the second input branch outputs a low level, and the output branch outputs a low level.
9. The simple AND gate circuit according to claim 1, characterized in that: When the first input branch inputs a high level, the second input branch inputs a low level, the fourth end of the second input branch outputs a low level, and the output branch outputs a low level.
10. The simple AND gate circuit according to claim 1, characterized in that: When the first input branch inputs a low level, the second input branch inputs a low level, the fourth end of the second input branch outputs a low level, and the output branch outputs a low level.