Wafer level package and system for producing wafer level package

Abstract

The utility model relates to a wafer level package and a system for producing a wafer level package. There is provided a wafer level package comprising: a silicon wafer wherein the silicon wafer defines a plane along a main horizontal surface; a contact pad located on the main horizontal surface of the silicon wafer; the redistribution layer is positioned on the silicon wafer; an aperture through the redistribution layer, where the aperture defines an axis along which the aperture extends, where the axis is at an angle of between about 10 degrees and 80 degrees with respect to the plane; and a contact extending from the contact pad through a hole through the redistribution layer to a position on the redistribution layer opposite the silicon wafer.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority to U.S. Provisional Patent Application Serial No. 63 / 509,312, filed on June 21, 2023, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Example embodiments of the present disclosure generally relate to the repositioning of input / output (I / O) contact pads in wafer - level packaging, and more particularly, to using a multi - axis laser drill to drill non - vertical holes through a redistribution layer in order to reposition I / O contact pads in wafer - level packaging. Background Art

[0004] As new technologies that require semiconductors develop, the demand for semiconductors is constantly increasing. In addition, with the development of electronic devices, smaller and thinner form factors have become increasingly desirable and achievable. The semiconductor packages used in electronic devices continue to shrink in size and are placed closer together. The size of some parameters of these semiconductor packages and other components of the electronic devices is determined by features other than the underlying semiconductor chip.

[0005] As demand increases, the production efforts of semiconductor chips and packages keep up. Manufacturing efficiency is extremely important for increasing production volume by reducing the time required to produce semiconductor chip packages. In addition, manufacturing quality is crucial for ensuring that the produced semiconductor chip packages meet the necessary standards of the products to avoid waste and further improve manufacturing efficiency.

[0006] New systems, devices, and methods for semiconductor manufacturing are needed. The inventors have identified numerous areas for improvement in the prior art and processes, which are the subject of the embodiments described herein. Through applied effort, ingenuity, and innovation, many of these deficiencies, challenges, and problems have been solved by developing the technical solutions included in the embodiments of the present disclosure, some examples of which are detailed herein. Summary of the Utility Model

[0007] One aspect of the present application discloses a wafer-level package, characterized in that the wafer-level package includes: a silicon wafer, wherein the silicon wafer defines a plane along a main horizontal surface; contact pads located on the main horizontal surface of the silicon wafer; a redistribution layer located on the silicon wafer; holes passing through the redistribution layer, wherein the holes define an axis along which the holes extend, and wherein the axis forms an angle between about 10 degrees and 80 degrees with respect to the plane; and contacts extending from the contact pads through the holes in the redistribution layer to a position on the redistribution layer opposite to the silicon wafer.

[0008] According to at least one embodiment of the present application, the holes passing through the redistribution layer are formed using a multi-axis laser drill.

[0009] According to at least one embodiment of the present application, the wafer-level package further includes: a solder mask located above the redistribution layer; and solder balls located on the contacts that are in electrical communication with the contact pads.

[0010] According to at least one embodiment of the present application, the redistribution layer includes an Ajinomoto build-up film.

[0011] According to at least one embodiment of the present application, the contact pads are contact pads of the input / output (I / O) part of a semiconductor chip.

[0012] According to at least one embodiment of the present application, the diameter of the holes is about 25 micrometers.

[0013] Another aspect of the present application discloses a system for producing a wafer-level package, characterized in that the system includes: a wafer having contact pads and a redistribution layer covering the main surface of the wafer and the contact pads; and a multi-axis laser drill, wherein the multi-axis laser drill is configured to drill holes passing through the redistribution layer to at least one of the contact pads at various different angles with respect to the plane defined by the main surface of the wafer.

[0014] According to at least one embodiment of the present application, the multi-axis laser drill is configured to drill holes that form an angle between about 10 degrees and about 80 degrees with respect to the plane defined by the wafer.

[0015] According to at least one embodiment of the present application, the multi-axis laser drill is configured to drill holes with a diameter of at least 25 micrometers passing through the redistribution layer.

[0016] The various embodiments described herein relate to the repositioning of input / output (I / O) contact pads in a wafer-level package, and more particularly, to drilling non-vertical holes through a redistribution layer using a multi-axis laser drill in order to reposition the I / O contact pads in a wafer-level package. According to some embodiments of the present disclosure, an example method is provided. Embodiments provided herein include a method of manufacturing a wafer-level package, the method comprising: forming a redistribution layer on a wafer having contact pads disposed thereon, wherein the wafer defines a plane along a main horizontal surface on which the contact pads are disposed; drilling a hole through the redistribution layer along an axis that reaches the contact pad using a multi-axis laser drill, wherein the axis of the hole through the redistribution layer is at an angle that is neither parallel nor orthogonal to the plane; and forming a contact that extends from the contact pad through the hole through the redistribution layer to a location on the redistribution layer.

[0017] According to some embodiments, the axis of the hole through the redistribution layer is at an angle between 10 degrees and 80 degrees relative to the plane. The method of some embodiments further comprises: forming a seed layer after drilling; and applying a photoresist dry film laminate above the seed layer, wherein the contact that extends from the contact pad is formed at a location where the photoresist dry film laminate is not cured. The method of some embodiments further comprises: applying a solder mask above the redistribution layer; and attaching solder balls at the contact that is in electrical communication with the contact pad. In some embodiments, the redistribution layer comprises an Ajinomoto build-up film. The contact pads of some embodiments are contact pads of an input / output (I / O) portion of a semiconductor chip. According to some embodiments, the method may include determining the angle of the hole through the redistribution layer relative to the plane is based on the thickness of the redistribution layer and the desired position of the contact relative to the contact pad. The holes of some embodiments are about 25 microns.

[0018] According to some embodiments, the contact pad is a first contact pad, the hole is a first hole, the axis is a first axis, the contact is a first contact, and the angle is a first angle. The method further includes: drilling, with the multi-axis laser drill, a second hole that reaches a second contact pad of the wafer along a second axis passing through the redistribution layer, wherein the second axis of the second hole passing through the redistribution layer forms a second angle different from the first angle with respect to the plane; and forming a second contact that extends from the second contact pad through the hole in the redistribution layer to a position on the redistribution layer opposite the wafer. According to some embodiments, drilling the hole that reaches the contact pad along the axis passing through the redistribution layer further includes, after drilling, removing one or more of frictional molten resin or drilling debris from the hole. According to some embodiments, removing one or more of frictional molten resin or drilling debris from the hole after drilling includes treating the hole with at least one of permanganate or plasma treatment.

[0019] Embodiments provided herein include a wafer-level package that includes: a silicon wafer, wherein the silicon wafer defines a plane along a main horizontal surface; a contact pad located on the main horizontal surface of the silicon wafer; a redistribution layer located on the silicon wafer; a hole passing through the redistribution layer, wherein the hole defines an axis along which the hole extends, and wherein the axis forms an angle between about 10 degrees and 80 degrees with respect to the plane; and a contact that extends from the contact pad through the hole in the redistribution layer to a position on the redistribution layer opposite the silicon wafer.

[0020] According to some embodiments, the hole passing through the redistribution layer is formed using a multi-axis laser drill. The wafer-level package of some embodiments further includes: a solder mask located above the redistribution layer; and solder balls located on the contact that is in electrical communication with the contact pad. The contact pad of some embodiments is a contact pad of an input / output (I / O) portion of a semiconductor chip. The diameter of the hole of some embodiments is about 25 micrometers.

[0021] The embodiments provided herein include a system for producing a wafer-level package, the system including: a wafer having contact pads and a redistribution layer covering a main surface of the wafer and the contact pads; and a multi-axis laser drill, wherein the multi-axis laser drill is configured to drill holes through the redistribution layer to at least one of the contact pads at various different angles relative to a plane defined by the main surface of the wafer. The multi-axis laser drill of some embodiments is configured to drill holes at an angle between about 10 degrees and about 80 degrees with respect to the plane defined by the wafer. The multi-axis laser drill of some embodiments is configured to drill holes having a diameter of at least 25 micrometers through the redistribution layer.

[0022] The above Summary of the Invention is provided merely for the purpose of summarizing some example embodiments to provide a basic understanding of some aspects of the present disclosure. Accordingly, it will be understood that the above embodiments are merely examples and should not be construed as in any way narrowing the scope or spirit of the subject matter of the present disclosure. It will also be understood that, in addition to the embodiments summarized herein, the scope of the present disclosure also encompasses many possible embodiments, some of which will be further described below. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Certain example embodiments of the present disclosure have been generally described above, and reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and in which:

[0024] Figure 1 A top view of a semiconductor package according to an example embodiment of the present disclosure is illustrated;

[0025] Figure 2A A cross-section of a wafer and contact pads according to an example embodiment of the present disclosure is illustrated;

[0026] Figure 2B Illustrated is a Figure 2A having a redistribution layer according to an example embodiment of the present disclosure;

[0027] Figure 2C Illustrated is a Figure 2B redistribution layer formed according to an example embodiment of the present disclosure;

[0028] Figure 2D Illustrated is a Figure 2C wafer-level package having an electroless copper seed layer according to an example embodiment of the present disclosure;

[0029] Figure 3A Illustrated is a Figure 2D wafer-level package having a photoresist dry film laminate applied thereto according to an example embodiment of the present disclosure;

[0030] Figure 3B Illustrates a wafer - level package in which a photoresist dry - film laminate is imaged and developed according to an exemplary embodiment of the present disclosure Figure 3A ;

[0031] Figure 3C Illustrates a wafer - level package on which copper traces are deposited according to an exemplary embodiment of the present disclosure Figure 3B ;

[0032] Figure 3D Illustrates a wafer - level package in which the photoresist dry - film laminate is removed and the seed layer is etched according to an exemplary embodiment of the present disclosure Figure 3C ;

[0033] Figure 4A Illustrates a wafer - level package having a second redistribution layer and second copper traces according to an exemplary embodiment of the present disclosure Figure 3D ;

[0034] Figure 4B Illustrates a wafer - level package on which a solder mask is applied according to an exemplary embodiment of the present disclosure Figure 4A ;

[0035] Figure 4C Illustrates a wafer - level package on which solder balls are applied according to an exemplary embodiment of the present disclosure Figure 4B ;

[0036] Figure 5A Illustrates a cross - section of a wafer and contact pads according to an exemplary embodiment of the present disclosure

[0037] Figure 5B Illustrates a cross - section of a wafer - level package having a redistribution layer according to an exemplary embodiment of the present disclosure Figure 5A ;

[0038] Figure 5C Illustrates holes drilled by a multi - axis laser drill in a redistribution layer according to an exemplary embodiment of the present disclosure Figure 5B ;

[0039] Figure 6A Illustrates a wafer - level package having an electroless copper seed layer according to an exemplary embodiment of the present disclosure Figure 5C ;

[0040] Figure 6B Illustrates a wafer - level package on which a photoresist dry - film laminate is applied and cured according to an exemplary embodiment of the present disclosure Figure 6A ;

[0041] Figure 6C Illustrates a wafer - level package on which copper traces are deposited according to an exemplary embodiment of the present disclosure Figure 6BWafer-level packaging;

[0042] Figure 7A illustrates a wafer-level packaging in which a photoresist dry film laminate is removed and a seed layer is etched according to an exemplary embodiment of the present disclosure; Figure 6C Wafer-level packaging;

[0043] Figure 7B illustrates a wafer-level packaging to which a solder mask is applied according to an exemplary embodiment of the present disclosure; Figure 7A Wafer-level packaging;

[0044] Figure 7C illustrates a wafer-level packaging to which solder balls are applied according to an exemplary embodiment of the present disclosure; Figure 7A Wafer-level packaging;

[0045] Figure 8A illustrates a wafer-level packaging having a relatively thin redistribution layer according to an exemplary embodiment of the present disclosure;

[0046] Figure 8B illustrates a wafer-level packaging having a relatively thick redistribution layer according to an exemplary embodiment of the present disclosure; and

[0047] Figure 9 is a flowchart of a method for manufacturing a wafer-level packaging by using a multi-axis laser drill to reposition contact pads on a redistribution layer according to an exemplary embodiment of the present disclosure. Detailed Description

[0048] Now, some embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings, in which some, but not all, embodiments of the present disclosure are shown. In fact, the various embodiments of the present disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements. Like reference numerals always refer to like elements.

[0049] As used herein, the term "comprising" means including but not limited to and should be construed in its ordinary sense as used in the patent context. The use of broader terms such as including, containing, and having should be understood to support narrower terms such as consisting of, consisting essentially of, and essentially comprising.

[0050] Phrases such as "in various embodiments", "in one embodiment", "according to one embodiment", "in some embodiments", etc. generally mean that the particular feature, structure, or characteristic following the phrase may be included in at least one embodiment of the present disclosure and may be included in more than one embodiment of the present disclosure (importantly, such phrases do not necessarily refer to the same embodiment).

[0051] As used herein, the terms "example" or "exemplary" are used to mean "serving as an example, instance, or illustration". Any implementation described herein as "exemplary" is not necessarily to be construed as preferred or superior to other implementations.

[0052] If the specification states that a component or feature "may", "can", "would", "should", "will", "preferably", "possibly", "typically", "optionally", "for example", "often", or "likely" (or other such language) is included or has a characteristic, it is not required that the particular component or feature be included or have the characteristic. In some embodiments, such a component or feature may optionally be included, or it may be excluded.

[0053] As used herein, the use of the term "circuit" for a component of a system or device should be understood to include specific hardware configured to perform the functions associated with a particular circuit as described herein. The term "circuit" should be broadly understood to include hardware and, in some embodiments, includes software for configuring the hardware. For example, in some embodiments, "circuit" may include processing circuitry, communication circuitry, input / output circuitry, etc. In some embodiments, other elements may provide or supplement the functions of a particular circuit.

[0054] Various embodiments of the present disclosure relate to improved systems, devices, and methods for semiconductor package manufacturing, and more particularly, to using a multi-axis laser drill to drill non-vertical holes through redistribution layers to reposition input / output (I / O) contact pads in wafer-level packages. Wafer-level packaging of semiconductor chips is crucial for the production of integrated circuits for various electronic devices. With the advancement of technology, the use of integrated circuits in electronic devices has increased exponentially. To meet this demand, improved manufacturing processes are needed to efficiently and effectively produce wafer-level packages for various applications. The embodiments described herein provide a mechanism by which operations in conventional wafer-level package manufacturing can be omitted, thereby improving throughput efficiency in manufacturing and reducing the likelihood of defects in wafer-level packages.

[0055] Electronic devices such as mobile phones are highly portable and are carried frequently throughout a user's day. As such, the size of a mobile phone or other portable electronic device is critical to the portability and use of such a device. These electronic devices have a very high level of functionality and need to be designed to be robust to withstand frequent use as well as often unintentional damage and wear. Thus, the structure of these electronic devices requires a degree of rigidity while maintaining a small form factor. The substantially rigid chassis of the electronic device that houses its hardware components (e.g., sensors, communication modules, speakers, cameras, screens, etc.) becomes an important component with respect to the overall size, which limits the available space for the hardware components. The sizes of competing hardware components need to be designed to fit within the small form factor, or else components will be omitted, which has an adverse effect on the functionality and desirability of the electronic device. As such, a small form factor for wafer-level packaging of one or more sensors is highly desirable, and smaller components enable the electronic device form factor to be made smaller and / or enable more components to be included, increasing the functionality of the electronic device.

[0056] Wafer-level packaging provides an efficient manufacturing process through which integrated circuits are fabricated, and components of the wafer-level package are attached to the integrated circuit before the integrated circuit is singulated into individual wafer-level packages for use in a device. By not requiring processes for handling individual integrated circuits, components such as the top and bottom layers of the package as well as solder bumps are attached to the integrated circuit. This process enables efficient and consistent package assembly of the integrated circuit without the need to handle and align individual integrated circuits in order to assemble components thereon.

[0057] Wafer-level packaging enables the fabrication of integrated circuits in a streamlined and efficient process while producing packages with a highly compact overall size. The integrated circuits assembled in wafer-level packages can be used in a variety of end products. Different end products may have different requirements for pin or solder ball connections, including different layouts and pitches. Thus, while a single integrated circuit with a fixed contact pattern can be used to produce various wafer-level packages, the wafer-level packages in which the integrated circuits are formed may need to have the positions of the pins or solder ball connections of the wafer-level packages adjusted.

[0058] Conventionally, wafer-level packaging uses multiple redistribution layers (RDLs) to route connections from an integrated circuit to the I / O region of the wafer-level package. This process involves producing multiple layers of an anisotropic build film (ABF), where each layer moves the connections of the integrated circuit a certain degree from their original positions. The process includes laminating ABF on top of the integrated circuit, drilling the ABF to expose integrated circuit contacts, depositing a copper seed layer, applying a patterned dry film photoresist laminate to receive copper electroplating, and depositing copper in the masked regions of the photoresist film layer. The photoresist film layer is then removed, and the process is repeated for the desired number of RDLs to move the integrated contacts to the I / O region of the wafer-level package. This process can be cumbersome due to the multiple layers and multiple steps involved. The embodiments described herein improve the above process by using a multi-axis laser drill as further described herein.

[0059] Figure 1 A top view of an example embodiment of a semiconductor package in accordance with one or more embodiments of the present disclosure is illustrated. The semiconductor package 10 may include a dielectric layer 15, a ground plane 20, a plurality of signal pads 30, and a plurality of solder balls, such as ground plane solder balls 22 and signal pad solder balls 32. The dielectric layer may be a polyimide (PI) and / or polybenzoxazole (PBO) material. Figure 1 Also depicted is a cross-section line A-A, which represents the cross-section line for subsequent figures taken according to various embodiments.

[0060] It will be readily understood that although only a few of the signal pads 30 and signal pad solder balls 32 are labeled, the semiconductor package 10 may include a plurality of signal pads as well as a plurality of signal pad solder balls, as Figure 1 shown. Each of the signal pads 30 may be separated from the ground plane 20 by one or more layers and / or portions of a dielectric material (e.g., dielectric layer 15). When the semiconductor package 10 is used in an electronic device, the plurality of solder balls (e.g., ground plane solder balls 22 and signal pad solder balls 32) may connect the semiconductor package to other circuits of the electronic device. Although the semiconductor package 10 is illustrated as rectangular, it will be readily understood that the semiconductor package 10 may take other shapes and / or sizes, particularly as required by the electronic device. Figure 1 The semiconductor package 10 is an example of a view of various semiconductor configurations as described herein, such that additional figures will be described using the view taken along cross-section line A-A, and the cross-sectional views may depict different embodiments of the semiconductor package 10.

[0061] Figures 2A to 3D Illustrated is a process of using multiple redistribution layers to relocate contact pads of a wafer-level package. As Figure 2AAs shown, known good die (KGD) of the wafer 110 is shown adjacent to the dry film EMC 115 (epoxy molding compound) of the wafer-level package 100. Contact pads 125 are located on top of the wafer 110, and the surface of the wafer is shown coated with a passivation layer 120. In Figure 2B the wafer 110 and the EMC 115 are laminated with an Ajinomoto build-up film (ABF) to form a redistribution layer 130. As Figure 2C shown, the redistribution layer 130 is processed to expose the contact pads 125. The processing can include drilling, etching, or other known processes for exposing the contact pads 125 through the redistribution layer 130. In addition to the exposed contact pads 125, the redistribution layer 130 forms a barrier over the wafer 110 and the EMC 115. As Figure 2D shown, the redistribution layer 130 is coated with an electroless copper seed layer 140. This process prepares the redistribution layer 130 for electroplating to provide an electroplated layer with improved adhesion to the surface of the wafer-level package 100.

[0062] Figure 3A The deposition of a photoresist dry film laminate layer 145 is illustrated. The photoresist layer is a photosensitive material that can be used to form a patterned coating on a surface. The substrate is coated with the photoresist dry film laminate layer 145, and the photoresist dry film laminate layer 145 is processed to expose a portion of the underlying surface. According to an example embodiment, a pattern mask is applied. The patterned mask provides an opaque pattern of the photoresist dry film laminate layer 145 to be held in place, while the transparent or translucent portions of the mask allow light to pass through the photoresist dry film laminate layer 145. The portion of the layer exposed to light is degraded such that, after removal of the mask, the exposed portion of the photoresist dry film laminate layer 145 that was exposed to light can be dissolved using a developer. According to another embodiment, the mask can be omitted and laser direct imaging can be employed instead, which can direct a laser to irradiate only the portions of the photoresist dry film laminate layer to be exposed to light. This process can be more efficient and at least as effective as the process using a mask. Figure 3B The remaining pattern of the photoresist dry film laminate layer 145 is illustrated, as well as voids 150 where the layer has been dissolved and washed away. As Figure 3C shown, copper electroplating is performed and copper traces 155 are deposited in the voids 150.

[0063] Figure 3DIllustrated is the remaining copper trace 155 after the photoresist dry film laminate 145 is peeled off and the copper seed layer 140 is etched to expose the ABF film redistribution layer 130. As shown, the process can provide a certain degree of repositioning of the contact pad 125 based on the vertical and lateral variations of the copper trace 155. The degree of vertical movement is based on the thickness of the redistribution layer 130. The degree of lateral movement of the trace is restricted based on the pattern on the surface of the redistribution layer 130. Because many wafer-level packages include multiple contact pads and thus include associated copper traces. Additionally, because the wafer-level package size is critical and the size is transitioning to smaller packages, the amount of lateral movement on any given redistribution layer is limited. Therefore, using multiple redistribution layers to reposition the contacts for the contact pads to any significant degree.

[0064] Figure 4A Illustrated is an example embodiment having a first redistribution layer 130 and a second redistribution layer 160, where the second redistribution layer is formed using the process described in Figures 2B to 3D . The process of forming the redistribution layer and the associated copper traces can continue as necessary to move the position of the solder balls for the contact pads. When adding additional redistribution layers, the buildup of materials causes a significant increase in the thickness of the wafer-level package. In embodiments where the overall package size is important, such as in mobile devices and other electronic devices that benefit from a small form factor, this thickness may be undesirable.

[0065] Figure 4B Illustrated is the process after the final redistribution layer, where a solder mask layer 170 is applied to the surface of the second redistribution layer 160. The solder mask layer 170 covers the surface of the wafer-level package, except for the areas that are to receive the solder balls. In the illustrated embodiment of Figure 4B , the solder pads 165 remain exposed so that the solder balls 175 can be deposited on the solder pads 165, as illustrated in Figure 4C .

[0066] The above-mentioned redistribution layers may introduce failure modes to the wafer-level package. For example, each redistribution layer increases the likelihood of delamination between the redistribution layer and the underlying substrate. As more redistribution layers are added, this likelihood increases accordingly. Additionally, each redistribution layer increases as described above with respect to Figures 2A to 3DThe described sequence of manufacturing operations. The added manufacturing operations introduce complexity to the manufacturing process and reduce efficiency. Each additional redistribution layer consumes manufacturing time and resources, thus reducing throughput. With technological advancements and high demand for semiconductor chips, the demand for wafer-level packaging is continuously increasing. Therefore, wafer-level packaging manufacturing efficiency is important. In addition, each redistribution layer increases the thickness of the wafer-level packaging, which may result in an undesirable overall thickness of the wafer-level packaging, especially in devices where packaging space is very valuable.

[0067] Embodiments described herein improve the prior art by providing methods, apparatuses, and systems for repositioning contacts for contact pads using fewer manufacturing operations and less redistribution. In addition, embodiments can have a thinner overall thickness while improving manufacturing efficiency and reducing the chance of defects. Embodiments described herein employ a multi-axis laser drill to drill through redistribution layers at non-vertical angles to provide repositioning of contacts for contact pads in the horizontal direction without the need for multiple redistribution layers. In addition, embodiments can reduce the number of manufacturing operations and improve overall efficiency.

[0068] The prior art processes of repositioning I / O contacts through multiple redistribution layers mentioned above are cumbersome and inefficient. Embodiments provided herein utilize advancements in laser drilling technology to reduce the number of operations required to reposition I / O contacts from an IC to a wafer-level packaging.

[0069] Rather than using multiple layers of ABF for redistribution, embodiments employ a single layer of ABF and use a 6-axis laser drill to drill through the layer at an angle to reposition I / O contacts from an IC to different positions on top of the single layer of ABF. The process is illustrated and described below.

[0070] Using the process described and illustrated below, contact repositioning can be performed with significantly fewer operations in a highly efficient and effective process. A 6-axis laser drill can drill a 25-micron hole into an IC contact pad at an angle of 18 degrees with respect to the horizontal plane. These current limitations can be improved with advancements in laser drilling technology with smaller hole diameters and shallower incident angles. The angle can vary with the multi-axis laser drill, where, given advancements in laser drill technology, the angle with respect to the horizontal plane corresponding to the wafer surface can generally be between 10 degrees and 80 degrees. The axis along which the hole is formed is generally neither vertical nor horizontal. For contacts that do not move laterally with respect to the contact pad, the hole can be vertical; however, such a hole does not require the multi-axis laser drill described herein.

[0071] The lateral movement of the contacts of the IC towards the contacts of the I / O depends on the incident angle of the laser drilling and the thickness of the ABF layer. A thicker ABF layer enables the contacts to move laterally more from their original positions on the IC. Embodiments of the present utility model achieve repositioning of the contact positions with fewer operations and greater flexibility. In addition, the RDL layer introduces the possibility of failure due to delamination between the layers, which is a problem overcome by the method described herein.

[0072] Figure 5A Illustrated is a known good die (KGD) of wafer 210 adjacent to the dry film EMC 215 of the wafer-level package 200. Contact pads 225 are located on top of wafer 210, and it is shown that the surface of the wafer is coated with a passivation layer 220. In Figure 5B , the wafer 210 and the EMC 215 are laminated with an Ajinomoto build-up film to form a redistribution layer 230. Then, a laser drill is used to drill through the redistribution layer 230. The laser drill of the exemplary embodiments described herein is a multi-axis laser drill, such as a 6-axis laser drill. The laser drill is a multi-axis laser drill so that the redistribution layer 230 can be drilled through at an angle that is offset from vertical or not aligned with the vertical axis defined orthogonal to the main surface of the wafer 210.

[0073] Figure 5C Illustrated is a hole 235 drilled through the redistribution layer 230 by the multi-axis laser drill. The hole 235 is angled 237 with respect to the horizontal plane along which the wafer extends. The angled hole 235 provides a lateral offset between the contact pad 225 and the contact that will form the solder ball. The diameter of the hole is as small as about 25 microns. Once the hole is drilled using the multi-axis laser drill, the contact pad 225 is decontaminated. The decontamination process provides a mechanism for removing, from the hole 235, such as friction-fused resin and drilling debris from the redistribution layer 230. This can be achieved, for example, using permanganate or plasma treatment. In addition, the contact pad 225 can be micro-roughened to wear or roughen its surface to improve adhesion and coating adhesion.

[0074] Figure 6A Illustrated is the application of an electroless copper seed layer 240. The seed layer covers the redistribution layer 230 and the interior of the hole 235 that reaches the contact pad 225. As Figure 6B shown, a photoresist dry film laminate layer 245 is applied. A photomask can be used to cure only a portion of the photoresist dry film laminate layer 245, but alternatively a laser direct imaging process can be used to cure a portion of the photoresist dry film laminate layer 245, and the uncured portion can be dissolved or washed away to leave voids 250, as Figure 6B shown. Then, the voids 250 can be filled with copper using the copper plating operation shown in Figure 6C where copper traces 255 have filled the voids 250 and formed contacts with the contact pads 225.

[0075] Figure 7A Illustrates the remaining copper traces 255 after the photoresist dry film laminate 245 is stripped and the copper seed layer 240 is etched to expose the ABF film redistribution layer 230. As shown, the process can provide a certain degree of repositioning of the contact pads 225 based on the angled path of the copper traces 255. The degree of vertical movement is based on the thickness of the redistribution layer 230. The degree of lateral movement of the traces is based on the angle 237 of the holes formed in the multi-axis laser drill and the thickness of the redistribution layer Figure 5C depicted in.

[0076] Figure 7B Illustrates the process after forming the copper traces 255, where a solder mask layer 270 is applied to the surface of the redistribution layer 230. The solder mask layer 270 covers the surface of the wafer-level package, except for the areas to receive the solder balls. In Figure 7B the illustrated embodiment, the solder pads 265 remain exposed so that the solder balls 275 can be deposited on the solder pads 265, as Figure 7C illustrated in.

[0077] As described above, the possible degree of lateral movement of the contact pads 225 and the solder balls 275 is based on the angle of the holes formed in the multi-axis drill and the thickness of the redistribution layer. Figure 8A and Figure 8B Illustrates the effect of the redistribution layer thickness on the ability to laterally move the solder ball connections. In Figure 8A it, the wafer 310 and the EMC 315 are shown, where the redistribution layer 330 has a thickness 339. The solder ball 375 is disposed at a distance 333 from the original contact pad 325 position. Figure 8B Illustrates the wafer 410 and the EMC 415, where the redistribution layer 430 has a thickness 439. The angle 437 is equal to the angle 337. However, because the thickness 439 of the redistribution layer 430 is significantly greater than the thickness 339 of the redistribution layer 330, the degree of lateral movement (distance 433) of the wafer-level package 400 is greater than the degree of lateral movement (distance 333) of the wafer-level package 300.

[0078] According to the embodiments described herein, a relatively thick redistribution layer can provide greater flexibility in repositioning the contact pads. Using a multi-axis laser drill can precisely control the angle of the drilled holes, thereby defining the degree of lateral movement from the contact pads based on the angle of the drilled holes. In addition, the degree of lateral movement can be in any direction on the surface plane of the redistribution layer.

[0079] Figure 9An example block diagram of a flowchart illustrating an operation of using a multi-axis laser drill to drill an off-vertical hole through a redistribution layer to reposition I / O contact pads in a wafer-level package in accordance with one or more embodiments of the present disclosure is shown. In various embodiments, one or more of the operations may be omitted or repeated. It will also be understood that other operations not described herein may occur. According to the illustrated embodiment, in 610, a redistribution layer is formed on a wafer having contact pads disposed thereon. The wafer defines a plane along a main horizontal surface on which the contact pads are disposed. In 620, a hole is drilled using a multi-axis laser drill along an axis passing through the redistribution layer to reach the contact pads. The axis of the hole passing through the redistribution layer is at an angle that is neither parallel nor orthogonal to the plane. In 630, a contact is formed that extends from the contact pads through the hole in the redistribution layer to a position on the redistribution layer opposite the wafer.

[0080] The operations and / or functions of the present disclosure have been described herein, such as in a flowchart or in a diagram associated with the flowchart. Although the operations and / or functions are illustrated in a particular order, this should not be construed as requiring that such operations and / or functions be performed in the particular order shown or in a sequential order, or that all of the illustrated operations be performed, to achieve the desired result. In some cases, alternative ordering of the operations and / or functions may be advantageous. In some cases, the acts recited in the claims may be performed in a different order and still achieve the desired result. Accordingly, while particular embodiments of the subject matter have been described, other embodiments are within the scope of the appended claims.

[0081] Although this specification contains many specific implementation details and embodiments, these should not be construed as limiting the scope of any disclosure or the scope of the claimed subject matter, but rather as descriptions of features specific to particular embodiments of a particular disclosure. Certain features described herein in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented separately or in any suitable sub-combination in multiple embodiments. Additionally, although features may be described above as acting in certain combinations and even initially claimed as such, in some cases, one or more of the features in the claimed combination may be deleted from the combination, and the claimed combination may relate to a sub-combination or a variation of a sub-combination.

[0082] Although this specific implementation has set forth some embodiments of the present invention, the appended claims cover other embodiments of the present invention that are different from the described embodiments according to various modifications and improvements.

[0083] In the following claims, unless the term "means for" or "step for" is used in a given claim, it is not intended to be construed under paragraph 6 of 35 U.S.C. § 112 of the United States Code.

Claims

1. A wafer-level package, characterized in that: The wafer level packaging comprises: a silicon wafer, wherein the silicon wafer defines a plane along a major horizontal surface; a contact pad located on the major horizontal surface of the silicon wafer; a redistribution layer, the redistribution layer being located on the silicon wafer; a hole through the redistribution layer, wherein the hole defines an axis along which the hole extends, wherein the axis is at an angle between about 10 degrees and 80 degrees relative to the plane; and A contact extends from the contact pad through a hole through the redistribution layer to a location on the redistribution layer opposite the silicon wafer.

2. The wafer level package according to claim 1, characterized in that: The holes are formed through the redistribution layer using multi-axis laser drilling.

3. The wafer level package according to claim 1, characterized in that: The wafer level package further comprises: a solder mask over the redistribution layer; and A solder ball is located on the contact in electrical communication with the contact pad.

4. The wafer level package according to claim 1, characterized in that: The redistribution layer includes an Ajinomoto stacked film.

5. The wafer level package according to claim 1, characterized in that: The contact pads are contact pads of an input / output (I / O) portion of a semiconductor chip.

6. The wafer level package according to claim 1, characterized in that: The diameter of the pores is about 25 microns.

7. A system for producing wafer-level packaging, characterized in that: The system comprises: a wafer having contact pads and a redistribution layer covering a major surface of the wafer and the contact pads; and A multi-axis laser drill, wherein the multi-axis laser drill is configured to drill holes through the redistribution layer to at least one of the contact pads at various angles relative to a plane defined by the major surface of the wafer.

8. The system according to claim 7, characterized in that The multi-axis laser drill is configured to drill a hole between about 10 degrees and about 80 degrees from the plane defined by the wafer.

9. The system according to claim 7, characterized in that The multi-axis laser drill is configured to drill holes having a diameter of at least 25 microns through the redistribution layer.

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