Integrated circuit memory device

Abstract

The utility model provides an integrated circuit comprising a first charge trapping device, a second charge trapping device and a control circuit. The first charge trapping device includes a first charge trapping structure disposed over the substrate between the first gate structure and the first channel region. A second charge trapping device is coupled in series with the first charge trapping device and includes a second charge trapping structure disposed over the substrate between the second gate structure and the second channel region. A control circuit is coupled to the first and second gate structures, and is configured to store a first input of an implicit (IMPLY) operation as a stored value of the first charge trapping device, a second input of the IMPLY operation as a stored value of the second charge trapping device, and a third input of the IMPLY operation as a stored value of the second charge trapping device. And updating the stored value of the second charge trapping device according to the stored value of the first charge trapping device to perform an IMPLY operation.

Description

Technical Field

[0001] The utility model relates to an integrated circuit memory device. Background Art

[0002] Many modern electronic devices include electronic memory devices. Electronic memory devices may be volatile memory devices or non-volatile memory devices. Non-volatile memory devices are able to retain their stored data when power is removed, while volatile memory devices lose their stored data when power is removed. Some efforts have been made to incorporate standard logic functions into electronic memory devices (e.g., non-volatile memory devices) by means of in-memory computing to perform some preliminary data processing on stored data without explicitly reading the stored data from the memory device to a central processing unit (CPU) in advance. Utility Model Content

[0003] An embodiment of the utility model provides an integrated circuit memory device, which includes a first charge capture device, a second charge capture device and a control circuit. The first charge capture device includes a first charge capture structure arranged on a substrate between a first gate structure and a first channel region. The second charge capture device is coupled in series with the first charge capture device and includes a second charge capture structure arranged on a substrate between the second gate structure and the second channel region. The control circuit is coupled to the first gate structure of the first charge capture device and the second gate structure of the second charge capture device. The control circuit is configured to store a first input of an IMPLY operation as a storage value of the first charge capture device, store a second input of the IMPLY operation as a storage value of the second charge capture device, and update the storage value of the second charge capture device to perform an IMPLY operation based on the storage value of the first charge capture device.

[0004] An embodiment of the utility model provides an integrated circuit memory device, which includes a plurality of charge capture devices coupled in series and a control circuit coupled to the gate connection of each of the plurality of charge capture devices. The control circuit is configured to store each of the one or more inputs of a logic function in a corresponding one of the plurality of charge capture devices, and to perform one or more IMPLY operations using the plurality of charge capture devices to perform the logic function. Each of the one or more IMPLY operations is performed using the stored value of each of the associated pairs of the plurality of charge capture devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The aspects of the present disclosure will be best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0006] Figure 1A Schematic diagrams of some embodiments of a portion of an integrated circuit (IC) memory device including two charge trapping devices to implement an IMPLY function according to the present invention are shown.

[0007] Figure 1B The invention according to the present invention is shown Figure 1A Voltage diagrams of the operation of a charge capture device in some embodiments of a portion of an IC memory device.

[0008] FIG. 2A to FIG. 2D Shows the use of Figure 1A A more detailed example of a series of operations of an IC memory device to implement the IMPLY function.

[0009] Figure 2E Shows Figure 1A Cross-sectional views of some embodiments of a portion of an IC memory device resulting from front end of line (FEOL) processing.

[0010] Figure 2F Shows Figure 1A Cross-sectional views of some embodiments of a portion of an IC memory device resulting from back end of line (BEOL) processing.

[0011] Figures 3A to 3G A series of operations using an IC memory device including three charge trapping devices to implement a NAND function using a series of IMPLY functions is shown.

[0012] Figure 3H Shows Figure 3A Cross-sectional views of some embodiments of a portion of an IC memory device resulting from FEOL processing.

[0013] Fig. 3I Shows Figure 3A Cross-sectional views of some embodiments of a portion of an IC memory device resulting from BEOL processing.

[0014] Figure 4 A method is shown in the form of a flow chart, which shows FIG. 2A to FIG. 2F Some embodiments of the operation of an IC memory device.

[0015] Figure 5 A method is shown in the form of a flow chart, which shows FIG. 3A to FIG. 3I Some embodiments of the operation of an IC memory device.

[0016] Figure 6A schematic diagram showing some embodiments of a portion of an IC memory device according to the present invention including five charge trapping devices to implement a logic function using one or more IMPLY functions.

[0017] 7A to 7F Some embodiments of a series of additive manufacturing steps are shown as Figure 6 A series of cross-sectional views of an IC memory device resulting from FEOL processing.

[0018] Figure 8 A method is shown in the form of a flow chart, which shows 7A to 7E Some embodiments of the present invention are related.

[0019] 9A to 9F Some embodiments of a series of additive manufacturing steps are illustrated as Figure 6 A series of cross-sectional views of an IC memory device resulting from BEOL processing.

[0020] Fig.10 A method is shown in the form of a flow chart, which shows 9A to 9F Some embodiments of the present invention are related. DETAILED DESCRIPTION

[0021] The present disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature on or above a second feature in the following description may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature. The first and second features, so that the first and second features may not be in direct contact. In addition, the present disclosure may repeat figure numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself dictate the relationship between the various embodiments and / or configurations discussed.

[0022] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one component or feature relative to another component(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0023] In a conventional computing configuration, memory devices and logic devices (e.g., within a computer processing unit (CPU)) are arranged within different parts of an integrated circuit. During operation, data is transmitted between the memory device and the logic device via relatively long bus lines. The resistance of the relatively long bus lines can cause power loss and reduce CPU performance. It has been recognized that an in-memory computing configuration can alleviate the power loss associated with relatively long bus lines. The in-memory computing configuration includes a memory device cell coupled to a logic gate (e.g., in a field-programmable gate array (FPGA)) to provide a certain degree of logic function without the need for CPU involvement to read data from the memory device device before performing the required logic calculation. However, in this case, a large amount of additional logic circuitry can be tightly integrated with the memory device cell to facilitate in-memory computing, thereby increasing the footprint of the in-memory computing configuration.

[0024] In some embodiments of the present disclosure, a memory device cell implemented using a charge capture device may also itself at least partially function as a logic circuit by performing one or more implicit (IMPLY) operations within the cell. Thus, the integrated circuit footprint typically consumed by the charge capture device and associated logic circuits of an IC memory device that implements in-memory computing may be reduced (e.g., by maintaining the memory device cell in an associated memory device portion of the IC memory device and providing support for logic functions in a separate control circuit of the device). Moreover, in some embodiments, the IC memory device may be manufactured during a front-end-of-line (FEOL) process or a back-end-of-line (BEOL) process, thereby providing a degree of flexibility in layout planning and other aspects of design.

[0025] As used herein, the IMPLY operation (sometimes implemented as a logic gate in digital logic) is a two-input binary operation that produces an "if A, then B" output for a first input A and a second input B. Thus, as used herein, if A is 0, the output is 1, regardless of the value of B. Conversely, if A is 1, the output is equal to B.

[0026] like Figure 1AA schematic diagram of some embodiments of a portion of an IC memory device 100 according to the present disclosure is shown, the IC memory device 100 including two charge capture devices 102 and 104 configured to implement an IMPLY function. The charge capture devices 102 and 104 are coupled in series (e.g., the drain of the first charge capture device 102 is coupled to the source of the second charge capture device 104). In some embodiments, each of the charge capture devices 102 and 104 can be a ferroelectric field-effect transistor (FeFET). However, in other embodiments, the charge capture devices 102 and 104 can be built using other charge capture transistor technologies, such as flash memory (e.g., NAND flash memory) technology.

[0027] In some embodiments, the gate of each of the charge capture devices 102 and 104 may be coupled to the control circuit 105. The control circuit 105 is configured to drive the charge capture devices 102 and 104 to implement the IMPLY function. The ability of the control circuit 105 to implement the IMPLY function is based on the drain current generated by the first charge capture device 102 in response to the voltage applied to the gate of the first charge capture device 102.

[0028] For example, Figure 1B The present disclosure is shown Figure 1A 1 and 104 in some embodiments of a portion of an IC memory device. In some embodiments, a charge capture device (e.g., first charge capture device 102 or second charge capture device 104) can be programmed by driving the gate of the charge capture device to one of two different levels: a programming voltage or state V PP , which may cause the charge trapping device to store a programmed state (eg, a low or "0" state) 112; and an erase voltage or state V EE , which may cause the charge trapping device to store an erased state (eg, a high or “1” state) 114 .

[0029] When the charge capture device stores a specific state, the charge capture device can be controlled to selectively output the state stored by the charge capture device. More specifically, Figure 1B As shown, when the gate voltage V G When the drain current I of the charge trapping device is kept low (e.g., zero volts), regardless of the storage state of the charge trapping device, D On the contrary, when the gate voltage V G Keep it high (for example, V R2 Volts), the drain current I Dcan be in a high (ON) level or state regardless of the storage state of the charge trapping device. However, when the gate voltage V G Keep it at mid-level (for example, V R1 volts, associated with the "read" state of the charge trapping device), the drain current I D The storage state of the charge trapping device may be indicated (eg, at a low or OFF level if in a programmed (“0”) state 112 , and at a high or ON level or state if in an erased (“1”) state 114 ).

[0030] Because the drain current of the charge trapping device can depend on the state stored in the charge trapping device when the gate voltage is maintained at the intermediate level, the state stored in the first charge trapping device can be used to affect the state stored in the second charge trapping device in a manner that simulates the IMPLY gate. Figure 1A When the first charge capture device 102 stores an erased state (“1”), the gate voltage is maintained at an intermediate level and does not cause drain current to flow, so the state stored by the second charge capture device 104 will remain the same state (e.g., “0” or “1”). However, when the first charge capture device 102 stores a programmed state (“0”), the gate voltage maintained at an intermediate level may cause drain current to flow, so that the state stored by the second charge capture device 104 may change according to the gate voltage of the second charge capture device 104.

[0031] Thus, in some embodiments, the control circuit 105 may be configured to apply a first gate voltage to the gate of the first charge capture device 102 to store the first input of the IMPLY operation as the stored value of the first charge capture device. The control circuit 105 may also be configured to apply a second gate voltage to the gate of the second charge capture device 104 to store the second input of the IMPLY operation as the stored value of the second charge capture device 104. The control circuit 105 may also be configured to update the stored value of the second charge capture device 104 based on the stored value of the first charge capture device 102 to perform the IMPLY operation. By implementing the IMPLY function using memory device cells in the associated memory device portion of the IC memory device, the footprint consumed by the charge capture device and associated logic circuitry of the IC memory device that implements the computation within the memory device may be reduced.

[0032] FIG. 2A to FIG. 2D Shows the use of Figure 1A A more detailed example of a series of operations using an IC memory device to implement the IMPLY function. Figure 2A As shown, the first charge trapping device 102 can be programmed at its gate (eg, by a programming voltage V PP ) or erase (e.g., by erasing voltage VEE ), resulting in the state “P” being stored therein. In addition, the second charge trap device 104 can be programmed or erased at its gate, resulting in the state “Q” being stored therein.

[0033] Afterwards, if Figure 2B As shown, the gates of charge capture devices 102 and 104 can be controlled to perform an IMPLY (sometimes denoted “IMP”) function with inputs P and Q, resulting in a result Q′=P IMP Q being stored in second charge capture device 104. In some embodiments, the gate of first charge capture device 102 can be set to V R1 (e.g., an intermediate level associated with the read state of the first charge capture device 102), thereby causing the drain current of the first charge capture device 102 to be set according to its storage state P. In addition, the gate of the second charge capture device 104 can be set to V EE (eg, “erased” state). The storage state of the second charge capture device 104 is set to “erased” (or high, or 1) according to the state P of the first charge capture device 102 .

[0034] like Figure 2C Provides a description as Figure 2B 1 is a truth table of the result Q' stored in the second charge capture device 104 as a result of the attempted erase operation. More specifically, if the state of the first charge capture device 102 (P) is low or 0, then when the gate is set to V R1 When the first charge capture device 102 is placed in its read state, the first charge capture device 102 is in the ON state, thereby being able to erase the second charge capture device 104, resulting in its storage state Q' being erased (e.g., high or 1). Conversely, if the state of the first charge capture device 102 (P) is high or 1, then when the gate is set to V R1 When , the first charge capture device 102 is turned off, thereby inhibiting the erasure of the second charge capture device 104, causing its stored state Q' to remain equal to its previous state Q.

[0035] Afterwards, if Figure 2D As shown, by setting the gate of the first charge capture device 102 to V R2 (thereby maintaining the state P of the first charge capture device 102 while turning on the first charge capture device 102), the new state Q' of the second charge capture device 104 can be output through its drain, and the gate of the second charge capture device 104 is set to V R1 , putting the second charge capture device 104 in a read state, thereby outputting the state Q' of the second charge capture device 104 through its drain connection.

[0036] Therefore, by properly controlling the gates of at least two charge trapping devices 102 and 104 operating as a memory device cell, an IMPLY function using the storage states of the charge trapping devices 102 and 104 can be generated.

[0037] like Figure 2E Shows Figure 1A Cross-sectional view of some embodiments of a portion of an IC memory device 100 resulting from front-end-of-line (FEOL) processing. A substrate 202 may include a plurality of source-drain regions 204 (e.g., doped regions). As used herein, a source-drain region or structure may be used as a source region or structure or a drain region or structure of a metal-oxide-semiconductor field-effect transistor (MOSFET), a thin-film transistor (TFT), or a metal-oxide-semiconductor field-effect transistor (MOSFET). Similarly, in some embodiments, each of a plurality of charge trapping structures 206 may be formed over the substrate 202 to join a corresponding pair of adjacent source-drain regions 204, and a gate structure 208 may be formed over each charge trapping structure 206. Each gate structure 208, charge trapping structure 206, and an associated pair of source-drain regions 204 may be located over an associated channel region 203 of the substrate 202, thereby forming a corresponding one of the charge trapping devices 102 and 104 coupled in series therein.

[0038] In addition, in some embodiments, each charge trapping structure 206 and associated gate structure 208 may be surrounded by spacers 207. Also, in some embodiments, at least source-drain regions 204 are at opposite ends of the series coupled charge trapping structures. Charge trapping devices 102 and 104 may be connected to other circuits using connection structures 215, which may include contacts 213, vias 223 and 233, and metal structures 214, 224, and 234 in one or more dielectric layers 212, 222, and 232. In some embodiments, each gate structure 208 may be surrounded by spacers 207. Also, in some embodiments, at least source-drain regions 204 are at opposite ends of the series coupled charge trapping structures. Charge trapping devices 102 and 104 may be connected to other circuits using connection structures 215, which may include contacts 213, vias 223 and 233, and metal structures 214, 224, and 234 in one or more dielectric layers 212, 222, and 232. Figure 2E contacts, vias, and metal structures not shown in the drawings to couple (e.g., to Figure 1A A control circuit 105) is provided to control the charge capture devices 102 and 104.

[0039] like Figure 2F Shows Figure 1ACross-sectional view of some embodiments of a portion of an IC memory device 100 resulting from back-end-of-line (BEOL) processing. In some embodiments, the substrate 202 may include source-drain regions 204 that have been doped, implanted, etc. However, in this case, a pair of source-drain regions 204 may be bridged via a dielectric structure 258 (e.g., an oxide structure) and an associated gate structure 208 to create a MOSFET that is not directly associated with a charge trapping device. Furthermore, in some embodiments, the MOSFETs may not be coupled in series, but may be isolated from each other (e.g., by a non-conductive plug 205 formed in the substrate 202 through one of the source-drain regions 204). Additionally, in some embodiments, the source and drain of the MOSFET may be coupled to other circuits via contacts 213, vias 223 and 233, and associated metal structures 214, 224, and 234 located in one or more dielectric layers 212, 222. In some embodiments, each gate structure 208 may be coupled to other circuits via contacts 213, vias 223 and 233, and associated metal structures 214, 224, and 234 located in one or more dielectric layers 212, 222. Figure 2F Contacts, vias and metal structures not shown are used to couple the control MOSFET.

[0040] like Figure 2F As shown, the charge trapping devices 102 and 104 may be formed in an upper layer (e.g., dielectric layer 242 above dielectric layer 232) of the IC memory device 100 using a thin film transistor (TFT) related process, rather than being formed at the substrate 202. In some embodiments, a gate structure 248 is formed above the dielectric layer 232 (e.g., dielectric layer 232) of each charge trapping device 102 and 104. In addition, a corresponding charge trapping structure 256 may be formed above each gate structure 248. In addition, a corresponding channel structure 252 (or channel region) may be formed above each charge trapping structure 256. A plurality of source-drain structures 257 may also be formed above the channel structure 252, such that the channel structure 252 is bridged by one of the source-drain structures 257, and each end of the channel structure 252 at opposite ends of the series coupled charge trapping devices 102 and 104 is covered by a corresponding source-drain structure 257. For example, in some embodiments, the source-drain structures 257 at the opposite ends of at least the series-coupled charge capture devices 102 and 104 may be coupled to other circuits (e.g., Figure 1A In some embodiments, the gate structure 248 may be formed through other contacts, vias, metal structures, etc. (e.g., within the dielectric layer 232 but in the Figure 2F ) coupled to other electronic circuits.

[0041] Since the IMPLY logic function is generally considered to be functionally complete, one or more IMPLY functions can be used to perform other logic functions, such as NOT, NAND, NOR, AND, OR, XOR, etc. For example, Figures 3A to 3G 1 shows a series of operations for implementing a two-input NAND function using multiple IMPLY functions using an IC memory device 300 including three charge capture devices 102, 104, and 106. Figure 3A As shown, in some embodiments, the gates of the charge capture devices 102, 104, and 106 may be set to a programming voltage V PP (e.g., associated with a “programmed” state of each charge trapping device 102, 104, and 106) to store a 0 (low) state in each charge trapping device 102, 104, and 106. Figure 3B As shown, the gate of the first charge capture device 102 can then be set to V PP (the “programmed” state of the first charge trapping device 102) or V EE (the “erased” state of the first charge capture device 102) respectively stores the corresponding state P as 0 or 1. At the same time, the gate of the second charge capture device 104 can be set to V PP or V EE , to store the corresponding state Q as 0 or 1 respectively. At the same time, the gate of the third charge capture device 106 can be set to the inhibition voltage V INH (eg, associated with an “inhibited” state) to prevent the current state (0) of the third charge capture device 106 from changing when the first and second charge capture devices 102 and 104 are programmed to the P and Q states, respectively.

[0042] Afterwards, if Figure 3C As shown, the gate of the first charge capture device 102 can be set to V R2 (so that the first charge capture device 102 is turned on without disturbing its storage state P), and the gate of the second charge capture device 104 can be set to V R1 (Thereby placing the second charge capture device 104 in its read state to allow its drain output to be set based on its storage state Q). At the same time, the gate of the third charge capture device 106 may be set to V EE (For the erased state, the current state (S) of the third charge capture device 106 may be set to “erased” based on the state Q expressed by the second charge capture device 104).

[0043] like Figure 3D A truth table is provided that describes the Figure 3CThe result S' stored in the third charge capture device 106 as a result of the attempted erase operation is shown. More specifically, if the state of the second charge capture device 104 (Q) is low or 0, then when the gate of the second charge capture device 104 is set to V R1 , the second charge capture device 104 is turned on to place the second charge capture device 104 in its read state, thereby enabling the third charge capture device 106 to be erased, resulting in its storage state S' being erased (e.g., high or 1). Conversely, if the state of the second charge capture device 104 (Q) is high or 1, then when the gate is set to V R1 When Q is 0, the first charge trapping device 102 is turned off, thereby inhibiting erasure of the second charge trapping device 104, causing its storage state S' to remain equal to its previous state 0. Therefore, the resulting storage state S' is the inverse of Q (S'=QIMP 0=NOT Q).

[0044] After that, Figure 3E Instructs to use an additional IMPLY operation of P IMP S'. To perform the above function, in some embodiments, the gates of the first, second and third charge trapping devices 102, 104 and 106 can be set to V R1 、V R2 and V EE As a result, the state P of the first charge capture device 102 is expressed at its drain, and the second charge capture device 104 is turned on, thereby transmitting the state P of the first charge capture device 102 to the third charge capture device 106, while the second charge capture device 104 maintains its current state Q. Therefore, based on the expression state P of the first charge capture device 102, the gate of the third charge capture device 104 is set to V EE It may be possible to enable erasure of the current state (S′) of the third charge capture device 106 .

[0045] like Figure 3F Provides a description as Figure 3E 1 is a truth table of the result S" stored in the third charge capture device 106 as a result of the attempted erase operation. More specifically, if the state of the first charge capture device 102(P) is low or 0, then the erase of the third charge capture device 106 is enabled, causing its storage state S" to be erased (e.g., high or 1). Conversely, if the state of the first charge capture device 102(P) is high or 1, then when the gate is set to V R1 When placing the first charge capture device 102 in the read state, the first charge capture device 102 is turned off, thereby inhibiting erasure of the third charge capture device 106, causing its storage state S" to remain equal to its previous state S'. Therefore, the resulting storage state S" = P IMP S' = P IMP (Q IMP 0) = P NAND Q.

[0046] Afterwards, if Figure 3G As shown, by setting the gates of the first charge capture device 102 and the second charge capture device 104 to V R2 (thereby turning on the first and second charge capture devices 102 and 104 while maintaining their respective states P and Q), and setting the gate of the third charge capture device 106 to V R1 , thereby connecting the state S" of the third charge capture device 106 through its drain output.

[0047] like Figure 3H Shows Figure 3A A cross-sectional view of some embodiments of a portion of an IC memory device 300 resulting from FEOL processing. The substrate 202 may include four source-drain regions 204 (eg, doped regions). In some embodiments, the substrate 202 may include four source-drain regions 204 (eg, doped regions). Figure 2E In the manner shown, each of the plurality of charge trapping structures 206 may be formed over the substrate 202 to engage a corresponding pair of adjacent source-drain regions 204, and a gate structure 208 may be formed over each charge trapping structure 206. Each gate structure 208, charge trapping structure 206, and associated pair of source-drain regions 204 may thus form a respective one of the series coupled charge trapping devices 102, 104, and 106.

[0048] In addition, in some embodiments, each charge trapping structure 206 and associated gate structure 208 may be surrounded by spacers 207. Also, in some embodiments, at least the source-drain region 204 at opposite ends of the series coupled charge trapping devices 102, 104, and 106 may be connected to other circuits using contacts 213, vias 223 and 233, and metal structures 214, 224, and 234 located in one or more dielectric layers 212, 222, and 232. In some embodiments, the gate structure of each gate structure 208 may be surrounded by spacers 207. Figure 3H contacts, vias, and metal structures not shown in the figure to couple (e.g., Figure 1A A control circuit 105) is provided to control the charge capture devices 102, 104 and 106.

[0049] like Fig. 3I Shows Figure 3ACross-sectional view of some embodiments of a portion of an IC memory device 300 resulting from BEOL processing. In some embodiments, substrate 202 may include source-drain regions 204 that have been doped, implanted, etc. However, in such cases, at least some adjacent pairs of source-drain regions 204 may be bridged via dielectric structures 258 and associated gate structures 208 to create MOSFETs that are not directly associated with charge trapping devices, as described herein. Additionally, in some embodiments, the MOSFETs may not be coupled in series, but may be isolated from one another by a non-conductive plug 205 formed in substrate 202 through one of the source-drain regions 204, as described above in conjunction with Figure 2F In addition, in some embodiments, the source and drain of the MOSFET can be coupled to other circuits through the contact 213, the through-holes 223 and 233, and the related metal structures 214, 224 and 234 located in one or more dielectric layers 212, 222. In some embodiments, each gate structure 208 can be connected to other circuits through Fig. 3I Contacts, vias and metal structures not shown are coupled to control the MOSFET.

[0050] like Fig. 3I As shown, the charge trapping devices 102 and 104 may be formed in an upper layer (e.g., dielectric layer 242 above dielectric layer 232) of the IC memory device 300 using a thin film transistor (TFT) related process, rather than being formed at the substrate 202. In some embodiments, a gate structure 248 is formed above the dielectric layer (e.g., dielectric layer 232) of each charge trapping device 102 and 104. In addition, a corresponding charge trapping structure 256 may be formed above each gate. In addition, a corresponding channel structure 252 may be formed above each charge trapping structure 256. A plurality of source-drain structures 257 may also be formed above the channel structure 252, such that the channel structure 252 is bridged by one of the source-drain structures 257, and each end of the channel structure 252 at opposite ends of the series-coupled charge trapping devices 102 and 104 is covered by a corresponding one of the source-drain structures 257. Furthermore, in some embodiments, the source-drain structures 257 at the opposite ends of at least the series-coupled charge capture devices 102 and 104 may be coupled to other circuits (e.g., Figure 1A In some embodiments, the gate structure 248 may be formed through other contacts, vias, metal structures, etc. (e.g., within the dielectric layer 232 but in the Fig. 3I ) coupled to other electronic circuits.

[0051] like Figure 4 The method 400 is shown in the form of a flow chart, which shows FIG. 2A to FIG. 2FSome embodiments of the operation of the IC memory device 100. Although the methods and other methods shown and / or described herein are shown as a series of steps or events, it should be understood that the present disclosure is not limited to the order or steps shown. Therefore, in some embodiments, the steps may be performed in an order different from the order shown, and / or may be performed simultaneously. In addition, in some embodiments, the steps or events shown may be subdivided into multiple steps or events, which may be performed at a separate time or simultaneously with other steps or sub-steps. In some embodiments, some of the steps or events shown may be omitted, and other steps or events not shown may be included.

[0052] At step 402, a first charge capture device and a second charge capture device (eg, Figure 1A At step 404, the first input of the IMPLY operation is stored as a stored value of the first charge capture device (eg, state P, such as Figure 2A At step 406, the second input of the IMPLY operation is stored as a stored value of the second charge capture device (eg, state Q, as shown). Figure 2A In step 408, the storage value of the second charge capture device is updated based on the storage value of the first charge capture device to perform an IMPLY operation (eg, state Q', as shown). Figure 2B shown).

[0053] like Figure 5 The method 500 is shown in the form of a flow chart, which shows FIG. 3A to FIG. 3I In step 502, each of the one or more inputs to a logic function is stored in a corresponding one of a plurality of charge trapping devices coupled in series (eg, Figure 3B In step 504, one or more IMPLY operations are performed between corresponding pairs of the plurality of charge capture devices to perform a logic function (e.g., FIG. 3C to FIG. 3F As shown, a state S" is generated. In step 506, the result of the logic function is output from one of the plurality of charge capture devices.

[0054] like Figure 6 A schematic diagram of some embodiments of a portion of an IC memory device 600 is shown that includes five charge capture devices 102, 104, 106, 108, and 110 to implement one or more logic functions using one or more IMPLY functions while also functioning as a memory device unit in accordance with the present disclosure. Figure 6Five charge capture devices are depicted in FIG. 1 , but they are not identical, and any number of charge capture devices greater than two may be used in other embodiments. For example, Figure 6 As shown, the first and second charge capture devices 102 and 104 may be used to perform an IMPLY function (e.g., as described above in conjunction with FIG. 2A to FIG. 2D ) and / or the third to fifth charge capture devices 106, 108 and 110 may be used to perform a NAND function (e.g., as described above in conjunction with Figures 3A to 3G discussed).

[0055] Reference Figure 6 In some embodiments, the gate connection 602 of each of the charge capture devices 102, 104, 106, 108, and 110 may be controlled (e.g., by Figure 1A control circuit 105). In addition, the first source-drain connection 604 of the first charge capture device 102 and the second source-drain connection 605 of the fifth charge capture device 110 and the gate connection 602 can facilitate logic and / or output control of the five charge capture devices 102, 104, 106, 108 and 110 according to their logic and / or memory device functions. In addition, at least one additional source-drain connection 606 coupling two adjacent charge capture devices (e.g., charge capture devices 104 and 106) can provide one or more outputs (e.g., one or more outputs of at least one logic function implemented by the charge capture devices 102, 104, 106, 108 and 110). Although Figure 6 A single additional source-drain connection 606 is shown, but other embodiments may include multiple additional source-drain connections 606 involving multiple pairs of charge trapping devices.

[0056] Therefore, in some embodiments, Figure 6 As shown, a series of charge capture devices can be operated as a typical series-coupled IC memory device (e.g., a NAND memory device) and simultaneously used as an IC logic device, such as for use in an in-memory computing architecture. Such an embodiment can maintain the IC footprint typically consumed by the charge capture device of the IC memory device (e.g., by providing the logic function in the IC memory device via separate control circuits of the IC memory device).

[0057] 7A to 7F Shown as Figure 6 A series of cross-sectional views of an IC memory device 600 resulting from FEOL processing are shown in a series of progressive manufacturing steps. Fig. 7A A substrate 202 is provided as a foundation upon which the final IC memory device 600 may be constructed. In some embodiments, the substrate 202 may be p-doped silicon, although other materials may be used in other embodiments.

[0058] like Figure 7B As shown, a plurality of doped regions 204 (eg, n-doped regions) may be formed in the substrate 202 (eg, by ion implantation). Figure 7C As shown, each of a plurality of charge trapping structures 206 (eg, ferroelectric structures including ferroelectric materials) may be formed over the substrate 202 to bridge two consecutive doped regions 204. Figure 7C In some embodiments, a gate structure 208 may be formed above each charge trapping structure 206 to form Figure 7C The charge capture devices 102, 104, 106, 108 and 110. In addition, Fig.7D As shown, spacers 207 may be formed (eg, conformally) around each charge trapping structure 206 and associated gate structure 208 .

[0059] In some embodiments, reference Fig. 7E , in some embodiments, a dielectric layer 212 (e.g., an oxide, such as silicon dioxide) can be formed over the substrate 202. Further, in some embodiments, a connection structure 215 including a contact 213 and an associated metal structure 214 can be formed. The connection structure 215 is coupled to the source-drain region 204 at a first end of a charge capture device (e.g., the first charge capture device 102) to form a first source-drain connection 604. Further, the connection structure 215 can be coupled to the source-drain connection 604. The source-drain region 204 is located at a second end of a charge capture device (e.g., the fifth charge capture device 110) to form a second source-drain connection 605. Further, the connection structure 215 can be coupled to the source-drain region 204 associated with the second and third charge capture devices 104 and 106 to form additional source-drain connections 606. As shown Figure 7F As shown, the connection structure 215 can be connected to one or more vias 223 and 233 and additional metal structures 224 and 234 to extend the first source-drain connection 604, the second source-drain connection 605, and / or the additional source-drain connection 606. In some embodiments, the gate structure 208 can be connected to the gate structure 208 through other contacts, vias, metal structures, etc. (e.g., within the dielectric layer 212, but not in the dielectric layer 212). Fig. 7E and Figure 7F ) coupled to other electronic circuits.

[0060] Figure 8 The method 800 is shown in flow chart form, illustrating some embodiments of the present concepts.

[0061] At step 802 , a plurality of source-drain regions (eg, source-drain regions 204 ) may be formed in a substrate (eg, substrate 202 ). Fig. 7A and 7B A cross-sectional view corresponding to some embodiments of step 802 is shown.

[0062] A plurality of charge trapping structures (eg, charge trapping structures 206 ) may be formed over substrate 202 . Figure 7C A cross-sectional view corresponding to some embodiments of step 804 is shown.

[0063] At step 806 , a corresponding gate structure (eg, gate structure 208 ) may be formed over each charge trapping structure 206 . Figure 7C and Fig.7D A cross-sectional view corresponding to some embodiments of step 806 is shown.

[0064] At step 808, a first connection (eg, first source-drain connection 604) is formed between a first source-drain region at a first end of the plurality of charge trapping devices and a first metal structure. Fig. 7E A cross-sectional view corresponding to some embodiments of step 808 is shown.

[0065] At step 810, a second connection (eg, second source-drain connection 605) is formed between a second source-drain region at a second end of the plurality of charge trapping devices and a second metal structure. Fig. 7E A cross-sectional view corresponding to some embodiments of step 810 is shown.

[0066] At step 812, a third connection (eg, additional source-drain connection 606) is formed between an additional source-drain region in the plurality of source-drain regions and the third metal structure. Fig. 7E A cross-sectional view corresponding to some embodiments of step 812 is shown.

[0067] 9A to 9F Shown as Figure 6 A series of cross-sectional views of an IC memory device 600 resulting from BEOL processing are shown in a series of progressive manufacturing steps. Fig.9A 6 shows the starting structure of the BEOL processing of the IC memory device 600. More specifically, Fig.9A A plurality of MOSFETs are shown, which include a source-drain region 204 in a substrate 202, a dielectric structure 258, a gate structure 208 and a non-conductive plug 205, on top of which a plurality of contacts 213, through-holes 223 and 233 and metal structures 214, 224 and 234 are formed within dielectric layers 212, 222 and 232.

[0068] like Fig. 9B As shown, the gate structure 248, the charge trapping structure 256, and the channel structure 252 may be formed as a layer above the dielectric layer 232. Fig. 9C, the gate structure 248, the charge trapping structure 256, and the channel structure 252 may be patterned, etched, etc. to form a plurality of (e.g., five) gate structures 248, charge trapping structures 256, and channel structures 252, each of which is associated with a corresponding charge trapping device 102, 104, 106, 108, and 110. In other embodiments, one or more of the gate structure 248, the charge trapping structure 256, and the channel structure 252 may be patterned, etched, etc. to form a plurality of (e.g., five) gate structures 248, charge trapping structures 256, and channel structures 252, each of which is associated with a corresponding charge trapping device 102, 104, 106, 108, and 110. Fig. 9B The structures shown can be patterned or etched individually. Fig.9D As shown, a dielectric layer 242 may be added to fill the areas not occupied by the gate structure 248 , the charge trapping structure 256 , and the channel structure 252 . Fig.9D The structure may also be planarized (eg, by chemical mechanical planarization (CMP)) to facilitate formation of additional layers or structures.

[0069] Afterwards, refer to Fig.9E , multiple source-drain structures 257 may be formed over channel structure 252 such that channel structure 252 is bridged by one of the source-drain structures 257 and each end of channel structure 252 is at an opposite end of the series structure. Coupled charge trapping devices (e.g., at charge trapping devices 102 and 110) are covered by respective source-drain structures 257.

[0070] refer to Fig.9F In some embodiments, additional dielectric material of dielectric layer 242 may be added, wherein contacts 253 and metal structures 254 may be added to form a first source-drain connection 604 at a first end of source-drain structure 257 (e.g., at first charge capture device 102), a second source-drain connection 605 at a second (opposite) end of source-drain structure 257 (e.g., at fifth charge capture device 110), and a third source-drain connection 606 at additional source-drain structures (e.g., shared by charge capture devices 104 and 106). Furthermore, in some embodiments, gate structure 248 may be connected to gate structure 248 by other contacts, vias, metal structures, etc. (e.g., within dielectric layer 232 but not within dielectric layer 232). Fig.9F ) coupled to other electronic circuits.

[0071] Fig.10 Method 1000 is shown in flowchart form, which illustrates some embodiments of the present concept. Steps 1002 to 1014 may correspond to, for example, 9A to 9F In some embodiments, one or more of steps 1002 to 1014 are TFT manufacturing process steps.

[0072] At step 1002, a plurality of gate structures (eg, gate structures 248) may be formed over a dielectric layer (eg, dielectric layer 232). Fig.9A A cross-sectional view corresponding to some embodiments of step 1002 is shown.

[0073] At step 1004 , a corresponding charge trapping structure of a plurality of charge trapping structures (eg, charge trapping structure 256 ) may be formed over each gate structure of the plurality of gate structures. Fig. 9B and 9C A cross-sectional view corresponding to some embodiments of step 1004 is shown.

[0074] At step 1006 , a corresponding channel material structure of a plurality of channel material structures (eg, channel structure 252 ) may be formed over each of the plurality of charge trapping structures. Fig. 9B and 9C A cross-sectional view corresponding to some embodiments of step 1006 is shown.

[0075] At step 1008, a plurality of source-drain structures (e.g., source-drain structure 257) may be formed over the plurality of channel material structures. In some embodiments, each source-drain structure may connect a corresponding pair of the plurality of channel material structures, or be formed at a first end or a second end of a first or last channel material structure to form a plurality of channel material structures. Charge capture devices (e.g., charge capture devices 102, 104, 106, 108, and 110) connected in series. Fig.9E A cross-sectional view corresponding to some embodiments of step 1008 is shown.

[0076] At step 1010, a first connection (e.g., first source-drain connection 604) may be formed between a first source-drain structure of a plurality of source-drain structures at a first end of a charge trap device (e.g., charge trap device 102), and a first metal structure (e.g., metal structure 254). Fig.9F A cross-sectional view corresponding to some embodiments of step 1010 is shown.

[0077] At step 1012, a second connection (e.g., second source-drain connection 605) may be formed between a second source-drain structure of the plurality of source-drain structures at a second end of a charge trap device (e.g., charge trap device 110), and a second metal structure (e.g., metal structure 254). Fig.9F A cross-sectional view corresponding to some embodiments of step 1012 is shown.

[0078] At step 1014, a third connection (e.g., third source-drain connection 606) may be formed between an additional source-drain structure in the plurality of source-drain structures (e.g., between charge trapping devices 104 and 106) and a metal structure (e.g., metal structure 254). Fig.9F A cross-sectional view corresponding to some embodiments of step 1014 is shown.

[0079] Some embodiments relate to an integrated circuit memory device, which includes a first charge capture device, a second charge capture device, and a control circuit. The first charge capture device includes a first charge capture structure disposed on a substrate between a first gate structure and a first channel region. The second charge capture device is coupled in series with the first charge capture device and includes a second charge capture structure disposed on the substrate between the second gate structure and the second channel region. The control circuit is coupled to the first gate structure of the first charge capture device and the second gate structure of the second charge capture device. The control circuit is configured to store a first input of an IMPLY operation as a stored value of the first charge capture device, store a second input of the IMPLY operation as a stored value of the second charge capture device, and update the stored value of the second charge capture device to perform an IMPLY operation based on the stored value of the first charge capture device.

[0080] Some embodiments relate to an integrated circuit memory device including a plurality of charge capture devices coupled in series and a control circuit coupled to a gate connection of each of the plurality of charge capture devices. The control circuit is configured to store each of one or more inputs of a logic function in a corresponding one of the plurality of charge capture devices and to perform one or more IMPLY operations using the plurality of charge capture devices to perform the logic function. Each of the one or more IMPLY operations is performed using the stored value of each of the associated pair of the plurality of charge capture devices.

[0081] Some embodiments relate to a method of performing a logic function in an integrated circuit memory device. The method includes storing each of one or more inputs to the logic function in a corresponding one of a plurality of charge capture devices, wherein the plurality of charge capture devices are coupled in series. The method also includes performing one or more IMPLY operations using the plurality of charge capture devices to perform the logic function, wherein each of the one or more IMPLY operations is performed using a stored value of each of a related pair of the plurality of charge capture devices. The method also includes outputting a result of the logic function from one of the plurality of charge capture devices.

[0082] It should be understood that in the written description and the appended claims, the terms "first", "second", "second", "third", etc. are merely general identifiers used to distinguish different terms for the convenience of describing different elements of a figure or series of figures. By themselves, these terms do not imply any temporal order or structural proximity of these devices, and are not intended to describe different illustrated embodiments and / or corresponding devices in non-illustrated embodiments. For example, the "first dielectric layer" described in conjunction with the first figure may not necessarily correspond to the "first dielectric layer" described in conjunction with another figure, and may not necessarily correspond to the "first dielectric layer" in non-illustrated embodiments.

[0083] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that the equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications to them herein without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated circuit memory device, characterized in that: include: A first charge trapping device including a first charge trapping structure disposed above the substrate between the first gate structure and the first channel region; a second charge trapping device coupled in series with the first charge trapping device, the second charge trapping device comprising a second charge trapping structure disposed above the substrate between a second gate structure and a second channel region; as well as a control circuit coupled to the first gate structure of the first charge trapping device and the second gate structure of the second charge trapping device, wherein the control circuit is configured to: A first input to the STORAGE IMPLY operation is a stored value of the first charge capture device; storing a second input of the IMPLY operation as a stored value of the second charge capture device; as well as The stored value of the second charge trapping device is updated according to the stored value of the first charge trapping device to perform the IMPLY operation.

2. The integrated circuit memory device according to claim 1, wherein: Updating the stored value of the second charge trapping device comprises: placing the first charge capture device in a read state; and The second charge trapping device is placed in an erased state.

3. The integrated circuit memory device according to claim 1, wherein: Also includes: a third charge trapping device coupled in series with the second charge trapping device, the third charge trapping device comprising a third charge trapping structure disposed on the substrate between a third gate structure and a third channel region, wherein the control circuit is further configured to: Outputting an updated value of the second charge trap device.

4. The integrated circuit memory device according to claim 1, wherein: The drain of the first charge trapping device is directly connected to the source of the second charge trapping device.

5. The integrated circuit memory device according to claim 1, wherein: The first charge trapping structure includes a first ferroelectric structure and the second charge trapping structure includes a second ferroelectric structure.

6. The integrated circuit memory device according to claim 1, wherein: The first channel region and the second channel region are disposed in the substrate between source-drain regions.

7. The integrated circuit memory device according to claim 1, wherein: Also includes: a connection structure disposed within the dielectric structure above the substrate; Each of the first charge trapping device and the second charge trapping device is disposed over at least a portion of the dielectric structure.

8. An integrated circuit memory device comprising: a plurality of charge trapping devices coupled in series; as well as a control circuit coupled to a gate connection of each of the plurality of charge trapping devices, wherein the control circuit is configured to: each of the one or more inputs to the logic function is stored in a corresponding one of the plurality of charge trap devices; and One or more IMPLY operations are performed using the plurality of charge trap devices to perform a logic function, wherein each of the one or more IMPLY operations is performed using a stored value of each of an associated pair of the plurality of charge trap devices.

9. The integrated circuit memory device according to claim 8, wherein: For at least one of the one or more IMPLY operations, a drain connection of a first charge trapping device of the associated pair of the plurality of charge trapping devices is directly connected to a source connection of a second charge trapping device of the associated pair of the plurality of charge trapping devices.

10. The integrated circuit memory device according to claim 8, wherein: The logic function is a two-input NAND function; The plurality of charge capture devices include a first charge capture device, a second charge capture device, and a third charge capture device; as well as Storing each of the one or more inputs comprises: placing the first charge trapping device, the second charge trapping device and the third charge trapping device into a programming state respectively; as well as A first input of the two-input NAND function is stored in the first charge capture device, and a second input of the two-input NAND function is stored in the second charge capture device, while the third charge capture device is placed in a disabled state.

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