Chip packaging structure

Abstract

The utility model discloses a chip packaging structure, and belongs to the field of chip packaging. The first surface of the chip is provided with an IC circuit, and the second surface of the chip is provided with a bottom plate; the first surface and the second surface of the chip are opposite, the first surface is the front surface of the chip, and the second surface is the back surface of the chip. According to the utility model, the MEMS chip and the IC circuit are stacked up and down, so that the size of a packaged product is greatly reduced; in addition, the IC circuit is used as a cover plate to limit the up-and-down deformation of the mass block in the MEMS chip, so that the mass block is prevented from being broken under the action of huge impact, and the robustness of the cantilever beam in the MEMS chip is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of chip packaging, and particularly relates to a chip packaging structure. Background Art

[0002] MEMS refers to high-tech devices with dimensions in millimeters or even smaller, and their internal structures are generally in the micron or even nanometer scale, and it is an independent intelligent system.

[0003] The piezoelectric MEMS accelerometer is an accelerometer device prepared based on the piezoelectric effect and combined with semiconductor processes, and its core technology is the multi-cantilever beam-mass block architecture. When an acceleration is applied to the device, the mass block will vibrate, thereby generating a potential difference on the surface of the piezoelectric surface.

[0004] Currently, the LGA (Land Grid Array) packaging method is usually used to lay and wire the MEMS chip and the IC circuit to form a complete packaging structure, as Figure 1 shown. Due to the laying and wiring, the size of this packaging product is relatively large; and when the acceleration is too large, the mass block is prone to break under the action of a huge impact, and the limitation of the mass block in the MEMS chip needs to be realized through the bonding of an additional glass sheet or silicon wafer, which makes the packaging structure more complex. Summary of the Utility Model

[0005] The purpose of the utility model is to provide a chip packaging structure to solve the problems in the background art.

[0006] To solve the above technical problems, the utility model provides a chip packaging structure, including:

[0007] A chip (11);

[0008] An IC circuit (12) is arranged on the first surface of the chip (11), and a bottom plate (13) is arranged on the second surface; wherein,

[0009] The first surface and the second surface of the chip (11) are opposite;

[0010] A PAD (16) is arranged on the first surface of the chip (11), and a pad (15) is arranged on the surface of the bottom plate (13) away from the chip (11);

[0011] The PAD (16) is connected to the pad (15) through a lead (17).

[0012] In an embodiment, the IC circuit (12) is arranged on the first surface of the chip (11) through a bonding material, and the bottom plate (13) is arranged on the second surface of the chip (11) through an epoxy resin (14).

[0013] In one embodiment, a metal shell (18) covers the bottom plate (13), and the metal shell (18) completely covers the chip (11), the IC circuit (12), the epoxy resin (14), the PAD (16), and the lead (17).

[0014] In one embodiment, the bonding material is gold, tin, or aluminum.

[0015] In one embodiment, the PAD (16) is in contact with the bonding material.

[0016] In one embodiment, the bottom plate (13) is a PCB board or a lead frame.

[0017] The present utility model further provides a chip packaging structure, including:

[0018] A chip (21);

[0019] A first surface of the chip (21) is provided with an IC circuit (22), and a second surface is provided with a bottom plate (24); wherein,

[0020] The first surface and the second surface of the chip (21) are opposite;

[0021] The chip (21) is located on one side of the IC circuit (22), and pads (25) are provided on the other side of the IC circuit (22) away from the chip (21).

[0022] In one embodiment, the IC circuit (22) is disposed on the first surface of the chip (21) by ball implantation (23); the ball implantation (23) is connected to the pads (25) through TSV vias (26) passing through the IC circuit (21).

[0023] In one embodiment, the ball implantation (23) is a gold ball or a tin ball; the bottom plate (24) is glass or a silicon substrate.

[0024] The chip packaging structure provided by the present utility model greatly reduces the size of the packaged product by stacking the MEMS chip and the IC circuit up and down; in addition, by using the IC circuit as a cover plate, the up and down deformation of the mass block in the MEMS chip is limited, avoiding the fracture phenomenon of the mass block under the action of a huge impact, and improving the robustness of the cantilever beam in the MEMS chip. Description of the Drawings

[0025] Figure 1 It is a schematic structural diagram of a traditional LGA packaging of an MEMS chip and an IC circuit.

[0026] Figure 2It is a schematic structural diagram of the first encapsulation method provided by the present utility model.

[0027] Figure 3 It is a schematic structural diagram of the second encapsulation method provided by the present utility model. Detailed implementation manners

[0028] The following further elaborates in detail on a chip packaging structure proposed by the present utility model in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present utility model will be clearer. It should be noted that the accompanying drawings are all in very simplified forms and use non-precise scales, only for facilitating and clearly assisting in explaining the purpose of the embodiments of the present utility model.

[0029] In this application, the serial numbers assigned to the components themselves, such as "first", "second", etc., are only used to distinguish the described objects and do not have any sequential or technical meanings. And the "connection" and "coupling" mentioned in this application, unless otherwise specifically stated, are not limited to physical or mechanical connections, and may include electrical communication connections, whether direct or indirect. In the description of this application, it should be understood that the orientation or positional relationships indicated by the terms "upper", "lower", "front", "rear", "left", "right", "middle", "between", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. are based on the orientation or positional relationships shown in the accompanying drawings, and are only for facilitating the description of this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be construed as a limitation to this application.

[0030] In this application, unless otherwise clearly specified and limited, the first feature being "on" or "under" the second feature can be that the first and second features are in direct contact, or the first and second features are indirectly in contact through an intermediate medium. Moreover, the first feature being "above", "over" and "on" the second feature can be that the first feature is directly above or obliquely above the second feature, or merely indicates that the first feature has a higher horizontal height than the second feature. The first feature being "under", "beneath" and "under" the second feature can be that the first feature is directly below or obliquely below the second feature, or merely indicates that the first feature has a lower horizontal height than the second feature. Moreover, the term "comprising", "including" or any other variation thereof is intended to cover a non-exclusive inclusion.

[0031] Embodiment 1

[0032] Embodiment 1 of the present utility model provides a first implementation manner of a chip packaging structure, and its structure is as Figure 2 shown, including a chip 11, an IC circuit 12, a PCB board 13, an epoxy resin 14, a solder pad 15, a PAD 16, a lead 17, and a metal shell 18.

[0033] The IC circuit 12 is disposed on the first side of the chip 11 through a bonding material, the PCB board 13 is disposed on the second side of the chip 11 through an epoxy resin 14, and the first side and the second side of the chip 11 are opposite to each other. In general actual situations, the first side is the front side of the chip, and the second side is the back side of the chip; the bonding material can be gold, tin or aluminum.

[0034] The chip 11 is located on one side of the PCB board 13, and the pads 15 are disposed on the other side of the PCB board 13 away from the chip 11. A PAD 16 is disposed on the chip 11, and the PAD 16 is in contact with the bonding material; one end of the lead 17 is connected to the PAD 16, and the other end passes through the PCB board 13 and is connected to the pad 15. The IC circuit 12 conducts signals to the PAD 16 through the bonding material, and the PAD 16 then conducts the signals to the pad 15 through the lead 17, and finally realizes external signal communication through the pad 15.

[0035] In addition, the metal shell 18 covers the PCB board 13 and completely covers the chip 11, the IC circuit 12, the epoxy resin 14, the PAD16, and the lead 17.

[0036] The PCB board 13 can also be replaced by a lead frame.

[0037] Embodiment 2

[0038] The second embodiment of the present invention provides a second implementation manner of the chip packaging structure, and its structure is as Figure 3 shown, including a chip 21, an IC circuit 22, a ball grid array (BGA) ball 23, a bottom plate 24, a pad 25, and a through-silicon via (TSV) via 26.

[0039] The IC circuit 22 is disposed on the first side of the chip 21 through the BGA ball 23, the bottom plate 24 is bonded to the second side of the chip 21, and the first side and the second side of the chip 21 are opposite to each other.

[0040] The chip 21 is located on one side of the IC circuit 22, and pads 25 are disposed on the other side of the IC circuit 22 away from the chip 21. The pads 25 are connected to the BGA balls 23 through the TSV via 26 passing through the IC circuit 21 to transmit signals.

[0041] The BGA ball 23 can be a gold ball or a tin ball; the bottom plate 24 can be glass or a silicon substrate.

[0042] The chip packaging structure of the present utility model greatly reduces the size of the packaged product by stacking the MEMS chip and the IC circuit up and down; in addition, the IC circuit is used as a cover plate to limit the up and down deformation of the mass block in the MEMS chip, avoiding the fracture phenomenon of the mass block under the action of huge impact and improving the robustness of the cantilever beam in the MEMS chip.

[0043] The above description is only a description of the preferred embodiments of the present utility model, and does not limit the scope of the present utility model in any way. Any changes and modifications made by those of ordinary skill in the field of the present utility model based on the above disclosure are within the scope of protection of the claims.

Claims

1. A chip packaging structure, characterized in that: include: Chip (11); The first surface of the chip (11) is provided with an IC circuit (12), and the second surface is provided with a base plate (13); wherein, The first surface and the second surface of the chip (11) are opposite to each other; A PAD (16) is provided on a first surface of the chip (11), and a solder pad (15) is provided on a surface of the base plate (13) away from the chip (11); The PAD (16) is connected to the pad (15) via a lead wire (17).

2. The chip packaging structure according to claim 1, characterized in that: The IC circuit (12) is arranged on the first surface of the chip (11) through a bonding material, and the base plate (13) is arranged on the second surface of the chip (11) through an epoxy resin (14).

3. The chip packaging structure according to claim 2, characterized in that: The base plate (13) is covered with a metal shell (18), and the metal shell (18) completely covers the chip (11), the IC circuit (12), the epoxy resin (14), the PAD (16), and the lead (17).

4. The chip packaging structure according to claim 2, characterized in that: The bonding material is gold, tin or aluminum.

5. The chip packaging structure according to claim 2, characterized in that: The PAD (16) is in contact with the bonding material.

6. The chip packaging structure according to claim 1, characterized in that: The base plate (13) is a PCB board or a lead frame.

7. A chip packaging structure, characterized in that: include: Chip (21); The first surface of the chip (21) is provided with an IC circuit (22), and the second surface is provided with a base plate (24); wherein, The first surface and the second surface of the chip (21) are opposite to each other; The chip (21) is located on one side of the IC circuit (22), and a pad (25) is provided on the other side of the IC circuit (22) away from the chip (21).

8. The chip packaging structure according to claim 7, characterized in that: The IC circuit (22) is arranged on the first surface of the chip (21) through a ball implant (23); the ball implant (23) passes through the IC circuit (21) through a TSV through hole (26) and is connected to the pad (25).

9. The chip packaging structure according to claim 8, characterized in that: The implant ball (23) is a gold ball or a solder ball; and the base plate (24) is a glass or silicon substrate.

Images