Potential detection circuit and potential detection device

Abstract

The utility model discloses a potential detection circuit and a potential detection device, the potential detection circuit comprises a pull-up module, the first end of the pull-up module is coupled with a power supply end, and the second end of the pull-up module is used for being coupled with a detected circuit node; the first end of the pull-down module is coupled to the node of the tested circuit, and the second end of the pull-down module is coupled to the reference ground; the detection module comprises at least two triggers which are connected in series, and the first trigger in the at least two triggers which are connected in series is coupled with the detected circuit node; the detection module is configured to have a detection period and is used for outputting a detection signal after at least one detection period, the detection signal is used for representing the state of a detected circuit node, and the state comprises a power connection state, a grounding state or a floating state; the detection signal comprises at least two digital signals output by at least two triggers connected in series. Through the mode, the problem that the floating state of the circuit node cannot be detected is solved.

Description

Technical Field

[0001] This application relates to the technical field of electronic circuits, and particularly to a potential detection circuit and a potential detection device. Background Art

[0002] In electronic circuit technology, circuits with corresponding functions are formed through the coupling of corresponding electronic components. And the circuit can provide corresponding circuit nodes for cooperation with the rest of the circuit. For the potential of a certain circuit node, its state needs to be detected, and its states may be: 1. Connected to the power supply state; 2. Grounded state; 3. Floating state.

[0003] Related technologies usually connect a large resistor between the circuit node to be measured and the ground, and then detect the state of the circuit node to be measured. In this way, there are only two states of the circuit node to be measured: 1. Connected to the power supply; 2. Grounded; that is, the floating state is eliminated, resulting in the inability to detect the floating state of the circuit node. Summary of the Utility Model

[0004] This application provides a potential detection circuit and a potential detection device to solve the problem of inability to detect the floating state of a circuit node.

[0005] To solve the above technical problem, a technical solution adopted in this application is: to provide a potential detection circuit, which includes: a pull-up module, the first end of the pull-up module is coupled to the power supply terminal, and the second end of the pull-up module is used to be coupled to the circuit node to be measured; a pull-down module, the first end of the pull-down module is coupled to the circuit node to be measured, and the second end of the pull-down module is coupled to the reference ground; a detection module, the detection module includes at least two serially connected flip-flops, wherein, the first flip-flop of the at least two serially connected flip-flops is coupled to the circuit node to be measured; the detection module is configured to have a detection period and is used to output a detection signal after at least one detection period, the detection signal is used to characterize the state of the circuit node to be measured, and the states include the power supply connection state, the ground connection state or the floating state; the detection signal includes at least two digital signals output by at least two serially connected flip-flops.

[0006] Among them, the detection module includes a first flip-flop and a second flip-flop, the first flip-flop is coupled to the circuit node to be measured, and the second flip-flop is serially connected with the first flip-flop; within the detection period, the pull-up module conducts and cuts off in response to the first control signal; after the detection period, the second flip-flop outputs a corresponding digital signal; within the detection period, the pull-down module conducts and cuts off in response to the second control signal; after the detection period, the first flip-flop outputs a corresponding digital signal; wherein, the pull-up module and the pull-down module do not conduct simultaneously.

[0007] Among them, the detection module includes a first trigger and a second trigger. The first trigger is coupled to the circuit node under test, and the second trigger is connected in series with the first trigger; during the detection period, the pull-down module conducts and cuts off in response to the first control signal; after the detection period, the second trigger outputs a corresponding digital signal; during the detection period, the pull-up module conducts and cuts off in response to the second control signal; after the detection period, the first trigger outputs a corresponding digital signal; among them, the pull-up module and the pull-down module do not conduct simultaneously.

[0008] Among them, the potential detection circuit further includes: a control module, which is coupled to the pull-up module and the pull-down module, and is used to control the pull-up module and the pull-down module to conduct or cut off respectively.

[0009] Among them, the pull-up module includes a first transistor. The first end of the first transistor is coupled to the power supply terminal, and the second end of the first transistor is used to be coupled to the circuit node under test.

[0010] Among them, the pull-down module includes a second transistor. The first end of the second transistor is coupled to the circuit node under test, and the second end of the second transistor is coupled to the reference ground.

[0011] Among them, the conduction duration of the pull-up module is greater than a first duration; where the first duration is the ratio of the product of the capacitance of the circuit node under test and the power supply terminal voltage to the conduction current when the pull-up module conducts; the conduction duration of the pull-down module is greater than a second duration; where the second duration is the ratio of the product of the capacitance of the circuit node under test and the power supply terminal voltage to the conduction current when the pull-down module conducts.

[0012] Among them, the detection module includes a first D flip-flop and a second D flip-flop; the data input terminal of the first D flip-flop is coupled to the circuit node under test, and the data output terminal of the first D flip-flop is coupled to the data input terminal of the second D flip-flop; among them, the digital signals output by the data output terminal of the first D flip-flop and the data output terminal of the second D flip-flop are used to characterize the state of the circuit node under test.

[0013] Among them, the potential detection circuit further includes: a selection module, the selection module includes at least two input terminals, each input terminal is configured to be respectively coupled to a circuit node under test, and the selection module responds to the control signal to select the corresponding target input terminal to conduct with the output terminal, so that the circuit node under test coupled to the target input terminal is connected to the second end of the pull-up module.

[0014] To solve the above technical problems, another technical solution adopted by this application is: to provide a potential detection device, including the potential detection circuit provided by the above technical solution.

[0015] The beneficial effects of the embodiments of the present application are as follows: Different from the prior art, the present application provides a potential detection circuit and a potential detection device. The potential detection circuit includes: a pull-up module, the first end of the pull-up module is coupled to the power supply terminal, and the second end of the pull-up module is used to be coupled to the circuit node to be measured; a pull-down module, the first end of the pull-down module is coupled to the circuit node to be measured, and the second end of the pull-down module is coupled to the reference ground; a detection module, the detection module includes at least two serially connected flip-flops, wherein, the first flip-flop of the at least two serially connected flip-flops is coupled to the circuit node to be measured; the detection module is configured to have a detection period and is used to output a detection signal after at least one detection period, the detection signal is used to characterize the state of the circuit node to be measured, and the state includes a power supply connection state, a ground connection state or a floating state; the detection signal includes at least two digital signals output by the at least two serially connected flip-flops. By the above method, the pull-up module and the pull-down module are turned on and off during the detection period, and then the serially connected flip-flops in the detection module are used to output corresponding digital signals after at least one detection period to form a detection signal, and the detection signal is used to characterize the power supply connection state, the ground connection state or the floating state of the circuit node to be measured, thereby solving the problem that the floating state of the circuit node cannot be detected. Further, as a digital circuit, the flip-flop has a small size, which can make the potential detection device more miniaturized. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0017] Among them:

[0018] Figure 1 is a schematic structural diagram of the first embodiment of the potential detection circuit provided by the present application;

[0019] Figure 2 is a schematic structural diagram of the second embodiment of the potential detection circuit provided by the present application;

[0020] Figure 3 is a timing diagram of the control module provided by the present application;

[0021] Figure 4 is a schematic structural diagram of the third embodiment of the potential detection circuit provided by the present application

[0022] Figure 5 is a schematic structural diagram of the fourth embodiment of the potential detection circuit provided by the present application;

[0023] Figure 6It is a schematic structural diagram of an embodiment of the potential detection device provided by this application. Specific Embodiments

[0024] Next, the technical solutions in the embodiments of this application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of this application. It can be understood that the specific embodiments described herein are only used to explain this application, rather than limiting this application. In addition, it should be noted that for the convenience of description, only parts related to this application rather than all structures are shown in the drawings. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of this application.

[0025] Referring to "embodiment" herein means that the specific features, structures, or characteristics described in connection with the embodiment may be included in at least one embodiment of this application. The phrase appears in various positions in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art explicitly and implicitly understand that the embodiments described herein may be combined with other embodiments.

[0026] In electronic circuit technology, through the coupling of corresponding electronic components, a circuit with corresponding functions is formed. And this circuit can provide corresponding circuit nodes for cooperation with the rest of the circuit. For the potential of a certain circuit node, it is necessary to detect its state, and its states may be: 1. Connected to the power supply state; 2. Grounded state; 3. Floating state.

[0027] The inventors of this application have found through long-term research that related technologies usually connect a large resistor between the circuit node to be measured and the ground, and then detect the state of the circuit node to be measured. In this way, there are only two states of the circuit node to be measured: 1. Connected to the power supply; 2. Grounded; that is, the floating state is eliminated, resulting in the inability to detect the floating state of the circuit node.

[0028] Based on this, this application proposes any of the following technical solutions to solve any of the above problems.

[0029] Refer to Figure 1 , Figure 1 It is a schematic structural diagram of the first embodiment of the potential detection circuit provided by this application. The potential detection circuit 100 includes: a pull-up module 10, a pull-down module 20, and a detection module 30.

[0030] Among them, the first end of the pull-up module 10 is coupled to the power supply terminal, and the second end of the pull-up module 10 is used to be coupled to the circuit node to be measured.

[0031] The first end of the pull-down module 20 is coupled to the circuit node to be measured, and the second end of the pull-down module 20 is coupled to the reference ground.

[0032] The detection module 30 is coupled to the circuit node under test. Among them, the detection module 30 includes at least two serially connected flip-flops. Among them, the first flip-flop of the at least two serially connected flip-flops is coupled to the circuit node under test.

[0033] The detection module 30 is configured to have a detection period and is used to output a detection signal after at least one detection period. The detection signal is used to characterize the state of the circuit node under test, and the state includes a power-connected state, a grounded state, or a floating state. The detection signal includes at least two digital signals output by at least two serially connected flip-flops.

[0034] In an application scenario, taking Figure 1 the detection module 30 in which includes a first flip-flop and a second flip-flop as an example for illustration:

[0035] The first flip-flop is coupled to the circuit node under test, and the second flip-flop is connected in series with the first flip-flop.

[0036] During the detection period, the pull-up module 10 conducts and cuts off in response to the first control signal; after the detection period, the second flip-flop outputs a corresponding digital signal. During the detection period, the pull-down module 20 conducts and cuts off in response to the second control signal; after the detection period, the first flip-flop outputs a corresponding digital signal; among them, the pull-up module 10 and the pull-down module 20 do not conduct simultaneously.

[0037] That is, during the detection period, the pull-up module 10 conducts in response to the first control signal and provides an electrical signal to the circuit node under test. Among them, when the pull-up module 10 is conducting, the pull-down module 20 is cut off; after the pull-up module 10 changes from conducting to cut off, the first flip-flop and the second flip-flop will output corresponding digital signals according to the corresponding clock signals. For example, at the rising edge of the clock signal, the flip-flop outputs the state of the input terminal to the output terminal. For example, if the input terminal of the flip-flop before the rising edge of the clock signal is high level, the output terminal is 1, and if the input terminal of the flip-flop before the rising edge of the clock signal is low level, the output terminal is 0. Among them, when the pull-up module 10 changes from conducting to cut off, it is after the falling edge of the first clock signal. Therefore, at the rising edge of the second clock signal, the first flip-flop can output the state of the circuit node under test after the pull-up module 10 is cut off to the second flip-flop, so that at the rising edge of the third clock signal, the second flip-flop outputs a corresponding digital signal. At this time, the corresponding digital signal output by the second flip-flop records the state of the circuit node under test after the pull-up module 10 changes from conducting to cut off.

[0038] During the detection period, the pull-down module 20 conducts in response to the second control signal. After the pull-down module 20 changes from conducting to cut off, the first flip-flop and the second flip-flop will output corresponding digital signals according to the corresponding clock signals.

[0039] That is, within the detection period, after the pull-up module 10 is turned on, since the first end of the pull-up module 10 is coupled to the power supply terminal, the power supply terminal can provide a high-level electrical signal to the circuit node under test through the pull-up module 10. After the pull-up module 10 is turned on for a preset time (T 1 ), the pull-up module 10 is controlled to be turned off. After the pull-up module 10 is turned off, under the control of the clock signal, the first flip-flop and the second flip-flop will output corresponding digital signals, which are used to represent the state of the circuit node under test after the pull-up module 10 is turned off. Meanwhile, the pull-down module 20 is always turned off and does not affect the potential of the circuit node under test. Among them, when the pull-up module 10 changes from being turned on to being turned off, it is after the falling edge of the first clock signal. Therefore, at the rising edge of the second clock signal, the first flip-flop can output the state of the circuit node under test after the pull-up module 10 is turned off to the second flip-flop, so that at the rising edge of the third clock signal, the second flip-flop outputs a corresponding digital signal. At this time, the corresponding digital signal output by the second flip-flop records the state of the circuit node under test after the pull-up module 10 is turned off. For example, the digital signal output by the first flip-flop at the rising edge of the second clock signal is represented by Q 1 1, and the digital signal output by the second flip-flop at the rising edge of the third clock signal is represented by Q 0 1. That is, Q 1 1 and Q 0 1 can represent the state of the circuit node under test after the pull-up module 10 is turned off.

[0040] After the pull-up module 10 is turned off for a preset time, within the detection period, the pull-down module 20 is turned on in response to the second control signal. Since the pull-down module 20 is coupled to the reference ground, when the pull-down module 20 is turned on, it will ground the circuit node under test, thereby pulling down the electrical signal of the circuit node under test. After the pull-down module 20 is turned on for a preset time (T 2 ), the pull-down module 20 is controlled to be turned off. After the pull-down module 20 is turned off, under the control of the clock signal, the first flip-flop and the second flip-flop will output corresponding digital signals, which are used to represent the state of the circuit node under test after the pull-down module 20 is turned off. Among them, when the pull-down module 20 changes from being turned on to being turned off (i.e., after T 2 ), it is after the falling edge of the third clock signal. Therefore, at the rising edge of the fourth clock signal, the first flip-flop can output the state of the circuit node under test after the pull-down module 20 is turned off to the second flip-flop, so that at the rising edge of the fifth clock signal, the second flip-flop outputs a corresponding digital signal. For example, the digital signal output by the first flip-flop at the rising edge of the fourth clock signal is represented by Q 1 2, and the digital signal output by the second flip-flop at the rising edge of the fifth clock signal is represented by Q 0 2. That is, Q 1 2 and Q 02 can characterize the state of the circuit node under test after the pull-down module 20 is turned off.

[0041] Combining the digital signals output by the second flip-flop and the first flip-flop at the rising edges of different clock signals, the state of the circuit node under test can be clearly known.

[0042] For example, when Q 1 1 is 0 and Q 0 1 is 0, it indicates that after the pull-up module 10 is turned on and off at time T 1 , the high-level electrical signal provided by the pull-up module 10 to the circuit node under test no longer exists. At this time, it can be determined that the state of the circuit node under test is grounded. Further, because the state of the circuit node under test is grounded, the pull-down module 20 has no effect on it when it is turned on and off at time T 2 . Therefore, Q 1 2 is 0 and Q 0 2 is 0.

[0043] For example, when Q 1 1 is 1 and Q 0 1 is 1, it indicates that after the pull-up module 10 is turned on and off at time T 1 , the circuit node under test remains at a high-level electrical signal. At this time, the state of the circuit node under test may be connected to the power supply or floating. After the pull-down module 20 is turned on and off at time T 2 , Q 1 2 is 1 and Q 0 2 is 1, it indicates that even if the pull-down module 20 is turned on and off at time T 2 , it cannot change the fact that the circuit node under test remains at a high-level electrical signal. Therefore, it can be determined that the state of the circuit node under test is connected to the power supply.

[0044] After the pull-down module 20 is turned on and off at time T 2 , Q 1 2 is 0 and Q 0 2 is 0, it indicates that when the pull-down module 20 is turned on and off at time T 2 , it changes the electrical signal of the circuit node under test, pulling it down from a high-level electrical signal to a low-level electrical signal. Therefore, it can be determined that the state of the circuit node under test is floating.

[0045] In some embodiments, the correspondence between the digital signals output by the above flip-flops and the circuit node under test can be simplified. For example, the digital signal output by the first flip-flop at the rising edge of the fourth clock signal is Q 1 2. Since before the rising edge of the fourth clock signal, the digital signal Q 0 1 output by the second flip-flop still characterizes the state of the circuit node under test after the pull-up module 10 is turned off and before the pull-down module 20 is turned on. Therefore, through the digital signal Q 0 1 and the digital signal Q1 The combination of 2 is used to characterize the state of the circuit node under test. For example, at Q 0 1Q 1 When 2 is 0X, it indicates that the state of the circuit node under test is grounded. Here, X represents 0 or 1.

[0046] At Q 0 1Q 1 When 2 is 10, it indicates that the state of the circuit node under test is floating. At Q 0 1Q 1 When 2 is 11, it indicates that the state of the circuit node under test is connected to the power supply.

[0047] In another application scenario, taking the detection module 30 in Figure 1 as an example for illustration: The first flip - flop is coupled to the circuit node under test, and the second flip - flop is connected in series with the first flip - flop.

[0048] During the detection period, the pull - down module conducts and cuts off in response to the first control signal; after the detection period, the second flip - flop outputs a corresponding digital signal. During the detection period, the pull - up module conducts and cuts off in response to the second control signal; after the detection period, the first flip - flop outputs a corresponding digital signal; where the pull - up module and the pull - down module do not conduct simultaneously.

[0049] That is, during the detection period, the pull - down module 20 conducts in response to the first control signal and provides an electrical signal to the circuit node under test. Here, when the pull - down module 20 is conducting, the pull - up module 10 is cut off; after the pull - down module 20 changes from conducting to cut - off, the first flip - flop and the second flip - flop will output corresponding digital signals according to the corresponding clock signals. For example, at the rising edge of the clock signal, the flip - flop outputs the state of the input terminal to the output terminal. For instance, if the input terminal of the flip - flop before the rising edge of the clock signal is at a high level, the output terminal is 1, and if the input terminal of the flip - flop before the rising edge of the clock signal is at a low level, the output terminal is 0. Among them, when the pull - down module 20 changes from conducting to cut - off, it is after the falling edge of the first clock signal. Therefore, at the rising edge of the second clock signal, the first flip - flop can output the current state of the circuit node under test to the second flip - flop, so that at the rising edge of the third clock signal, the second flip - flop outputs a corresponding digital signal. At this time, the corresponding digital signal output by the second flip - flop records the state of the circuit node under test after the pull - down module 20 changes from conducting to cut - off.

[0050] During the detection period, the pull - up module 10 conducts in response to the second control signal; after the pull - up module changes from conducting to cut - off, at least two series - connected flip - flops, the first flip - flop and the second flip - flop will output corresponding digital signals according to the corresponding clock signals.

[0051] That is, within the detection period, after the pull-down module 20 is turned on, since the pull-down module 20 is coupled to the reference ground, the node of the circuit under test is pulled to a low level. After the pull-down module 20 is turned on for a preset time (T 2 ), the pull-down module 20 is controlled to turn off. After the pull-down module 20 is turned off, under the control of the clock signal, the first flip-flop and the second flip-flop will output corresponding digital signals, which are used to characterize the state of the node of the circuit under test after the pull-down module 20 is turned off. At the same time, the pull-up module 10 is always turned off and does not affect the potential of the node of the circuit under test. Among them, when the pull-down module 20 changes from on to off, it is after the falling edge of the first clock signal. Therefore, at the rising edge of the second clock signal, the first flip-flop can output the state of the node of the circuit under test after the pull-down module 20 is turned off to the second flip-flop, so that at the rising edge of the third clock signal, the second flip-flop outputs a corresponding digital signal. At this time, the corresponding digital signal output by the second flip-flop records the state of the node of the circuit under test after the pull-down module 20 is turned off. For example, the digital signal output by the first flip-flop at the rising edge of the second clock signal is represented by Q 1 1, and the digital signal output by the second flip-flop at the rising edge of the third clock signal is represented by Q 0 1.

[0052] After the pull-down module 20 is turned off for a preset time, within the detection period, the pull-up module 10 is turned on in response to the second control signal. Since the pull-up module 10 is coupled to the power supply terminal, when the pull-up module 10 is turned on, it will pull the node of the circuit under test to a high level. After the pull-up module 10 is turned on for a preset time (T 1 ), the pull-up module 10 is controlled to turn off. After the pull-up module 10 is turned off, under the control of the clock signal, the first flip-flop and the second flip-flop will output corresponding digital signals, which are used to characterize the state of the node of the circuit under test after the pull-up module 10 is turned off. Among them, when the pull-up module 10 changes from on to off (that is, after T 1 ), it is after the falling edge of the third clock signal. Therefore, at the rising edge of the fourth clock signal, the first flip-flop can output the current state of the node of the circuit under test to the second flip-flop, so that at the rising edge of the fifth clock signal, the second flip-flop outputs a corresponding digital signal. For example, the digital signal output by the first flip-flop at the rising edge of the fourth clock signal is represented by Q 1 2, and the digital signal output by the second flip-flop at the rising edge of the fifth clock signal is represented by Q 0 2.

[0053] By combining the digital signals output by the second flip-flop and the first flip-flop at the rising edges of different clock signals, the state of the node of the circuit under test can be clearly known.

[0054] For example, Q 1 1 is 0, Q 0When 1 is 0, it indicates that the pull - down module 20 is at T 2 After the pull - down module 20 conducts and cuts off at time T, it pulls down the measured circuit node to a low level. At this time, the state of the measured circuit node is grounded or floating. The pull - up module 10 is at T 1 After the pull - up module 10 conducts and cuts off at time T, Q 1 2 is 1, Q 0 When 2 is 1, it indicates that the pull - up module 10 is at T 1 After the pull - up module 10 conducts and cuts off at time T, it changes the electrical signal of the measured circuit node, pulling it up from a low - level electrical signal to a high - level electrical signal. Therefore, it can be determined that the state of the measured circuit node is floating.

[0055] The pull - up module 10 is at T 1 After the pull - up module 10 conducts and cuts off at time T, Q 1 2 is 0, Q 0 When 2 is 0, it indicates that the pull - up module 10 is at T 1 After the pull - up module 10 conducts and cuts off at time T, it does not change the electrical signal of the measured circuit node. Therefore, it can be determined that the state of the measured circuit node is grounded.

[0056] For example, Q 1 1 is 1, Q 0 When 1 is 1, it indicates that the pull - down module 20 is at T 2 After the pull - down module 20 conducts and cuts off at time T, it does not change the electrical signal of the measured circuit node. At this time, the state of the measured circuit node is connected to the power supply. The pull - up module 10 is at T 1 After the pull - up module 10 conducts and cuts off at time T, Q 1 2 is 1, Q 0 When 2 is 1, it indicates that even if the pull - up module 10 is at T 1 After the pull - up module 10 conducts and cuts off at time T, it cannot change the measured circuit node from continuously being at a high - level electrical signal. Therefore, it can be determined that the state of the measured circuit node is connected to the power supply.

[0057] In some embodiments, the correspondence between the digital signal output by the above - mentioned flip - flop and the measured circuit node can be simplified. For example, the digital signal output by the first flip - flop at the rising edge of the fourth clock signal is Q 1 2. Since before the rising edge of the fourth clock signal, the digital signal Q 0 1 output by the second flip - flop still represents the state of the measured circuit node after the pull - down module 20 cuts off and before the pull - up module 10 conducts. Therefore, through the combination of the digital signal Q 0 1 and the digital signal Q 1 2 to represent the state of the measured circuit node. For example, when Q 0 1Q 1 2 is 00, it represents that the state of the measured circuit node is grounded. When Q 0 1Q 1 2 is 01, it represents that the state of the measured circuit node is floating. When Q 01Q 1 When it is 11, it represents that the state of the circuit node under test is connected to the power supply.

[0058] In other embodiments, other combination methods can be adopted to represent the state of the circuit node under test.

[0059] In this embodiment, the pull-up module 10 and the pull-down module 20 are turned on and off during the detection period, and then the flip-flops connected in series in the detection module 30 output corresponding digital signals after at least one detection period to form a detection signal. The detection signal is used to represent the power supply connection state, ground connection state or floating state of the circuit node under test, thereby solving the problem of being unable to detect the floating state of the circuit node. Further, as the type of the flip-flop of the digital circuit is small, the potential detection device can be made more miniaturized.

[0060] Refer to Figure 2 , Figure 2 is a schematic structural diagram of the second embodiment of the potential detection circuit provided by the present application. The potential detection circuit 100 includes: a pull-up module 10, a pull-down module 20, a detection module 30 and a control module 40.

[0061] Among them, the first end of the pull-up module 10 is coupled to the power supply terminal, and the second end of the pull-up module 10 is used to be coupled to the circuit node under test.

[0062] The first end of the pull-down module 20 is coupled to the circuit node under test, and the second end of the pull-down module 20 is coupled to the reference ground.

[0063] The control module 40 is coupled to the pull-up module 10 and the pull-down module 20, and is used to control the pull-up module 10 and the pull-down module 20 to be turned on or off respectively.

[0064] Combined with Figure 3 for illustration:

[0065] The control module 40 controls the pull-up module 10 to be turned on within the time of T 1 , and the control module 40 controls the pull-down module 20 to be turned on within the time of T 2 , so that the flip-flop outputs corresponding digital signals at the rising edge of the corresponding clock signal after the time of T 1 and the flip-flop outputs corresponding digital signals at the rising edge of the corresponding clock signal after the time of T 2 . The state of the circuit node under test is represented by the digital signal.

[0066] Among them, the conduction duration T 1 of the pull-up module 10 is greater than the first duration; among them, the first duration is the ratio of the product of the capacitance of the circuit node under test and the voltage of the power supply terminal to the conduction current when the pull-up module 10 is conducting. Such as T 1 >C pad ×VDD / I 上拉 Among them, T 1 represents the conduction duration of the pull-up module 10, and C pad represents the capacitance of the circuit node to be measured, and V DD represents the voltage of the power supply terminal, and I 上拉 represents the conduction current when the pull-up module 10 is conducting.

[0067] The conduction duration T of the pull-down module 20 2 is greater than the second duration; among them, the second duration is the ratio between the product of the capacitance of the circuit node to be measured and the voltage of the power supply terminal and the conduction current when the pull-down module 20 is conducting. T 2 >C pad ×V DD / I 下拉 Among them, T 2 represents the conduction duration of the pull-down module 20, and C pad represents the capacitance of the circuit node to be measured, and V DD represents the voltage of the power supply terminal, and I 下拉 represents the conduction current when the pull-down module 20 is conducting.

[0068] For the working modes of the remaining pull-up module 10, pull-down module 20, and detection module 30, reference can be made to any embodiment of this application, and no description will be given here.

[0069] In this embodiment, the control module 40 is used to control the pull-up module 10 and the pull-down module 20 to conduct and cut off within the detection period, and then the flip-flops connected in series in the detection module 30 are used to output corresponding digital signals to form a detection signal after at least one detection period. The detection signal is used to characterize the power supply state, ground state, or floating state of the circuit node to be measured, thereby solving the problem that the floating state of the circuit node cannot be detected. Further, as the type of the flip-flop in the digital circuit is small, the potential detection device can be made more miniaturized.

[0070] Refer to Figure 4 , Figure 4 which is a schematic structural diagram of the third embodiment of the potential detection circuit provided by this application. The potential detection circuit 100 includes: a pull-up module 10, a pull-down module 20, a detection module 30, and a selection module 50.

[0071] The selection module 50 includes at least two input terminals, and each input terminal is configured to be respectively coupled to a circuit node to be measured. The selection module 50 responds to a control signal and selects a corresponding target input terminal to conduct with the output terminal, so that the circuit node to be measured coupled to the target input terminal is connected to the second end of the pull-up module 10. As Figure 4 shown, the selection module 50 includes at least N input terminals.

[0072] For the working modes of the remaining pull-up module 10, pull-down module 20, and detection module 30, reference can be made to any embodiment of this application, which will not be described here.

[0073] In this embodiment, multiple circuit nodes to be measured can be simultaneously connected to the input end of the selection module 50. Then, during detection, the selection module 50 can be directly used to select and perform switching detection on the circuit nodes to be measured, without the need to manually connect a new circuit node to be measured to the potential detection circuit 100 again after the detection of a single circuit node to be measured is completed, thereby improving the detection efficiency and quickly realizing the detection of a large number of circuit nodes.

[0074] Refer to Figure 5 , Figure 5 FIG. is a schematic structural diagram of a fourth embodiment of the potential detection circuit provided by this application. The potential detection circuit 100 includes: a first transistor Q1, a second transistor Q2, a detection module 30, and a control module 40. The detection module 30 includes a first D flip-flop and a second D flip-flop.

[0075] Among them, the first end of the first transistor Q1 is coupled to the power supply terminal, and the second end of the first transistor Q1 is used to be coupled to the circuit node to be measured.

[0076] Among them, the first end of the second transistor Q2 is coupled to the circuit node to be measured, and the second end of the second transistor Q2 is coupled to the reference ground.

[0077] The control module 40 is coupled to the control ends of the first transistor Q1 and the second transistor Q2, and is used to control the first transistor Q1 and the second transistor Q2 to be turned on or off respectively.

[0078] The data input terminal of the first D flip-flop is coupled to the circuit node to be measured, and the data output terminal of the first D flip-flop is coupled to the data input terminal of the second D flip-flop; among them, the digital signals output by the data output terminal of the first D flip-flop and the data output terminal of the second D flip-flop are used to represent the state of the circuit node to be measured.

[0079] In some embodiments, during a detection period, the first transistor Q1 is turned on in response to a first control signal to provide an electrical signal to a circuit node under test. When the first transistor Q1 is on, the second transistor Q2 is off. After the first transistor Q1 changes from on to off, the first flip-flop and the second flip-flop output corresponding digital signals according to corresponding clock signals. For example, at the rising edge of the clock signal, the flip-flop outputs the state of the input terminal to the output terminal. For example, if the input terminal of the flip-flop before the rising edge of the clock signal is at a high level, the output terminal is 1; if the input terminal of the flip-flop before the rising edge of the clock signal is at a low level, the output terminal is 0. When the first transistor Q1 changes from on to off, it is after the falling edge of the first clock signal. Therefore, at the rising edge of the second clock signal, the first flip-flop can output the state of the circuit node under test after the first transistor Q1 is off to the second flip-flop, so that the second flip-flop outputs a corresponding digital signal at the rising edge of the third clock signal. At this time, the corresponding digital signal output by the second flip-flop records the state of the circuit node under test after the first transistor Q1 changes from on to off.

[0080] During the detection period, the second transistor Q2 is turned on in response to a second control signal. After the second transistor Q2 changes from on to off, the first flip-flop and the second flip-flop output corresponding digital signals according to corresponding clock signals.

[0081] That is, during the detection period, after the first transistor Q1 is turned on, since the first end of the first transistor Q1 is coupled to the power supply terminal, the power supply terminal can provide a high-level electrical signal to the circuit node under test through the first transistor Q1. After the first transistor Q1 is turned on for a preset time (T 1 ), the first transistor Q1 is controlled to turn off. After the first transistor Q1 is turned off, under the control of the clock signal, the first flip-flop and the second flip-flop output corresponding digital signals, which are used to represent the state of the circuit node under test after the first transistor Q1 is turned off. At the same time, the second transistor Q2 is always off and does not affect the potential of the circuit node under test. When the first transistor Q1 changes from on to off, it is after the falling edge of the first clock signal. Therefore, at the rising edge of the second clock signal, the first flip-flop can output the state of the circuit node under test after the first transistor Q1 is off to the second flip-flop, so that the second flip-flop outputs a corresponding digital signal at the rising edge of the third clock signal. At this time, the corresponding digital signal output by the second flip-flop records the state of the circuit node under test after the first transistor Q1 is turned off. For example, the digital signal output by the first flip-flop at the rising edge of the second clock signal is represented by Q 1 1, and the digital signal output by the second flip-flop at the rising edge of the third clock signal is represented by Q 0 1. That is, Q 11. Q 0 1 can characterize the state of the circuit node under test after the first transistor Q1 is turned off.

[0082] After the first transistor Q1 is turned off for a preset time, within the detection period, the second transistor Q2 is turned on in response to the second control signal. Since the second transistor Q2 is coupled to the reference ground, when the second transistor Q2 is turned on, it will ground the circuit node under test, thereby pulling down the electrical signal of the circuit node under test. After the second transistor Q2 is turned on for a preset time (T 2 ), control the second transistor Q2 to turn off. After the second transistor Q2 is turned off, under the control of the clock signal, the first flip-flop and the second flip-flop will output corresponding digital signals to characterize the state of the circuit node under test after the second transistor Q2 is turned off. Among them, when the second transistor Q2 changes from on to off (i.e., after T 2 ), it is after the falling edge of the third clock signal. Therefore, at the rising edge of the fourth clock signal, the first flip-flop can output the state of the circuit node under test after the second transistor Q2 is turned off to the second flip-flop, so that at the rising edge of the fifth clock signal, the second flip-flop outputs a corresponding digital signal. For example, the digital signal output by the first flip-flop at the rising edge of the fourth clock signal is represented by Q 1 2, and the digital signal output by the second flip-flop at the rising edge of the fifth clock signal is represented by Q 0 2. That is, Q 1 2, Q 0 2 can characterize the state of the circuit node under test after the second transistor Q2 is turned off.

[0083] By combining the digital signals output by the second flip-flop and the first flip-flop at the rising edges of different clock signals, the state of the circuit node under test can be clearly known.

[0084] For example, when Q 1 1 is 0 and Q 0 1 is 0, it means that after the first transistor Q1 is turned on and off at time T 1 , the high-level electrical signal provided by the first transistor Q1 to the circuit node under test no longer exists. At this time, it can be determined that the state of the circuit node under test is grounded. Further, since the state of the circuit node under test is grounded, the on and off of the second transistor Q2 at time T 2 has no effect on it. Therefore, Q 1 2 is 0 and Q 0 2 is 0.

[0085] For example, when Q 1 1 is 1 and Q 0 1 is 1, it means that after the first transistor Q1 is turned on and off at time T 1After the time conduction and cutoff, the node of the circuit under test remains at a high-level electrical signal. At this time, the state of the node of the circuit under test may be connected to the power supply or floating. The second transistor Q2 is at T 2 After the time conduction and cutoff, Q 1 2 is 1, and when Q 0 2 is 1, it indicates that even if the second transistor Q2 conducts and cuts off at T 2 time, it cannot change the node of the circuit under test to remain at a high-level electrical signal. Therefore, it can be determined that the state of the node of the circuit under test is connected to the power supply.

[0086] After the second transistor Q2 conducts and cuts off at T 2 time, Q 1 2 is 0, and when Q 0 2 is 0, it indicates that the second transistor Q2 conducts and cuts off at T 2 time, changing the electrical signal of the node of the circuit under test, pulling it down from a high-level electrical signal to a low-level electrical signal. Therefore, it can be determined that the state of the node of the circuit under test is floating.

[0087] In some embodiments, the correspondence between the digital signal output by the above trigger and the node of the circuit under test can be simplified. For example, the digital signal output by the first trigger at the rising edge of the fourth clock signal is Q 1 2. Since before the rising edge of the fourth clock signal, the digital signal Q 0 1 output by the second trigger still represents the state of the node of the circuit under test after the first transistor Q1 is cutoff and before the second transistor Q2 conducts. Therefore, the state of the node of the circuit under test is represented by the combination of the digital signal Q 0 1 and the digital signal Q 1 2. For example, when Q 0 1Q 1 2 is 0X, it represents that the state of the node of the circuit under test is grounded. Where X represents 0 or 1.

[0088] When Q 0 1Q 1 2 is 10, it represents that the state of the node of the circuit under test is floating. When Q 0 1Q 1 2 is 11, it represents that the state of the node of the circuit under test is connected to the power supply.

[0089] In some other embodiments, during a detection period, the second transistor Q2 is turned on in response to a first control signal to provide an electrical signal to a circuit node under test. When the second transistor Q2 is on, the first transistor Q1 is off. After the second transistor Q2 changes from on to off, the first flip-flop and the second flip-flop output corresponding digital signals according to corresponding clock signals. For example, at the rising edge of a clock signal, the flip-flop outputs the state of its input terminal to the output terminal. For instance, if the input terminal of the flip-flop is at a high level before the rising edge of the clock signal, the output terminal is 1; if the input terminal of the flip-flop is at a low level before the rising edge of the clock signal, the output terminal is 0. When the second transistor Q2 changes from on to off, it is after the falling edge of the first clock signal. Therefore, at the rising edge of the second clock signal, the first flip-flop can output the current state of the circuit node under test to the second flip-flop, so that at the rising edge of the third clock signal, the second flip-flop outputs a corresponding digital signal. At this time, the corresponding digital signal output by the second flip-flop records the state of the circuit node under test after the second transistor Q2 changes from on to off.

[0090] During a detection period, the first transistor Q1 is turned on in response to a second control signal; after at least two series-connected flip-flops change from on to off in a pull-up mode, the first flip-flop and the second flip-flop output corresponding digital signals according to corresponding clock signals.

[0091] That is, during a detection period, after the second transistor Q2 is turned on, since the second transistor Q2 is coupled to a reference ground, the circuit node under test is pulled to a low level. After the second transistor Q2 is turned on for a preset time (T 2 ), the second transistor Q2 is controlled to turn off. After the second transistor Q2 is turned off, under the control of a clock signal, the first flip-flop and the second flip-flop output corresponding digital signals, which are used to characterize the state of the circuit node under test after the second transistor Q2 is turned off. At the same time, the first transistor Q1 is always off and does not affect the potential of the circuit node under test. When the second transistor Q2 changes from on to off, it is after the falling edge of the first clock signal. Therefore, at the rising edge of the second clock signal, the first flip-flop can output the state of the circuit node under test after the second transistor Q2 is turned off to the second flip-flop, so that at the rising edge of the third clock signal, the second flip-flop outputs a corresponding digital signal. At this time, the corresponding digital signal output by the second flip-flop records the state of the circuit node under test after the second transistor Q2 is turned off. For example, the digital signal output by the first flip-flop at the rising edge of the second clock signal is represented by Q 1 1, and the digital signal output by the second flip-flop at the rising edge of the third clock signal is represented by Q 0 1.

[0092] After the second transistor Q2 is turned off for a preset time, within the detection period, the first transistor Q1 is turned on in response to the second control signal. Since the first transistor Q1 is coupled to the power supply terminal, when the first transistor Q1 is turned on, it will pull the circuit node under test to a high level. After the first transistor Q1 is turned on for a preset time (T 1 ), the first transistor Q1 is controlled to turn off. After the first transistor Q1 is turned off, under the control of the clock signal, the first flip-flop and the second flip-flop will output corresponding digital signals, which are used to characterize the state of the circuit node under test after the first transistor Q1 is turned off. Among them, when the first transistor Q1 changes from on to off (i.e., after T 1 ), it is after the falling edge of the third clock signal. Therefore, at the rising edge of the fourth clock signal, the first flip-flop can output the current state of the circuit node under test to the second flip-flop, so that at the rising edge of the fifth clock signal, the second flip-flop outputs a corresponding digital signal. For example, the digital signal output by the first flip-flop at the rising edge of the fourth clock signal is represented by Q 1 2, and the digital signal output by the second flip-flop at the rising edge of the fifth clock signal is represented by Q 0 2.

[0093] By combining the digital signals output by the second flip-flop and the first flip-flop at the rising edges of different clock signals, the state of the circuit node under test can be clearly known.

[0094] For example, when Q 1 1 is 0 and Q 0 1 is 0, it means that after the second transistor Q2 is turned on and off at time T 2 , the second transistor Q2 pulls the circuit node under test to a low level. At this time, the state of the circuit node under test is grounded or floating. After the first transistor Q1 is turned on and off at time T 1 , when Q 1 2 is 1 and Q 0 2 is 1, it means that the first transistor Q1 is turned on and off at time T 1 , changing the electrical signal of the circuit node under test and pulling it from a low-level electrical signal to a high-level electrical signal. Therefore, it can be determined that the state of the circuit node under test is floating.

[0095] After the first transistor Q1 is turned on and off at time T 1 , when Q 1 2 is 0 and Q 0 2 is 0, it means that the first transistor Q1 is turned on and off at time T 1 , without changing the electrical signal of the circuit node under test. Therefore, it can be determined that the state of the circuit node under test is grounded.

[0096] For example, when Q 1 1 is 1 and Q 0 1 is 1, it means that the second transistor Q2 is at T2 After the time conduction is cut off, the electrical signal of the node of the circuit under test is not changed. At this time, the state of the node of the circuit under test is connected to the power supply. The first transistor Q1 is at T 1 After the time conduction is cut off, Q 1 2 is 1, and when Q 0 2 is 1, it indicates that even if the first transistor Q1 is turned on and off at T 1 time, it is impossible to change the node of the circuit under test to continuously have a high-level electrical signal. Therefore, it can be determined that the state of the node of the circuit under test is connected to the power supply.

[0097] In some embodiments, the correspondence between the digital signal output by the above trigger and the node of the circuit under test can be simplified. For example, the digital signal output by the first trigger at the rising edge of the fourth clock signal is Q 1 2. Since before the rising edge of the fourth clock signal, the digital signal Q 0 1 output by the second trigger still represents the state of the node of the circuit under test after the second transistor Q2 is cut off and before the first transistor Q1 is turned on. Therefore, through the digital signal Q 0 1 and the digital signal Q 1 2 are combined to represent the state of the node of the circuit under test. For example, when Q 0 1Q 1 2 is 00, it represents that the state of the node of the circuit under test is grounded. When Q 0 1Q 1 2 is 01, it represents that the state of the node of the circuit under test is floating. When Q 0 1Q 1 2 is 11, it represents that the state of the node of the circuit under test is connected to the power supply.

[0098] It can be understood that in this embodiment, the selection module 50 as in the above embodiment can also be set.

[0099] In this application, the detection period mentioned in any of the above embodiments can be at least 4 clock signals. For example, the detection period is 4 clock signals, 5 clock signals or 6 clock signals.

[0100] In this embodiment, by using the conduction and cutoff of the first transistor Q1 and the second transistor Q2, an electrical signal is provided to the circuit node to be measured. Then, the electrical signal is detected by using the serially connected flip-flops in the detection module 30, and a corresponding digital signal is output. The digital signal is used to characterize the state of the circuit node to be measured, and the state includes the power supply connection state, the ground connection state, or the floating state, thereby solving the problem that the floating state of the circuit node cannot be detected. Further, the flip-flop as a digital circuit has a small device type, which can make the potential detection device more miniaturized. Further, using a digital circuit can also improve the detection speed. Further, the first transistor Q1 is directly coupled to the power supply terminal, without coupling to the power supply terminal through a current source as in the related art, which can reduce the use of electronic components and save costs.

[0101] Referring to Figure 6 , Figure 6 FIG. is a schematic structural diagram of an embodiment of the potential detection device provided by the present application. The potential detection device 1000 includes a potential detection circuit 100. Among them, the potential detection circuit 100 is the potential detection circuit 100 in any of the above embodiments.

[0102] In summary, for the potential detection circuit 100 and the potential detection device 1000 provided by the present application, by using the conduction and cutoff of the pull-up module 10 and the pull-down module 20 during the detection period, and then using the serially connected flip-flops in the detection module 30 to output a corresponding digital signal to form a detection signal after at least one detection period, the detection signal is used to characterize the power supply connection state, the ground connection state, or the floating state of the circuit node to be measured, thereby solving the problem that the floating state of the circuit node cannot be detected. Further, the flip-flop as a digital circuit has a small device type, which can make the potential detection device more miniaturized. Further, using a digital circuit can also improve the detection speed.

[0103] When the embodiments of the present application are implemented in the form of software function units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor to execute all or part of the steps of the methods described in various embodiments of the present application. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical discs that can store program codes.

[0104] The above are only the embodiments of the present application, and do not thus limit the patent scope of the present application. Any equivalent structural or equivalent process transformations made according to the content of the specification and drawings of the present application, or directly or indirectly applied in other related technical fields, are similarly included within the patent protection scope of the present application.

Claims

1. A potential detection circuit, characterized in that: The potential detection circuit comprises: A pull-up module, wherein a first end of the pull-up module is coupled to a power supply end, and a second end of the pull-up module is used to couple to a node of a circuit under test; A pull-down module, wherein a first end of the pull-down module is coupled to the circuit node under test, and a second end of the pull-down module is coupled to a reference ground; A detection module, the detection module comprising at least two triggers connected in series, wherein a first trigger of the at least two triggers connected in series is coupled to the circuit node under test; The detection module is configured to have a detection cycle and is used to output a detection signal after at least one detection cycle, wherein the detection signal is used to characterize the state of the circuit node under test, wherein the state includes a power supply state, a grounded state or a floating state; and the detection signal includes at least two digital signals output by the at least two triggers connected in series.

2. The potential detection circuit according to claim 1, characterized in that: The detection module includes a first trigger and a second trigger, the first trigger is coupled to the circuit node under test, and the second trigger is connected in series with the first trigger; During the detection period, the pull-up module is turned on and off in response to the first control signal; after the detection period, the second trigger outputs a corresponding digital signal; During the detection period, the pull-down module is turned on and off in response to the second control signal; after the detection period, the first trigger outputs a corresponding digital signal; Wherein, the pull-up module and the pull-down module are not turned on at the same time.

3. The potential detection circuit according to claim 1, characterized in that: The detection module includes a first trigger and a second trigger, the first trigger is coupled to the circuit node under test, and the second trigger is connected in series with the first trigger; During the detection period, the pull-down module is turned on and off in response to the first control signal; after the detection period, the second trigger outputs a corresponding digital signal; During the detection period, the pull-up module is turned on and off in response to the second control signal; after the detection period, the first trigger outputs a corresponding digital signal; Wherein, the pull-up module and the pull-down module are not turned on at the same time.

4. The potential detection circuit according to claim 1, characterized in that: The potential detection circuit further comprises: A control module is coupled to the pull-up module and the pull-down module, and is used to control the pull-up module and the pull-down module to be turned on or off respectively.

5. The potential detection circuit according to claim 1, characterized in that: The pull-up module includes a first transistor, a first end of the first transistor is coupled to the power supply end, and a second end of the first transistor is used to couple to the circuit node under test.

6. The potential detection circuit according to claim 1, characterized in that: The pull-down module includes a second transistor, a first terminal of the second transistor is coupled to the circuit node under test, and a second terminal of the second transistor is coupled to a reference ground.

7. The potential detection circuit according to claim 2 or 3, characterized in that: The on-time of the pull-up module is greater than the first time length; wherein the first time length is the ratio between the product of the capacitance of the circuit node under test and the voltage at the power supply terminal and the on-current when the pull-up module is turned on; The on-time of the pull-down module is greater than the second time; wherein the second time is the ratio of the product of the capacitance of the circuit node under test and the power supply terminal voltage to the on-current when the pull-down module is turned on.

8. The potential detection circuit according to claim 1, characterized in that: The detection module includes a first D flip-flop and a second D flip-flop; the data input terminal of the first D flip-flop is coupled to the circuit node under test, and the data output terminal of the first D flip-flop is coupled to the data input terminal of the second D flip-flop; wherein the digital signals output by the data output terminal of the first D flip-flop and the data output terminal of the second D flip-flop are used to characterize the state of the circuit node under test.

9. The potential detection circuit according to claim 1, characterized in that: The potential detection circuit further comprises: A selection module, wherein the selection module includes at least two input terminals, each of which is configured to be coupled to a circuit node under test. The selection module selects the corresponding target input terminal and the output terminal to be connected in response to a control signal, so that the circuit node under test coupled to the target input terminal is connected to the second terminal of the pull-up module.

10. A potential detection device, characterized in that: The method comprises a potential detection circuit as described in any one of claims 1 to 9.

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