Phase sequence measuring circuit

Abstract

The utility model relates to a phase sequence measuring circuit, which comprises an input circuit, an induction circuit, a phase inverter U2A, a phase inverter U2B, a phase inverter U2C, a D-type trigger U1A, a D-type trigger U1B, a phase sequence indicating circuit and a phase sequence measuring switch, three-phase power needing to be measured is obtained through the input circuit, the phase inverter U2A, the phase inverter U2B, the induction circuit and the phase inverter U2C receive signals of the input circuit, and the phase sequence indicating circuit and the phase sequence measuring switch are connected with the input circuit. The phase sequence measuring circuit is characterized in that the phase sequence measuring circuit is used for measuring the phase sequence of the three-phase power supply, the phase sequence is processed by the phase inverter and then is output by branches, and the D-type trigger U1A and the D-type trigger U1B receive signals processed by the phase inverter and control the output end to output a high level or a low level according to clock signals. Compared with a traditional manual measurement method, the method has the practical advantages of simple and efficient circuit, automatic triggering and recognition, visual LED indication, high reliability and stability, reduction of operation complexity, high expansibility and the like.

Description

Technical Field

[0001] The utility model relates to a phase sequence measurement circuit, belonging to the technical field of electrical measurement. Background Art

[0002] At present, for the measurement of three-phase power phase sequence, common measuring instruments for three-phase power phase sequence all have three test terminals. For example, the utility model patent with the publication number CN203929901U discloses a three-phase power phase sequence measurement circuit with three measuring probes. The circuit includes three measuring probes, a phase sequence indicator light, and several electronic components; the first measuring probe is connected to one end of a capacitor, the other end of the capacitor is connected to a first resistor, the other end of the first resistor is connected to the second measuring probe, and at the same time, the other end of the capacitor is also connected to one end of a second resistor, and the other end of the second resistor is connected to the third measuring probe through a third resistor, and the phase sequence indicator light is connected in parallel at both ends of the second resistor; this utility model design has a relatively low cost, does not require external power supply, and can display the phase sequence of the electric phase, greatly simplifying the complexity of the traditional phase sequence detection circuit;

[0003] This design in the above solution requires the user to connect the test terminals to the three phase lines one by one during phase sequence detection, which is not only cumbersome but also particularly inconvenient in actual operation; this connection method not only takes time but also increases the risk of operation errors, affecting the measurement efficiency and accuracy. Summary of the Utility Model

[0004] In order to solve the problems existing in the above-mentioned prior art, the utility model proposes a phase sequence measurement circuit.

[0005] The technical solution of the utility model is as follows:

[0006] The utility model provides a phase sequence measurement circuit, including an input circuit, an induction circuit, an inverter U2A, an inverter U2B, an inverter U2C, a D-type flip-flop U1A, a D-type flip-flop U1B, a phase sequence indication circuit, and a phase sequence measurement switch;

[0007] The input end of the input circuit is connected to the three-phase power to be measured, and its output end is connected to the input end of the inverter U2A. The output end of the inverter U2A is respectively connected to the clock terminal CLK of the D-type flip-flop U1A and the input end of the inverter U2B, and the output end of the inverter U2B is connected to the clock terminal CLK of the D-type flip-flop U1B;

[0008] One end of the phase sequence indication circuit is connected to the D-type flip-flop U1A, and the other end of the phase sequence indication circuit is connected to the D-type flip-flop U1B, which is used to indicate the result of the phase sequence measurement;

[0009] The output end of the induction circuit is connected to the input end of the inverter U2C, and is used to sense the signal of the input circuit and output it to the inverter U2C;

[0010] The output end of the inverter U2C is respectively connected to the trigger ends D of the D-type flip-flop U1A and the D-type flip-flop U1B;

[0011] The output ends Q of the D-type flip-flop U1A and the D-type flip-flop U1B are respectively connected to the phase sequence indication circuit;

[0012] One end of the phase sequence measurement switch is respectively connected to the reset ends R of the D-type flip-flop U1A and the D-type flip-flop U1B, and the other end is grounded.

[0013] As a preferred embodiment of the present invention, the input circuit includes a resistor R1, a resistor R4, a capacitor C1, a test pen L1, and a test pen L2;

[0014] One end of the test pen L1 is connected to the a-phase of the three-phase power to be measured, the other end is connected to the resistor R1, the other end of the resistor R1 is connected to the capacitor C1, and the other end of the capacitor C1 is connected to the input end of the inverter U2A;

[0015] One end of the test pen L2 is connected to the b-phase of the three-phase power to be measured, the other end is connected to one end of the resistor R4, and the other end of the resistor R4 is connected to the positive power supply.

[0016] As a preferred embodiment of the present invention, the induction circuit includes a wire N, a resistor R2, and a resistor R3;

[0017] One end of the wire N is respectively connected to one ends of the resistor R2 and the resistor R3, the other end is suspended, the end of the resistor R2 not connected to the wire N is connected to the input end of the inverter U2C, and the end of the resistor R3 not connected to the wire N is grounded;

[0018] There is a stray capacitance between the wire N and the input end of the test pen L2, and the induction circuit obtains the b-phase signal of the three-phase power obtained by the test pen L2 through the stray capacitance.

[0019] As a preferred embodiment of the present invention, one end pin of the inverter U2A is connected to the positive power supply, and the other end pin is grounded.

[0020] As a preferred embodiment of the present invention, the set end S of the D-type flip-flop U1A is grounded, the reset end R is connected to the resistor R5, and the other end of the resistor R5 is connected to the positive power supply;

[0021] The set end S of the D-type flip-flop U1B is grounded, the reset end R is connected to the resistor R5, and the other end of the resistor R5 is connected to the positive power supply.

[0022] As a preferred embodiment of the present utility model, the phase sequence indicating circuit includes a resistor R6, a forward-phase indicating lamp LED1, and a reverse-phase indicating lamp LED2;

[0023] One end of the forward-phase indicating lamp LED1 of the phase sequence measuring circuit is connected to the resistor R6, the other end of the resistor R6 is connected to the output terminal Q of the D-type flip-flop U1B, and the other end of the forward-phase indicating lamp LED1 is connected to the output terminal Q of the D-type flip-flop U1A;

[0024] One end of the reverse-phase indicating lamp LED2 of the phase sequence measuring circuit is connected to the resistor R6, the other end of the resistor R6 is connected to the output terminal Q of the D-type flip-flop U1B, and the other end of the reverse-phase indicating lamp LED2 is connected to the output terminal Q of the D-type flip-flop U1A.

[0025] As a preferred embodiment of the present utility model, a CD4013 dual D flip-flop is used as the D-type flip-flop U1A and the D-type flip-flop U1B, and inverters U1A, U1B, and U1C use a hex inverter of model CD4069.

[0026] Compared with the prior art, the present utility model has the following beneficial effects:

[0027] 1. By using a CD4013 dual D flip-flop for digital processing, the present utility model makes the result of phase sequence measurement more accurate and reliable; digital circuits are not easily affected by environmental factors such as temperature and humidity changes, thus ensuring the stability and consistency of measurement.

[0028] 2. By using fewer components (such as resistors, capacitors, inverters, and dual D flip-flops), the present utility model constructs a phase sequence measuring circuit, realizing the simplification of the circuit; this reduces costs and at the same time reduces the possible fault points introduced by complex circuits.

[0029] 3. By directly displaying the phase sequence result through an LED indicator (such as the forward-phase indicating lamp LED1), the present utility model makes the measurement result more intuitive; operators can quickly judge whether the phase sequence is correct without relying on complex instruments or analysis.

[0030] 4. By using a D-type flip-flop, the present utility model can quickly respond to changes in input signals, thus quickly judging the phase sequence. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is the circuit schematic diagram of the embodiment of the present utility model;

[0032] Figure 2 is the module schematic diagram of the embodiment of the present utility model;

[0033] Figure 3 is the working waveform diagram of the D-type flip-flop of the embodiment of the present utility model;

[0034] Figure 4 This is the waveform diagram of the D-type flip-flop in the embodiment of the present utility model. Detailed implementation manners

[0035] Next, the technical solutions in the embodiments of the present utility model will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present utility model without making creative efforts shall fall within the protection scope of the present utility model.

[0036] It should be understood that the step numbers used in the text are only for convenient description and do not limit the execution order of the steps.

[0037] It should be understood that the terms used in the specification of the present utility model are only for the purpose of describing specific embodiments and are not intended to limit the present utility model. As used in the specification of the present utility model and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include the plural forms.

[0038] The terms "comprising" and "including" indicate the presence of the described features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their combinations.

[0039] The term " / and / " refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0040] Embodiment 1:

[0041] Refer to Figure 1-2 , a phase sequence measurement circuit, including an input circuit, an induction circuit, an inverter U2A, an inverter U2B, an inverter U2C, a D-type flip-flop U1A, a D-type flip-flop U1B, a phase sequence indication circuit and a phase sequence measurement switch;

[0042] The input end of the input circuit is connected to the three-phase power to be measured, and its output end is connected to the input end of the inverter U2A. The output end of the inverter U2A is respectively connected to the clock terminal CLK of the D-type flip-flop U1A and the input end of the inverter U2B. The output end of the inverter U2B is connected to the clock terminal CLK of the D-type flip-flop U1B;

[0043] One end of the phase sequence indication circuit is connected to the D-type flip-flop U1A, and the other end of the phase sequence indication circuit is connected to the D-type flip-flop U1B, and is used to indicate the result of the phase sequence measurement;

[0044] It is connected to the input terminal of the inverting amplifier U2C at the output terminal of the induction circuit, and is used to sense the signal of the input circuit and output it to the inverting amplifier U2C;

[0045] The output terminal of the inverting amplifier U2C is respectively connected to the trigger terminals D of the class-D flip-flops U1A and U1B;

[0046] The output terminals Q of the class-D flip-flops U1A and U1B are respectively connected to the phase sequence indicating circuit;

[0047] One end of the phase sequence measurement switch is respectively connected to the reset terminals R of the class-D flip-flops U1A and U1B, and the other end is grounded.

[0048] As a preferred embodiment of the present invention, the input circuit includes a resistor R1, a resistor R4, a capacitor C1, a test pen L1, and a test pen L2;

[0049] One end of the test pen L1 is connected to the a-phase of the three-phase power supply to be measured, the other end is connected to the resistor R1, the other end of the resistor R1 is connected to the capacitor C1, and the other end of the capacitor C1 is connected to the input terminal of the inverting amplifier U2A;

[0050] One end of the test pen L2 is connected to the b-phase of the three-phase power supply to be measured, the other end is connected to one end of the resistor R4, and the other end of the resistor R4 is connected to the positive pole of the power supply.

[0051] As a preferred embodiment of the present invention, the induction circuit includes a wire N, a resistor R2, and a resistor R3;

[0052] One end of the wire N is respectively connected to one ends of the resistor R2 and the resistor R3, the other end is suspended, the end of the resistor R2 not connected to the wire N is connected to the input terminal of the inverting amplifier U2C, and the end of the resistor R3 not connected to the wire N is grounded;

[0053] There is a stray capacitance between the wire N and the input terminal of the test pen L2, and the induction circuit obtains the b-phase signal of the three-phase power supply obtained by the test pen L2 through the stray capacitance.

[0054] As a preferred embodiment of the present invention, one end pin of the inverting amplifier U2A is connected to the positive pole of the power supply, and the other end pin is grounded, and is used to receive the input circuit signal, invert the signal, and output it after shaping.

[0055] As a preferred embodiment of the present invention, the set terminal S of the class-D flip-flop U1A is grounded, the reset terminal R is connected to the resistor R5, and the other end of the resistor R5 is connected to the positive pole of the power supply;

[0056] The set terminal S of the D-type flip-flop U1B is grounded, the reset terminal R is connected to the resistor R5, and the other end of the resistor R5 is connected to the positive pole of the power supply; the D-type flip-flop U1A and the D-type flip-flop U1B drive the phase sequence indicating circuit according to the input signals of the clock terminal CLK and the trigger terminal D.

[0057] As a preferred embodiment of the present invention, the phase sequence indicating circuit includes a resistor R6, a forward-phase indicating lamp LED1 and a reverse-phase indicating lamp LED2;

[0058] One end of the forward-phase indicating lamp LED1 of the phase sequence measuring circuit is connected to the resistor R6, the other end of the resistor R6 is connected to the output terminal Q of the D-type flip-flop U1B, and the other end of the forward-phase indicating lamp LED1 is connected to the output terminal Q of the D-type flip-flop U1A, which is used to indicate the forward phase of the measured phase sequence;

[0059] One end of the reverse-phase indicating lamp LED2 of the phase sequence measuring circuit is connected to the resistor R6, the other end of the resistor R6 is connected to the output terminal Q of the D-type flip-flop U1B, and the other end of the reverse-phase indicating lamp LED2 is connected to the output terminal Q of the D-type flip-flop U1A, which is used to indicate the reverse phase of the measured phase sequence.

[0060] As a preferred embodiment of the present invention, the CD4013 dual D flip-flop is used as the D-type flip-flop U1A and the D-type flip-flop U1B, and the models of the inverters U1A, U1B, and U1C are CD4069 hex inverters.

[0061] Embodiment 2:

[0062] A three-phase power phase sequence measuring circuit, and its specific operation method is as follows:

[0063] When in standby, the set terminal S of the D-type flip-flop U1A and the D-type flip-flop U1B is grounded, the reset terminal R is connected to the positive pole of the power supply through the resistor R5. It can be obtained from the truth table of CD4013 (Table 1) that it works in the reset state. The output terminal Q of the D-type flip-flop U1A and the output terminal Q of the D-type flip-flop U1B both output low levels, and the forward-phase indicating lamp LED1 and the reverse-phase indicating lamp LED2 do not light up;

[0064] Table 1 CD4013 truth table

[0065]

[0066] When measuring the phase sequence, the test pen L1 is connected to the a-phase of the three-phase power to be measured, the test pen L2 is connected to the b-phase of the three-phase power to be measured (the b-phase lags behind the a-phase by 120°), the phase sequence measuring switch K1 is turned on, and the reset terminal R of the D-type flip-flop U1A and the D-type flip-flop U1B is connected to the power ground. It can be obtained from the truth table of CD4013 that it works in the trigger state;

[0067] The pen L2 is connected to the positive pole of the power supply via the resistor R4. Since the wire N of the induction circuit is close to the input end of the pen L2, there is a stray capacitance between the wire N of the induction circuit and the input end of the pen L2. The b-phase measurement signal of the pen L2 is coupled to the wire N of the induction circuit through the stray capacitance, and then reaches the input end of the inverter U2C via the resistor R2. The resistor R3 can adjust the intensity of the induction signal. After being inverted and shaped by the inverter U2C, a square wave is output to the trigger terminals D of the D-type flip-flops U1A and U1B( Figure 3 of waveform a).

[0068] The a-phase signal of the pen L1 reaches the input end of the inverter U2A via the resistor R1 and the capacitor C1. The square wave output after being inverted and shaped by the inverter U2A is divided into two paths. One path reaches the clock terminal CLK of the D-type flip-flop U1A Figure 3 of waveform b), and the other path reaches the input end of the inverter U2B. After being inverted by the inverter U2B, it is transmitted from the output end of the inverter U2B to the clock terminal CLK of the D-type flip-flop U1B Figure 3 of waveform c). It can be obtained from the truth table of CD4013 (Table 1) that the rising edge trigger of the clock terminal CLK is effective. The output terminal Q of the D-type flip-flop U1A outputs a high level, and the output terminal Q of the D-type flip-flop U1B outputs a low level. The current flows from the output terminal Q of the D-type flip-flop U1A through the in-phase indicator light LED1, R6 to the output terminal Q of the D-type flip-flop U1B, and the in-phase indicator light LED1 lights up.

[0069] If the pen L1 is connected to the b-phase of the three-phase power supply and the pen L2 is connected to the a-phase of the three-phase power supply, through the induction circuit, after each inverter, the signals are input to the clock terminals CLK and trigger terminals D of the D-type flip-flops U1A and U1B Figure 4 ), it can be obtained from the truth table of CD4013 (Table 1) that the rising edge trigger of the clock terminal CLK is effective. The output terminal Q of the D-type flip-flop U1A outputs a low level, and the output terminal Q of the D-type flip-flop U1B outputs a high level. The current flows from the output terminal Q of the D-type flip-flop U1B through R6, the reverse-phase indicator light LED2 to the output terminal Q of the D-type flip-flop U1A, and the reverse-phase indicator light LED2 lights up.

[0070] In the embodiments of the present application, "at least one" means one or more, and "a plurality" means two or more. "And / or" describes the relationship between related objects and indicates that there can be three relationships. For example, A and / or B can represent the cases where A exists alone, A and B exist simultaneously, and B exists alone. Here, A and B can be singular or plural. The character " / " generally indicates that the related objects before and after are in an "or" relationship. "At least one of the following" and its similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, and c can represent: a, b, c, a and b, a and c, b and c, or a, b, and c, where a, b, and c can be single or multiple.

[0071] The above are only the embodiments of the present utility model, and do not limit the patent scope of the present utility model accordingly. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of the present utility model, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of the present utility model.

Claims

1. A phase sequence measurement circuit, characterized in that: It includes an input circuit, a sensing circuit, an inverter U2A, an inverter U2B, an inverter U2C, a D-type trigger U1A, a D-type trigger U1B, a phase sequence indication circuit and a phase sequence measurement switch; The input end of the input circuit is electrically connected to the three-phase to be tested, and the output end thereof is connected to the input end of the inverter U2A. The output end of the inverter U2A is respectively connected to the clock end CLK of the D-type trigger U1A and the input end of the inverter U2B. The output end of the inverter U2B is connected to the clock end CLK of the D-type trigger U1B. One end of the phase sequence indication circuit is connected to the D-type trigger U1A, and the other end of the phase sequence indication circuit is connected to the D-type trigger U1B, for indicating the result of phase sequence measurement; The output end of the sensing circuit is connected to the input end of the inverter U2C, and is used to sense the signal of the input circuit probe L2 and output it to the inverter U2C; The output end of the inverter U2C is connected to the trigger end D of the D-type flip-flop U1A and the D-type flip-flop U1B respectively; The output terminals Q of the D-type trigger U1A and the D-type trigger U1B are respectively connected to the phase sequence indication circuit; One end of the phase sequence measurement switch is respectively connected to the reset end R of the D-type trigger U1A and the D-type trigger U1B, and the other end is grounded.

2. A phase sequence measurement circuit according to claim 1, characterized in that: The input circuit includes a resistor R1, a resistor R4, a capacitor C1, a test lead L1 and a test lead L2; One end of the test lead L1 is connected to phase a of the three-phase electricity to be tested, and the other end is connected to the resistor R1, the other end of the resistor R1 is connected to the capacitor C1, and the other end of the capacitor C1 is connected to the input end of the inverter U2A; One end of the test lead L2 is connected to phase b of the three-phase electricity to be tested, and the other end is connected to one end of the resistor R4, and the other end of the resistor R4 is connected to the positive electrode of the power supply.

3. A phase sequence measurement circuit according to claim 1, characterized in that: The induction circuit includes a wire N, a resistor R2 and a resistor R3; One end of the wire N is connected to one end of the resistor R2 and the resistor R3 respectively, and the other end is suspended, the end of the resistor R2 not connected to the wire N is connected to the input end of the inverter U2C, and the end of the resistor R3 not connected to the wire N is grounded; There is stray capacitance between the wire N and the input end of the test lead L2, and the induction circuit obtains the b-phase signal of the three-phase electricity obtained by the test lead L2 through the stray capacitance.

4. A phase sequence measurement circuit according to claim 1, characterized in that: One end pin of the inverter U2A is connected to the positive pole of the power supply, and the other end pin is grounded.

5. A phase sequence measurement circuit according to claim 1, characterized in that: The set terminal S of the D-type flip-flop U1A is grounded, the reset terminal R is connected to the resistor R5, and the other end of the resistor R5 is connected to the positive electrode of the power supply; The set terminal S of the D-type flip-flop U1B is grounded, the reset terminal R is connected to the resistor R5, and the other end of the resistor R5 is connected to the positive electrode of the power supply.

6. A phase sequence measurement circuit according to claim 1, characterized in that: The phase sequence indication circuit includes a resistor R6, a forward phase indicator LED1 and a reverse phase indicator LED2; One end of the forward phase indicator LED1 of the phase sequence measurement circuit is connected to the resistor R6, the other end of the resistor R6 is connected to the output end Q of the D-type trigger U1B, and the other end of the forward phase indicator LED1 is connected to the output end Q of the D-type trigger U1A; One end of the reverse phase indicator LED2 of the phase sequence measurement circuit is connected to the resistor R6, the other end of the resistor R6 is connected to the output end Q of the D-type trigger U1B, and the other end of the reverse phase indicator LED2 is connected to the output end Q of the D-type trigger U1A.

7. A phase sequence measurement circuit according to claim 1, characterized in that: A CD4013 dual D flip-flop is used as the D-type flip-flop U1A and the D-type flip-flop U1B, and the inverter U1A, the inverter U1B, and the inverter U1C use a six-inverter model of CD4069.

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