10W co-location filter

Abstract

The utility model provides a 10W co-location filter. A digital control circuit is used for storing parameters of tuning control level; the switch driving circuit is used for outputting a control level to the switched capacitor array according to the storage parameters; the switched capacitor array is used for tuning the working frequency of the loop by switching on or switching off the corresponding binary capacitors; and the tuning inductor is used for tuning the working frequency of the switched capacitor array and then outputting the working frequency through the port, or is used for tuning a frequency signal received by the port and then sending the frequency signal to the switched capacitor array. According to the utility model, a preselection filter is arranged between an antenna and a frequency mixer in a receiving system, the preselection filter works at 30MHz-88MHz, the PIN tube is connected with the capacitor array, capacitors with different capacitance values are gated by utilizing the characteristic that the PIN tube is conducted at positive voltage and cut off at negative voltage, frequency hopping is realized, and the preselection filter has the advantages of high Q value, less energy loss, digitization and high sensitivity.

Description

Technical Field

[0001] The utility model relates to the field of radio frequency, in particular to a 10W co-located filter. Background Art

[0002] With the rapid development of modern wireless communication technology and the increasing demand for diversified communication methods, microwave filters with the advantages of low cost, high performance, miniaturization, and easy design have received more and more attention. One of the most important anti-jamming means in military communication is to use frequency hopping technology in wireless communication. If a band-pass filter with a suitable center frequency and capable of quickly tracking frequency hopping changes is used in the system, the anti-jamming performance of the system can be significantly improved.

[0003] Currently, in the receiving system, the preselection filter located between the antenna and the mixer has high energy loss, low out-of-band suppression, and poor anti-jamming ability. Summary of the Invention

[0004] In order to solve the problems existing in the background art, the utility model provides a 10W co-located filter.

[0005] A 10W co-located filter includes

[0006] A digital control circuit configured to connect to a switch driving circuit, for storing parameters of a tuning control level, and outputting a control level to the switch driving circuit according to the stored parameters;

[0007] A switch driving circuit configured to connect to the digital control circuit and a switched capacitor array, for outputting a 200V or -3.3V level to the switched capacitor array according to the control level of the digital control circuit;

[0008] A switched capacitor array configured to connect to the switch driving circuit and a tuning inductor, for tuning the operating frequency of the loop by connecting or disconnecting corresponding binary capacitors;

[0009] A tuning inductor configured to connect to the switched capacitor array and an input / output port, for performing LC tuning and frequency selection with the switched capacitor array, filtering the frequency signal received at the input port, and sending it to the output port.

[0010] Based on the above, the switch driving circuit includes a first comparison control circuit, a second comparison control circuit, and a switching output circuit. The input ends of the first comparison control circuit and the second comparison control circuit are respectively connected to the digital control circuit and used for receiving digital signal instructions. The first comparison control circuit and the second comparison control circuit are respectively connected to the switching output circuit, and the output end of the switching output circuit is connected to the switched capacitor array.

[0011] Based on the above, there are two groups of switched-capacitor arrays. Each group of switched-capacitor arrays includes 8-way capacitor arrays, and each capacitor is connected to an output terminal of the switch driving circuit through a PIN diode.

[0012] Based on the above, one group of switched-capacitor arrays is sequentially connected to an input / output port through a tuning inductor and an auxiliary inductor coil.

[0013] Based on the above, the Q value of the tuning inductor is at least 250.

[0014] Based on the above, the digital control circuit includes an AT24C32D memory chip, which stores 600 hexadecimal level parameters, and each level parameter corresponds to a frequency parameter of a 10W co-located filter in the range of 30MHz to 88MHz.

[0015] The present utility model has substantial features and progress compared with the prior art. Specifically, the present utility model is located between the antenna and the mixer in the receiving system as a preselection filter, with a power of 10W, operating at 30MHz to 88MHz. The PIN diodes are connected to the capacitor arrays. Utilizing the characteristics of the PIN diodes that conduct under positive voltage and cut off under negative voltage, different capacitance values of capacitors are selected to achieve frequency hopping. It has the advantages of high Q value, less energy consumption, digitalization, and high sensitivity. This co-located filter is sensitive to frequency changes and can quickly track narrowband bandpass filters, effectively improving the signal-to-noise ratio of the receiver and making the frequency hopping communication device more reliable and efficient. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a structural schematic block diagram of the present utility model (in the figure, the parabolic shape with an arrow is the tuning inductor).

[0017] Figure 2 is the circuit schematic diagram of the switched-capacitor array of the present utility model.

[0018] Figure 3 is the circuit schematic diagram of the switch driving circuit of the present utility model.

[0019] Figure 4 is the circuit schematic diagram of the digital control circuit of the present utility model. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0020] Hereinafter, the technical solutions in the embodiments of the present utility model will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all of the embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present utility model.

[0021] As Figures 1 - 4As shown in the figure, a 10W co-located filter includes a tuning inductor, a switched capacitor array, a switch driving circuit, and a digital control circuit. The tuning inductor I75 is wound with a copper wire of silver-copper alloy for the loop coil, and its Q value (quality factor) is above 250. The auxiliary inductor coils L9 and L10 are wound with silver-plated copper wires, and their Q values (quality factors) are above 80. They have little influence on the Q value of the resonant circuit. The co-located filter is matched with the front and rear stages in the circuit with a 50Ω impedance. Critical coupling is used between the primary and secondary to obtain the flattest passband characteristic and the best stopband attenuation. Since the loop inductor coil has only 4 turns, it is difficult to correctly position the tap for coupling and matching with the signal source load. Therefore, the auxiliary inductor coils L9 and L10 are needed to achieve the matching, and the best state can be achieved by finely tuning the auxiliary inductor coils L9 and L10.

[0022] The switched capacitor array has two groups. Each group of the switched capacitor array is connected to an input / output port through a tuning inductor I75 and an auxiliary inductor coil respectively. Each group of the switched capacitor array includes 8-way capacitor arrays. The access or disconnection of the binary capacitors is realized by controlling the conduction or disconnection of the PIN diodes connected thereto. When the filter is tuned, the loop is tuned to the operating frequency by connecting or disconnecting the corresponding binary capacitors. The capacitor array uses Darlicon high-Q capacitors (DLC10B series capacitors) with a withstand voltage of 500V, and the PIN diodes use MA4P506-1072T with a withstand voltage of 500V. The -3.3V and 200V voltages provided by the switch driving circuit control the conduction and cut-off of the PIN diodes.

[0023] In this embodiment, there are also 8 groups corresponding to the switch driving circuit. Each group of the switch driving circuit has 2 output terminals, which respectively correspond to 2-way capacitor arrays in the two groups of the switched capacitor array. Figure 3 Only 2 groups of the switch driving circuit are shown. Each group of the switch driving circuit is controlled by a binary digital signal, and the binary digital signal is provided by the digital control circuit for the fast switching between the 200V high voltage IN_PWR and the -3.3V low voltage. The switching transistors V1, V2, and V20 all use field effect transistors STN1NK80 with a withstand voltage of 800V. Through a +3.3V level switch signal, the output switching between the two voltage signals of +200V voltage or -3.3V voltage is quickly realized. When the input signal IN_T1 is at +3.3V level, OUT_T1 and OUT_T11 are at -3.3V; when the switch signal IN_T1 is at 0V level, OUT_T1 and OUT_T11 are at 200V. The working principles of the other 7-way switch driving circuits are the same as the above.

[0024] The digital control circuit includes a storage chip D2, model number AT24C32D. The storage chip D2 is a serial interface storage chip with a storage capacity of 32Kb. T1_TX - T8_TX are used to connect to the external FPGA in actual use to read the parameters of the storage chip D2. The storage chip D2 is used to store 600 hexadecimal level parameters, and each parameter corresponds to a frequency parameter of the 10W co-site filter in the range of 30MHz to 88MHz. The frequency interval between adjacent parameters for the filter is 0.1MHz, realizing full-band filtering switching of the 10W co-site filter in the frequency band of 30MHz to 88MHz. After the external FPGA reads the parameters of the storage chip D2, it forms 8-bit binary digital control signals T1 - T8, and outputs a switching level signal IN_T1 - IN_T8 of +3.3V through a latch chip D1 (model number SN74AHC573PW).

[0025] In actual use, according to the external serial port data signal, the storage parameters corresponding to the frequency in the storage chip D2 are read to form 8-bit binary digital control signals T1 - T8. The 8-bit binary digital control signals drive and output IN_T1 - IN_T8 through SN74AHC573PW. Through the 8-bit binary digital control signals, the on and off of two voltage signals, +200V voltage and -3.3V voltage, of the 8-way switch drive circuit ( Figure 3 being two of the switch drive circuits) are quickly realized. When the input signal IN_T1 is at 3.3V level, the comparators respectively output high levels, the field effect transistors V1 and V20 are respectively turned on, the field effect transistor V2 is turned off, OUT_T1 and OUT_T11 are at -3.3V, and the switch drive circuit outputs -3.3V; when the input signal IN_T1 is at 0V level, the comparators respectively output low levels, the field effect transistors V1 and V20 are respectively turned off, the field effect transistor V2 is turned on, OUT_T1 and OUT_T11 are at +200V, and the switch drive circuit outputs +200V.

[0026] The on and off of the PIN diode are controlled by the -3.3V and 200V voltages provided by the switch drive circuit. The resonant capacitors on the conduction path of the conducting PIN diode participate in resonance and cooperate with the tuning inductor to form the corresponding tuning frequency. The switch capacitor array has a total of 8 capacitor arrays. The connection or disconnection of the binary capacitors is achieved by controlling the conduction or disconnection of the PIN diodes connected to them. When the filter is tuned, the loop is tuned to the required operating frequency by connecting or disconnecting the corresponding number of binary capacitors. When the PIN diode is conducting, the resonant capacitor on this channel participates in resonance and cooperates with the tuning inductor to form the corresponding tuning frequency. The calculation formula for the resonant frequency is (L is the inductance of the tuning inductor, and C is the capacitance value participating in resonance). XS1 and XS2 are respectively the RF input / output ports of the 10W co-located filter, one as the input port and the other as the output port at the same time. The input signal is tuned and filtered by the switched capacitor array and then output from the output port.

[0027] For those skilled in the art, it is obvious that the present utility model is not limited to the details of the above exemplary embodiments, and the present utility model can be implemented in other specific forms without departing from the spirit or basic characteristics of the present utility model. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present utility model is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be embraced within the present utility model. Any reference signs in the claims should not be regarded as limiting the claims involved.

Claims

1. A 10W co-site filter, characterized in that: include a digital control circuit configured to be connected to the switch drive circuit, to store parameters for tuning the control level, and to output the control level to the switch drive circuit according to the stored parameters; A switch driving circuit, configured to connect the digital control circuit and the switch capacitor array, and to output a 200V or -3.3V level to the switch capacitor array according to a control level of the digital control circuit; a switched capacitor array configured to connect the switch driving circuit and the tuning inductor, and used to tune the operating frequency of the loop by switching on or off the corresponding binary capacitors; The tuning inductor is configured to connect the switch capacitor array and the input / output port, and is used to perform LC tuning and frequency selection with the switch capacitor array, and filter the frequency signal received at the input port and send it to the output port.

2. The 10W co-site filter according to claim 1, characterized in that: The switch driving circuit includes a first comparison control circuit, a second comparison control circuit and a switching output circuit. The input ends of the first comparison control circuit and the second comparison control circuit are respectively connected to the digital control circuit and are used to receive digital signal instructions. The first comparison control circuit and the second comparison control circuit are respectively connected to the switching output circuit, and the output end of the switching output circuit is connected to the switch capacitor array.

3. The 10W co-site filter according to claim 1, characterized in that: There are two groups of switch capacitor arrays, each group of switch capacitor arrays includes 8-way capacitor arrays, and each capacitor is connected to an output end of the switch drive circuit through a PIN tube.

4. The 10W co-site filter according to claim 1, characterized in that: A set of switched capacitor arrays are connected to an input / output port in sequence through a tuning inductor and an auxiliary inductor coil.

5. The 10W co-site filter according to claim 1, characterized in that: The tuning inductor should have a Q value of at least 250.

6. The 10W co-site filter according to claim 5, characterized in that: The digital control circuit comprises an AT24C32D memory chip, which stores 600 hexadecimal level parameters, each of which corresponds to a frequency parameter of a 10W co-site filter in the range of 30MHz to 88MHz.

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