Power switch circuit, power amplifier and electronic equipment

Abstract

The embodiment of the utility model relates to the technical field of power supplies, and discloses a power switch circuit, a power amplifier and electronic equipment. The power switch circuit comprises a switch starting circuit, an upper tube switch circuit, a lower tube switch circuit, a switch switching circuit and a first voltage stabilizing circuit, the switch switching circuit is provided with a junction capacitor, the junction capacitor prompts the switch switching circuit to output a target power supply in a discharging state, and when the junction capacitor enters the discharging state, the first voltage stabilizing circuit outputs the target power supply. The junction capacitor, the lower tube switching circuit and the first voltage stabilizing circuit form a discharge loop, and the first voltage stabilizing circuit provides stable voltage for the lower tube switching circuit in the discharge loop. According to the embodiment of the invention, the first voltage stabilizing circuit is arranged on the discharge loop, and the first voltage stabilizing circuit provides a stable voltage for the lower tube switching circuit in the discharge loop, thereby preventing the voltage of the input power supply from being too large or the voltage fluctuation from being too large to damage related devices of the power supply switching circuit. And the capability of adapting to a wide voltage range and the switching rate of the power switch circuit can be improved.

Description

Technical Field

[0001] The embodiments of the present utility model relate to the technical field of power supplies, and particularly to a power switch circuit, a power amplifier, and an electronic device. Background Art

[0002] The power switch circuit can supply the input power to the radio frequency power amplifier to ensure the normal operation of the radio frequency power amplifier. However, the radio frequency power amplifier requires that the power switch circuit quickly switches the power supply to the radio frequency power amplifier, and the switching speed reaches the microsecond level to meet the application requirements of the radio frequency power amplifier. However, the voltage application range of the power switch circuit provided by the related technology is relatively narrow. When the input power fluctuates greatly, the input power is likely to damage the related devices of the power switch circuit. Summary of the Utility Model

[0003] In order to solve the above technical problems, the embodiments of the present utility model provide a power switch circuit, a power amplifier, and an electronic device, which are used to solve the technical problem that the voltage application range of the power switch circuit provided by the related technology is relatively narrow.

[0004] In a first aspect, an embodiment of the present application provides a power switch circuit, including:

[0005] A switch startup circuit, including a first node and a second node, is configured to respond to an enable signal and adjust a first voltage of the first node, wherein the second node is configured to be applied with a target power supply;

[0006] An upper transistor switch circuit is electrically connected between the first node and the second node and is configured to enter an upper transistor switch state in response to the first voltage;

[0007] A lower transistor switch circuit is electrically connected to the first node and is electrically connected to the upper transistor switch circuit at a preset series node, and is configured to enter a lower transistor switch state in response to the first voltage, and the lower transistor switch state is mutually exclusive with the upper transistor switch state;

[0008] A switch switching circuit is electrically connected between the second node and the series node. The switch switching circuit is configured with a junction capacitance and is configured to enter a discharge state or a charge state in response to the upper transistor switch state and the lower transistor switch state. The junction capacitance causes the switch switching circuit to output the target power supply in the discharge state;

[0009] A first voltage stabilizing circuit is electrically connected to the lower transistor switch circuit. When the junction capacitance enters the discharge state, the junction capacitance, the lower transistor switch circuit, and the first voltage stabilizing circuit form a discharge loop, and the first voltage stabilizing circuit provides a stable voltage for the lower transistor switch circuit in the discharge loop.

[0010] Optionally, the first voltage stabilizing circuit includes a first voltage stabilizing diode, the positive electrode of the first voltage stabilizing diode is grounded, and the negative electrode of the first voltage stabilizing diode is electrically connected to the lower transistor switching circuit.

[0011] Optionally, the switch startup circuit includes:

[0012] A startup control circuit, including a third node, for responding to the enable signal and adjusting the third voltage of the third node;

[0013] A switch trigger circuit, including the first node and the second node, electrically connected to the startup control circuit at the third node, for responding to the third voltage and adjusting the first voltage of the first node.

[0014] Optionally, the startup control circuit includes:

[0015] An enable input circuit, including the third node, for transmitting the enable signal;

[0016] An enable switch circuit, electrically connected to the enable input circuit at the third node, for responding to the enable signal and a control signal sent by an external device and adjusting the third voltage of the third node.

[0017] Optionally, the upper transistor switching circuit includes a first NPN transistor, the base of the first NPN transistor is electrically connected to the first node, the emitter is electrically connected to the series node, and the collector is applied with the target power supply.

[0018] Optionally, the lower transistor switching circuit includes a first PNP transistor, the base of the first PNP transistor is electrically connected to the first node, the emitter is electrically connected to the series node, and the collector is electrically connected to the first voltage stabilizing circuit.

[0019] Optionally, the switch switching circuit includes a PMOS transistor, the source of the PMOS transistor is applied with the target power supply, the gate is electrically connected to the series node, the drain is the output end of the target power supply, and the gate-source capacitance of the PMOS transistor is the junction capacitance.

[0020] Optionally, the power switch circuit further includes a second voltage stabilizing circuit, and the second voltage stabilizing circuit is electrically connected between the first node and the second node.

[0021] In a second aspect, an embodiment of the present application provides a power amplifier, including the above-mentioned power switch circuit.

[0022] In a third aspect, an embodiment of the present application provides an electronic device, including the above-mentioned power amplifier.

[0023] The beneficial effects of the power switch circuit provided by the embodiments of the present application are as follows: In the embodiments of the present application, a first voltage stabilizing circuit is provided on the discharge loop. The first voltage stabilizing circuit provides a stable voltage for the lower transistor switch circuit in the discharge loop, thereby preventing the relevant devices of the power switch circuit from being damaged due to excessive voltage or excessive voltage fluctuation of the input power supply, which is beneficial to improving the ability of the power switch circuit to adapt to a wide voltage range. In addition, the first voltage stabilizing circuit provides a stable voltage in the high-voltage state, which can avoid the instability problem of the switching state of the switch switching circuit caused by voltage fluctuation, and is beneficial to the reliable discharge of the switch switching circuit. At the same time, the first voltage stabilizing circuit has a fast voltage-current response characteristic, which can quickly respond to the voltage change of the switch switching circuit, thereby accelerating the switching rate of the switch switching circuit. Description of the Drawings

[0024] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not limit the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the drawings in the drawings do not constitute a proportional limitation.

[0025] Figure 1 Schematic diagram of the circuit structure of a power amplifier provided by an embodiment of the present utility model;

[0026] Figure 2 Schematic diagram of the circuit structure of a power switch circuit provided by an embodiment of the present utility model;

[0027] Figure 3 Schematic diagram of the circuit structure of a power switch circuit provided by another embodiment of the present utility model, wherein, Figure 3 The provided power switch circuit is on the basis of Figure 2 and adds a second voltage stabilizing circuit;

[0028] Figure 4 Schematic diagram of the circuit structure of a power switch circuit provided by still another embodiment of the present utility model, wherein, Figure 4 The provided power switch circuit is on the basis of Figure 3 and adds a start control circuit and a switch trigger circuit;

[0029] Figure 5 Schematic diagram of the circuit structure of a power switch circuit provided by yet another embodiment of the present utility model, wherein, Figure 5 The provided power switch circuit is on the basis of Figure 4 and adds an enable input circuit and an enable switch circuit;

[0030] Figure 6 Schematic diagram of the specific circuit structure of a power switch circuit provided by an embodiment of the present utility model;

[0031] Figure 7 A schematic circuit diagram of a power switch circuit provided by still another embodiment of the present invention, wherein, Figure 7 The provided power switch circuit is Figure 5 based on which a first switch circuit and a current-limiting voltage-dividing circuit are added. Specific embodiments

[0032] To facilitate the understanding of the present invention, the present invention will be described in more detail below with reference to the accompanying drawings and specific embodiments. It should be noted that when an element is expressed as "fixed to" another element, it can be directly on the other element, or there can be one or more intermediate elements therebetween. When an element is expressed as "electrically connected to" another element, it can be directly connected to the other element, or there can be one or more intermediate elements therebetween. The terms "upper", "lower", "inner", "outer", "bottom", etc. used in this specification indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be construed as a limitation to the present invention. In addition, the terms "first", "second", "third", etc. are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0033] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by those skilled in the technical field to which the present invention belongs. The terms used in the description of the present invention in this specification are only for the purpose of describing specific embodiments and are not used to limit the present invention. The term "and / or" used in this specification includes any and all combinations of one or more of the related listed items. In addition, the technical features involved in different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0034] In the process of implementing the embodiments of the present application, in addition to discovering the technical problems pointed out in the background art, the inventors also found the following technical problems in the related art:

[0035] The power switch circuit provided by the related art includes a PMOS transistor. The gate of the PMOS transistor is controlled by the control of the peripheral circuit, the source is applied with an input power supply, and the drain is used as the output terminal of the input power supply.

[0036] When the PMOS transistor is controlled by the peripheral circuit to enter the conducting state, the junction capacitance of the PMOS transistor enters the discharging state, causing the PMOS transistor to enter the conducting state. When the PMOS transistor is in the conducting state, the input power supply outputs to the load through the PMOS transistor. Among them, a resistor is provided in the discharging loop of the junction capacitance of the PMOS transistor, and the discharging current of the junction capacitance of the PMOS transistor will pass through the resistor. When the PMOS transistor is controlled by the peripheral circuit to enter the cut-off state, the junction capacitance of the PMOS transistor enters the charging state, causing the PMOS transistor to enter the cut-off state. When the PMOS transistor is in the cut-off state, the input power supply cannot output to the load through the PMOS transistor.

[0037] When the voltage of the input power supply is relatively high, the voltage across the resistor becomes larger during the discharging process, which is likely to damage the electronic switch transistor connected to the resistor. When the voltage of the input power supply fluctuates greatly, the voltage across the resistor is not stable, which is likely to reduce the discharging rate of the PMOS transistor, and further reduce the switching rate of the PMOS transistor.

[0038] In the embodiment of the present application, a first voltage stabilizing circuit is provided on the discharging loop. The first voltage stabilizing circuit provides a stable voltage for the lower transistor switching circuit in the discharging loop, thereby preventing the relevant devices of the power switch circuit from being damaged due to excessive voltage or excessive voltage fluctuation of the input power supply, which is beneficial to improving the ability of the power switch circuit to adapt to a wide voltage range.

[0039] Hereinafter, the embodiment of the present application provides a power switch circuit, which can be applied in a power amplifier, and the power amplifier can be a GaN (gallium nitride) power amplifier. Please refer to Figure 1 , the power amplifier includes a power switch circuit 100 and a power amplification circuit 101, and the power amplification circuit 101 is electrically connected to the power switch circuit 100.

[0040] The power switch circuit 100 can transmit a target power supply to the power amplification circuit 101, and the power amplification circuit 101 operates according to the target power supply. When the power amplification circuit 101 enters the working state, it amplifies the input radio frequency signal to obtain an amplified radio frequency signal, and finally transmits the amplified radio frequency signal to the load so that the load processes the amplified radio frequency signal. For example, the load is an antenna, and the antenna, as a radiator of the radio frequency signal, can convert the amplified radio frequency signal into electromagnetic waves and radiate them into space.

[0041] It can be understood that the power amplifier provided in the above embodiment can be applied to any type of electronic device, such as the electronic device includes an electronic strike device, an electronic countermeasure device, a radar device, etc.

[0042] Please refer to Figure 2, the power switch circuit 100 includes a switch startup circuit 200, an upper transistor switch circuit 300, a lower transistor switch circuit 400, a switch switching circuit 500, and a first voltage stabilizing circuit 600.

[0043] The switch startup circuit 200 includes a first node N1 and a second node N2, and is configured to adjust a first voltage of the first node N1 in response to an enable signal, wherein the second node N2 is configured to be applied with a target power supply.

[0044] For example, when the enable signal is at a high level, the switch startup circuit 200 pulls down the first voltage of the first node N1, for example, sets the first voltage to a low level; when the enable signal is at a low level, the switch startup circuit 200 pulls up the first voltage of the first node N1, for example, sets the first voltage to a high level.

[0045] It can be understood that the switch startup circuit 200 can be configured as any circuit structure capable of mapping the enable signal and the first voltage, such that the relationship between the enable signal and the first voltage can not only be the manifestation provided by the above embodiments, but also another manifestation: when the enable signal is at a high level, the switch startup circuit 200 pulls up the first voltage of the first node N1; when the enable signal is at a low level, the switch startup circuit 200 pulls down the first voltage of the first node N1.

[0046] The upper transistor switch circuit 300 is electrically connected between the first node N1 and the second node N2, and is configured to enter an upper transistor switch state in response to the first voltage. For example, when the first voltage is at a low level, the upper transistor switch state is an off state; when the first voltage is at a high level, the upper transistor switch state is an on state.

[0047] The lower transistor switch circuit 400 is electrically connected to the first node N1 and is electrically connected to the upper transistor switch circuit 300 at a preset series node L1, and is configured to enter a lower transistor switch state in response to the first voltage. For example, when the first voltage is at a low level, the lower transistor switch state is an on state; when the first voltage is at a high level, the lower transistor switch state is an off state.

[0048] The lower transistor switch state and the upper transistor switch state are mutually exclusive. When the upper transistor switch state is an on state, the lower transistor switch state is an off state; when the upper transistor switch state is an off state, the lower transistor switch state is an on state.

[0049] The switch switching circuit 500 is electrically connected between the second node N2 and the series node L1. The switch switching circuit 500 is configured with a junction capacitance, and is configured to enter a discharge state or a charge state in response to the upper transistor switch state and the lower transistor switch state. The junction capacitance causes the switch switching circuit 500 to output a target power supply in the discharge state.

[0050] When the upper transistor switch is in the off state and the lower transistor switch is in the on state, the junction capacitance enters the discharge state. The junction capacitance, the lower transistor switch circuit 400, and the first voltage stabilizing circuit 600 form a discharge loop. Among them, when the junction capacitance is in the discharge state, it continuously discharges, causing the switch switching circuit 500 to meet the conduction condition and enter the on state. Then, the target power supply outputs through the switch switching circuit 500.

[0051] When the upper transistor switch is in the on state and the lower transistor switch is in the off state, the junction capacitance enters the charging state. The target power supply charges the junction capacitance. Among them, when the junction capacitance is in the charging state, it causes the switch switching circuit 500 not to meet the conduction condition and enter the off state. Then, the target power supply cannot output through the switch switching circuit 500.

[0052] The first voltage stabilizing circuit 600 is electrically connected to the lower transistor switch circuit 400. When the junction capacitance enters the discharge state, the junction capacitance, the lower transistor switch circuit 400, and the first voltage stabilizing circuit 600 form a discharge loop. The first voltage stabilizing circuit 600 provides a stable voltage for the lower transistor switch circuit 400 in the discharge loop.

[0053] When the voltage of the target power supply is relatively large, for example, when the voltage of the target power supply is any voltage between 10V and 50V, the first voltage stabilizing circuit 600 can still provide a stable voltage for the lower transistor switch circuit 400, avoiding the lower transistor switch circuit 400 from being broken down by the high voltage during the discharge process, thereby protecting the lower transistor switch circuit 400. When the voltage of the target power supply fluctuates greatly, for example, when the voltage of the target power supply fluctuates between 10V and 50V, the first voltage stabilizing circuit 600 can still provide a stable voltage for the lower transistor switch circuit 400, enabling the switch switching circuit 500 to discharge stably and quickly. Therefore, the power switch circuit 100 provided by the embodiment of the present application can adapt to a wide voltage range for fast power switching.

[0054] The first voltage stabilizing circuit 600 provides a stable voltage in the high-voltage state, which can avoid the instability problem of the switch state of the switch switching circuit 500 caused by voltage fluctuations, and is beneficial to the reliable discharge of the switch switching circuit 500. At the same time, the first voltage stabilizing circuit 600 has a fast voltage-current response characteristic, which can quickly respond to the voltage change of the switch switching circuit 500, thereby accelerating the switch switching rate of the switch switching circuit 500.

[0055] Please refer to Figure 3 , in some embodiments, the power switch circuit 100 further includes a second voltage stabilizing circuit 700. The second voltage stabilizing circuit 700 is electrically connected between the first node N1 and the second node N2. The second voltage stabilizing circuit 700 is used to limit the voltage across the upper transistor switch circuit 300, avoiding damage to the components of the upper transistor switch circuit 300 due to excessive voltage across the upper transistor switch circuit 300.

[0056] Please refer to Figure 4 , in some embodiments, the switch startup circuit 200 includes a startup control circuit 21 and a switch trigger circuit 22.

[0057] The startup control circuit 21 includes a third node N3, which is configured to adjust a third voltage of the third node N3 in response to an enable signal. The switch trigger circuit 22 includes a first node N1 and a second node N2, and is electrically connected to the startup control circuit 21 at the third node N3, and is configured to adjust a first voltage of the first node N1 in response to the third voltage.

[0058] When the enable signal is at a high level, the startup control circuit 21 responds to the high level and adjusts the third voltage of the third node N3 to a high level. The switch trigger circuit 22 responds to the high-level third voltage and adjusts the first voltage of the first node N1 to a low level.

[0059] When the enable signal is at a low level, the startup control circuit 21 responds to the high level and adjusts the third voltage of the third node N3 to a low level. The switch trigger circuit 22 responds to the low-level third voltage and adjusts the first voltage of the first node N1 to a high level.

[0060] Please refer to Figure 5 , in some embodiments, the startup control circuit 21 includes an enable input circuit 211 and an enable switch circuit 212.

[0061] The enable input circuit 211 includes a third node N3, which is configured to transmit an enable signal. The enable switch circuit 212 is electrically connected to the enable input circuit 211 at the third node N3, and is configured to adjust the third voltage of the third node N1 in response to the enable signal and a control signal sent by an external device.

[0062] When the enable signal is at a high level and the control signal is at a low level, the enable input circuit 211 transmits a high level, and the enable switch circuit 212 adjusts the third voltage of the third node N1 to a high level.

[0063] When the enable signal is at a low level and the control signal is at a low level, the enable input circuit 211 transmits a low level, and the enable switch circuit 212 adjusts the third voltage of the third node N1 to a low level.

[0064] When the control signal is at a high level, regardless of whether the enable signal is at a high level or a low level, the enable switch circuit 212 adjusts the third voltage of the third node N1 to a low level. As described above, when the third voltage is at a low level, the switch trigger circuit 22 adjusts the first voltage of the first node N1 to a high level. When the first voltage of the first node N1 is at a high level, the upper transistor switch state is in the on state, and the lower transistor switch state is in the off state. When the upper transistor switch state is in the on state and the lower transistor switch state is in the off state, the junction capacitance enters the charging state, and the switch switching circuit 500 enters the off state, and the target power supply cannot be output through the switch switching circuit 500.

[0065] In the embodiment of the present application, an enable switch circuit is added, and by transmitting a control signal to the enable switch circuit, it is possible to control whether the entire power switch circuit needs to work, so as to ensure that the working state of the power switch circuit can be quickly controlled in case of an abnormality, and to protect the downstream circuit from being affected by the power switch circuit.

[0066] Please refer to Figure 6 , in some embodiments, the enable input circuit 211 includes a first resistor R1 and a second resistor R2. One end of the first resistor R1 is applied with the system power supply, and the other end of the first resistor R1 and one end of the second resistor R2 are both applied with the enable signal, and the other end of the second resistor R2 is electrically connected to the third node N3.

[0067] The enable switch circuit 212 includes a third resistor R3 and a second NPN transistor NQ2. One end of the third resistor R3 is applied with the control signal, the other end of the third resistor R3 is electrically connected to the base of the second NPN transistor NQ2, the collector of the second NPN transistor NQ2 is electrically connected to the third node N3, and the emitter of the second NPN transistor NQ2 is grounded.

[0068] The first resistor R1 and the second resistor R2 play a role in current limiting and voltage division, avoiding excessive current transmitted to the base of the third NPN transistor NQ3, and avoiding the voltage of the third node N3 being clamped at the voltage of the system power supply all the time. The third resistor R3 plays a role in current limiting, avoiding excessive current transmitted to the base of the second NPN transistor NQ2.

[0069] When the control signal is at a high level, the second NPN transistor NQ2 enters the on state, thereby pulling down the third voltage of the third node N3. At this time, even if the enable signal is at a high level, the third voltage of the third node N3 is still at a low level.

[0070] When the control signal is at a low level, the second NPN transistor NQ2 enters the off state. At this time, if the enable signal is at a high level, the third voltage of the third node N3 is at a high level. If the enable signal is at a low level, the third voltage of the third node N3 is at a low level.

[0071] Please refer to Figure 7 , in some embodiments, the switch trigger circuit 22 includes a first switch circuit 221 and a current limiting and voltage dividing circuit 222.

[0072] The first switch circuit 221 is electrically connected to the start control circuit 21 at the third node N3, and is used to enter the target switch state in response to the third voltage.

[0073] The current limiting and voltage dividing circuit 222 includes a first node N1 and a second node N2. The current limiting and voltage dividing circuit 222 is electrically connected to the first switch circuit 221, and is used to adjust the first voltage of the first node N1 in response to the first switch circuit 221 entering the target switch state.

[0074] When the third voltage is high, the first switch circuit 221 enters the conducting state, where the target switch state is the conducting state. When the first switch circuit 221 enters the conducting state, the current limiting and voltage dividing circuit 222 adjusts the first voltage of the first node N1 to a low level.

[0075] When the third voltage is low, the first switch circuit 221 enters the cut-off state, where the target switch state is the cut-off state. When the first switch circuit 221 enters the cut-off state, the current limiting and voltage dividing circuit 222 adjusts the first voltage of the first node N1 to a high level.

[0076] Please combine with Figure 6 , in some embodiments, the first switch circuit 221 includes a fourth resistor R4 and a third NPN transistor NQ3. One end of the fourth resistor R4 is electrically connected to the third node N3, the other end of the fourth resistor R4 is electrically connected to the base of the third NPN transistor NQ3, the collector of the third NPN transistor NQ3 is electrically connected to the current limiting and voltage dividing circuit 222, and the emitter of the third NPN transistor NQ3 is grounded.

[0077] The current limiting and voltage dividing circuit 222 includes a fifth resistor R5 and a sixth resistor R6. One end of the fifth resistor R5 is electrically connected to the collector of the third NPN transistor NQ3, the other end of the fifth resistor R5 is electrically connected to the first node N1, one end of the sixth resistor R6 is electrically connected to the first node N1, and the other end of the sixth resistor R6 is electrically connected to the second node N2.

[0078] The fourth resistor R4 functions to limit the current to prevent the current transmitted to the base of the third NPN transistor NQ3 from being too large. The fifth resistor R5 and the sixth resistor R6 function to limit the current and divide the voltage, and are used to adjust the first voltage of the first node N1 to an appropriate voltage to avoid damaging the upper transistor switch circuit 300 and the lower transistor switch circuit 400.

[0079] When the third voltage of the third node N3 is at a high level, the third NPN transistor NQ3 enters the conducting state, thereby pulling down the first voltage of the first node N1. At this time, the upper transistor switching state of the upper transistor switching circuit 300 is in the cut-off state, the lower transistor switching state of the lower transistor switching circuit 400 is in the conducting state, the junction capacitance enters the discharging state, the switching switching circuit 500 meets the conducting condition and enters the conducting state. Thus, the target power supply is output through the switching switching circuit 500.

[0080] When the third voltage of the third node N3 is at a low level, the third NPN transistor NQ3 enters the cut-off state, thereby raising the first voltage of the first node N1. At this time, the upper transistor switching state of the upper transistor switching circuit 300 is in the conducting state, the lower transistor switching state of the lower transistor switching circuit 400 is in the cut-off state, the junction capacitance enters the charging state, the switching switching circuit 500 does not meet the conducting condition and enters the cut-off state. Thus, the target power supply cannot be output through the switching switching circuit 500.

[0081] Please refer to Figure 6 , in some embodiments, the upper transistor switching circuit 300 includes a first NPN transistor NQ1. The base of the first NPN transistor NQ1 is electrically connected to the first node N1, the emitter is electrically connected to the series node L1, and the collector is applied with the target power supply.

[0082] When the voltage of the first node N1 is at a high level, the first NPN transistor NQ1 enters the conducting state, that is, the upper transistor switching state is in the conducting state, and the lower transistor switching state of the lower transistor switching circuit is in the cut-off state.

[0083] When the voltage of the first node N1 is at a low level, the first NPN transistor NQ1 enters the cut-off state, that is, the upper transistor switching state is in the cut-off state, and the lower transistor switching state of the lower transistor switching circuit is in the conducting state.

[0084] Please continue to refer to Figure 6 , in some embodiments, the upper transistor switching circuit 300 further includes a seventh resistor R7. One end of the seventh resistor R7 is electrically connected to the second node N2, and the other end of the seventh resistor R7 is electrically connected to the collector of the first NPN transistor NQ1. The seventh resistor R7 functions to limit the current and adjust the working voltages of each node.

[0085] Please refer to Figure 6 , in some embodiments, the lower transistor switching circuit 400 includes a first PNP transistor PQ1. The base of the first PNP transistor PQ1 is electrically connected to the first node N1, the emitter is electrically connected to the series node L1, and the collector is electrically connected to the first voltage stabilizing circuit 600.

[0086] When the voltage of the first node N1 is high, the first PNP transistor PQ1 enters the cut-off state, that is, the switching state of the lower transistor is the cut-off state, and the switching state of the upper transistor in the upper transistor switching circuit is the conducting state.

[0087] When the voltage of the first node N1 is low, the first PNP transistor PQ1 enters the conducting state, that is, the switching state of the lower transistor is the conducting state, and the switching state of the upper transistor in the upper transistor switching circuit is the cut-off state.

[0088] It can be understood that in some embodiments, in addition to selecting an NPN transistor for the electronic switching transistor of the upper transistor switching circuit 300, a PNP transistor, an NMOS transistor, or a PMOS transistor can also be selected. Correspondingly, in addition to selecting a PNP transistor for the electronic switching transistor of the lower transistor switching circuit 400, an NPN transistor, an NMOS transistor, or a PMOS transistor can also be selected.

[0089] Please refer to Figure 6 , in some embodiments, the switch switching circuit 500 includes a PMOS transistor PQ2. The source of the PMOS transistor PQ2 is applied with a target power supply. The gate is electrically connected to the series node L1, and the drain is the output terminal of the target power supply. The gate-source capacitance of the PMOS transistor PQ2 is the junction capacitance.

[0090] When the switching state of the upper transistor in the upper transistor switching circuit is the conducting state and the switching state of the lower transistor is the cut-off state, the junction capacitance of the PMOS transistor PQ2 enters the charging state, the PMOS transistor PQ2 does not meet the conducting condition and enters the cut-off state, and the target power supply cannot be output through the PMOS transistor PQ2.

[0091] When the switching state of the upper transistor in the upper transistor switching circuit is the cut-off state and the switching state of the lower transistor is the conducting state, the junction capacitance of the PMOS transistor PQ2 enters the discharging state, the PMOS transistor PQ2 meets the conducting condition and enters the conducting state, and the target power supply can be output through the PMOS transistor PQ2.

[0092] Please continue to refer to Figure 6 , in some embodiments, the switch switching circuit 500 further includes an eighth resistor R8, a first capacitor C1, and a second capacitor C2. One end of the first capacitor C1 is grounded, and the other end of the first capacitor C1 is electrically connected to the source of the PMOS transistor PQ2. One end of the second capacitor C2 is grounded, and the other end of the second capacitor C2 is electrically connected to the drain of the PMOS transistor PQ2. The first capacitor C1 and the second capacitor C2 can filter out harmonic signals and improve the output quality of the target power supply.

[0093] Please refer to Figure 6, in some embodiments, the first voltage stabilizing circuit 600 includes a first voltage stabilizing diode D1. The positive electrode of the first voltage stabilizing diode D1 is grounded, and the negative electrode of the first voltage stabilizing diode D1 is electrically connected to the lower transistor switching circuit 400. Specifically, the negative electrode of the first voltage stabilizing diode D1 is electrically connected to the collector of the first PNP transistor PQ1.

[0094] Please refer to Figure 6 , in some embodiments, the second voltage stabilizing circuit 700 includes a second voltage stabilizing diode D2. The positive electrode of the second voltage stabilizing diode D2 is electrically connected to the first node N1, and the negative electrode of the second voltage stabilizing diode D2 is electrically connected to the second node N2.

[0095] Hereinafter, the embodiments of the present application will Figure 6 make the following detailed elaboration on the working principle of the power switch circuit 100 provided by the embodiments of the present application, specifically as follows:

[0096] When the power switch circuit 100 is in an abnormal state, the external device sends a high-level control signal to the second NPN transistor NQ2. The second NPN transistor NQ2 pulls down the third voltage at the third node N3 to a low level, and the third NPN transistor NQ3 enters the cut-off state. The first voltage at the first node N1 is at a high level. The first NPN transistor NQ1 enters the conduction state, and the first PNP transistor PQ1 enters the cut-off state. The junction capacitance of the PMOS transistor PQ2 enters the charging state. At the same time, the PMOS transistor PQ2 enters the cut-off state, and the target power supply cannot be output through the PMOS transistor PQ2. At this time, regardless of whether the enable signal is at a high level or a low level, the PMOS transistor PQ2 is in the cut-off state.

[0097] When the power switch circuit 100 is in a normal state, the external device sends a low-level control signal to the second NPN transistor NQ2.

[0098] On the premise that the power switch circuit 100 is in a normal state:

[0099] When the enable signal is at a high level, the third NPN transistor NQ3 enters the conduction state, pulls down the first voltage at the first node N1 to a low level, the first NPN transistor NQ1 enters the cut-off state, and the first PNP transistor PQ1 enters the conduction state. The junction capacitance of the PMOS transistor PQ2 enters the discharging state. Among them, the junction capacitance of the PMOS transistor PQ2, the first PNP transistor PQ1, and the first voltage stabilizing diode D1 form a discharging loop. During the discharging process, the gate-source voltage of the PMOS transistor PQ2 is less than 0, and the PMOS transistor PQ2 meets the conduction condition and enters the conduction state, and the target power supply can be output through the PMOS transistor PQ2.

[0100] During the discharging process, the first zener diode D1 provides a stable voltage for the first PNP transistor PQ1 in the discharging circuit, thereby preventing the voltage of the target power supply from being too large or fluctuating too much and damaging the related devices of the power switch circuit, which is beneficial to improving the ability of the power switch circuit 100 to adapt to a wide voltage range.

[0101] At the same time, the first zener diode D1 provides a stable voltage in the high-voltage state, which can avoid the instability problem of the switching state of the PMOS transistor PQ2 caused by voltage fluctuations, and is beneficial to the reliable discharging of the PMOS transistor PQ2. At the same time, the first zener diode D1 has a fast voltage-current response characteristic, which can quickly respond to the voltage change of the PMOS transistor PQ2, thereby accelerating the switching rate of the PMOS transistor PQ2.

[0102] In addition, the second zener diode D2 can clamp the voltage between the base and the collector of the first NPN transistor NQ1 to a stable voltage, avoiding that the voltage of the target power supply is too large and easily breakdown the first NPN transistor NQ1.

[0103] When the enable signal is at a low level, the third NPN transistor NQ3 enters the cut-off state, raising the first voltage of the first node N1 to a high level. The first NPN transistor NQ1 enters the conducting state, the first PNP transistor PQ1 enters the cut-off state, and the junction capacitance of the PMOS transistor PQ2 enters the charging state. In this way, the gate voltage of the PMOS transistor PQ2 is equal to the source voltage, causing the PMOS transistor PQ2 not to meet the conduction condition and enter the cut-off state, and the target power supply cannot be output through the PMOS transistor PQ2.

[0104] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than limiting it; under the idea of the present invention, the technical features in the above embodiments or different embodiments can also be combined, and the steps can be implemented in any order, and there are many other variations in different aspects of the present invention as described above. For the sake of brevity, they are not provided in detail; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A power switch circuit, characterized in that: include: A switch start-up circuit, comprising a first node and a second node, for adjusting a first voltage of the first node in response to an enable signal, wherein the second node is used to be applied with a target power supply; an upper tube switch circuit, electrically connected between the first node and the second node, and configured to enter an upper tube switch state in response to the first voltage; a lower tube switch circuit, electrically connected to the first node and electrically connected to the upper tube switch circuit at a preset series node, for responding to the first voltage to enter a lower tube switch state, the lower tube switch state and the upper tube switch state being mutually exclusive; a switch switching circuit, electrically connected between the second node and the series node, the switch switching circuit being configured with a junction capacitor, for responding to the upper tube switch state and the lower tube switch state to enter a discharge state or a charge state, the junction capacitor prompting the switch switching circuit to output the target power supply in the discharge state; The first voltage stabilizing circuit is electrically connected to the lower tube switch circuit. When the junction capacitor enters a discharge state, the junction capacitor, the lower tube switch circuit and the first voltage stabilizing circuit form a discharge loop. The first voltage stabilizing circuit provides a stable voltage for the lower tube switch circuit in the discharge loop.

2. The power switch circuit according to claim 1, characterized in that: The first voltage stabilizing circuit includes a first voltage stabilizing diode, an anode of the first voltage stabilizing diode is grounded, and a cathode of the first voltage stabilizing diode is electrically connected to the lower tube switch circuit.

3. The power switch circuit according to claim 1, characterized in that: The switch start circuit comprises: A startup control circuit, comprising a third node, for adjusting a third voltage of the third node in response to the enable signal; The switch trigger circuit includes the first node and the second node, is electrically connected to the startup control circuit at the third node, and is used to respond to the third voltage to adjust the first voltage of the first node.

4. The power switch circuit according to claim 3, characterized in that: The startup control circuit comprises: an enable input circuit, comprising the third node, for transmitting the enable signal; The enabling switch circuit is electrically connected to the enabling input circuit at the third node, and is used to respond to the enabling signal and a control signal sent by an external device to adjust a third voltage of the third node.

5. The power switch circuit according to claim 1, characterized in that: The upper tube switch circuit includes a first NPN type transistor, the base of the first NPN type transistor is electrically connected to the first node, the emitter is electrically connected to the series node, and the collector is applied with the target power supply.

6. The power switch circuit according to claim 1, characterized in that: The lower tube switch circuit includes a first PNP type transistor, the base of the first PNP type transistor is electrically connected to the first node, the emitter is electrically connected to the series node, and the collector is electrically connected to the first voltage stabilizing circuit.

7. The power switch circuit according to claim 1, characterized in that: The switch switching circuit includes a PMOS tube, the source of the PMOS tube is applied with the target power supply, the gate is electrically connected to the series node, the drain is the output end of the target power supply, and the gate-source capacitance of the PMOS tube is the junction capacitance.

8. The power switch circuit according to any one of claims 1 to 7, characterized in that: The device further includes a second voltage stabilizing circuit electrically connected between the first node and the second node.

9. A power amplifier, characterized in that: The invention comprises a power switch circuit as claimed in any one of claims 1 to 8.

10. An electronic device, characterized in that: Comprising the power amplifier as claimed in claim 9.

Images