SD card IO port level conversion circuit

Abstract

The utility model relates to the field of SD (Secure Digital) cards, in particular to an IO (Input / Output) port level conversion circuit of an SD card. In the circuit, a traditional SD card IO port level conversion circuit is improved, each switching circuit is controlled through the main control module, level conversion at the SD card module end is completed through the conduction of the first switching circuit and the second switching circuit, compared with a control circuit design in the related technology, the cost of a power supply chip and a resistance state chip is reduced, and the reliability of the circuit is improved. The method has good application and popularization values in various scenes.

Description

Technical Field

[0001] The utility model relates to the field of SD cards, and particularly to an SD card IO port level conversion circuit. Background Art

[0002] With the continuous improvement of people's living standards and the pursuit of better product performance, the consumption demand in the electronic product industry in China has been upgraded. There are increasing demands for the miniaturization and convenience of electronic products, as well as for larger storage capacities and higher data transmission rates. Due to its advantages such as small size, light weight, large capacity, fast transmission speed, and high data reliability, SD cards are widely used in mobile storage.

[0003] An SD card is a memory card based on the SPI protocol. The voltage of its transmission interface IO port mainly includes 3.3V voltage and 1.8V voltage. In the SD protocol, when the SD card is powered by 3.3V, the upper limit of the frequency is 50MHZ, and the upper limit of the communication rate is 25MB / sec. However, this communication cannot meet many high-rate demand scenarios. Therefore, after the SD card is powered on and initialized, it is necessary to switch the IO port level from 3.3V to 1.8V to meet the high-rate demand. The highest rate can reach 10425MB / sec, and the voltage switch brings the advantage of low power consumption, thus extending the working time of the circuit.

[0004] In the related art, the switching of the IO port level is achieved by using a DC power chip to output a power supply to pull up the IO port, and software controls the feedback resistance value of the DC power chip to change the output power supply from 3.3V to 1.8V. However, this solution requires adding a DC power chip and a resistance state chip, resulting in a high cost. Summary of the Utility Model

[0005] The utility model provides an SD card IO port level conversion circuit, which can solve the problem of high cost in realizing the IO port level conversion in the related art. The technical solution is as follows:

[0006] An SD card IO port level conversion circuit is provided. The circuit includes a first switch circuit 10, a second switch circuit 20, a main control module 30, an inter-switch resistor R, a first level terminal 11, a second level terminal 21, and an SD card module terminal 31;

[0007] The input end of the first switch circuit 10 is connected to the first level terminal 11, the output end of the first switch circuit 10 is connected to the output end of the second switch circuit 20, and the input end of the second switch circuit 20 is connected to the second level terminal 21; the second switch circuit 20 is provided with a grounding terminal DGND;

[0008] The control terminal of the first switch circuit 10 is connected to the first end of the resistor R between switches, and the second end of the resistor R between switches is connected to the control terminal of the second switch circuit 20; the first end of the resistor R between switches is also connected to the main control module 30;

[0009] The SD card module terminal 31 is connected to the output terminal of the first switch circuit 10 and, at the same time, to the output terminal of the second switch circuit 20.

[0010] Optionally, the first switch circuit 10 includes a first MOS transistor Q1 and a first resistor R1;

[0011] The input terminal of the first MOS transistor Q1 serves as the input terminal of the first switch circuit 10, the output terminal of the first MOS transistor Q1 serves as the output terminal of the first switch circuit 10, and the control terminal of the first MOS transistor Q1 serves as the control terminal of the first switch circuit 10;

[0012] In the first switch circuit 10, the control terminal of the first MOS transistor Q1 is connected to the first end of the first resistor R1, and the second end of the first resistor R1 is connected to the first level terminal 11.

[0013] Optionally, the second switch circuit 20 includes a second MOS transistor Q2 and a second resistor R2;

[0014] The input terminal of the second MOS transistor Q2 serves as the input terminal of the second switch circuit 20, the output terminal of the second MOS transistor Q2 serves as the output terminal of the second switch circuit 20, and the control terminal of the second MOS transistor Q2 serves as the control terminal of the second switch circuit 20;

[0015] In the second switch circuit 20, the control terminal of the second MOS transistor Q2 is connected to the first end of the second resistor R2, the second end of the second resistor R2 is connected to the output terminal of the second MOS transistor Q2; the first end of the second resistor R2 is connected to the ground terminal DGND.

[0016] Optionally, the first switch circuit 10 is also provided with a filtering circuit, and the filtering circuit includes a first capacitor C1;

[0017] The first capacitor C1 is connected in parallel across the first resistor R1.

[0018] Optionally, the second switch circuit 20 is also provided with a filtering circuit, and the filtering circuit includes a second capacitor C2 and a third capacitor C3;

[0019] The second capacitor C2 is connected in parallel across the second resistor R2;

[0020] The first end of the third capacitor C3 is connected to the control terminal of the second MOS transistor Q2, and the second end of the third capacitor C3 is connected to the first end of the second resistor R2.

[0021] Optionally, the filtering circuit further includes a fourth capacitor C4;

[0022] The first terminal of the fourth capacitor C4 is connected to the input terminal of the second MOS transistor Q2, and the second terminal of the fourth capacitor C4 is connected to the ground terminal DGND.

[0023] Optionally, the first level terminal 11 is a 3.3V power supply terminal, and the second level terminal 21 is a 1.8V power supply terminal.

[0024] Optionally, the first MOS transistor Q1 is of PMOS transistor type;

[0025] The source electrode of the first MOS transistor Q1 is provided as the input terminal of the first switching circuit 10, the drain electrode of the first MOS transistor Q1 is provided as the output terminal of the first switching circuit 10, and the gate electrode of the first MOS transistor Q1 is provided as the control terminal of the first switching circuit 10.

[0026] Optionally, the second MOS transistor Q2 is of NMOS transistor type;

[0027] The source electrode of the second MOS transistor Q2 is provided as the input terminal of the second switching circuit 20, the drain electrode of the second MOS transistor Q2 is provided as the output terminal of the second switching circuit 20, and the gate electrode of the second MOS transistor Q2 is provided as the control terminal of the second switching circuit 20.

[0028] The technical effects brought by this application are at least as follows.

[0029] This application provides an SD card IO port level conversion circuit, which improves the traditional SD card IO port level conversion circuit. In this circuit, the main control module controls each switching circuit, and the conduction of the first switching circuit and the second switching circuit complete the level conversion at the SD card module end. Compared with the control circuit design in the related art, the cost of the power supply chip and the impedance chip is reduced, and it has good application and promotion value in various scenarios. Description of the Drawings

[0030] Figure 1 Shows the circuit structure schematic diagram of the SD card IO port level conversion circuit in the related art;

[0031] Figure 2 Shows the circuit structure schematic diagram of the SD card IO port level conversion circuit shown in an exemplary embodiment of this application;

[0032] Figure 3 Shows the circuit structure schematic diagram of the SD card IO port level conversion circuit shown in another exemplary embodiment of this application. Detailed Embodiments

[0033] To make the purpose, technical solutions and advantages of this application clearer, the following will further describe the embodiments of this application in detail with reference to the drawings.

[0034] As used herein, "a plurality of" means two or more. "And / or" describes the relationship between associated objects and indicates that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally indicates an "or" relationship between the associated objects before and after.

[0035] To further illustrate the improvements in the circuit structure of the present utility model, please refer to Figure 1 , Figure 1 which shows a schematic circuit diagram of the SD card IO port level conversion circuit in the related art.

[0036] As Figure 1 shown, the currently common method is that the DC power supply chip outputs a path Figure 1 marked as OUT in , and the power of this path is pulled up to the IO port. The software controls the feedback resistance value of the DC power supply chip to change the voltage of the output power supply VDD_GPIO_SB terminal from 3.3V to 1.8V, thus completing the level conversion. However, this solution requires a DC power supply chip and a resistance state chip to complete, with a relatively high cost. Here, FB indicates a voltage-dividing feedback resistor.

[0037] Therefore, the present utility model provides a low-cost SD card IO port level conversion circuit, which can solve the problem of relatively high cost in realizing IO port level conversion in the related art.

[0038] As Figure 2 shown, Figure 2 shows a schematic circuit diagram of the SD card IO port level conversion circuit shown in an exemplary embodiment of the present application.

[0039] First, the composition and connection relationship of the SD card IO port level conversion circuit will be introduced. The circuit includes a first switch circuit 10, a second switch circuit 20, a main control module 30, an inter-switch resistor R, a first level terminal 11, a second level terminal 21, and an SD card module terminal 31 as Figure 2 shown, Figure 2 wherein, the first switch circuit 10 is simply marked as VCC_1, and the second switch circuit 20 is simply marked as VCC_2.

[0040] For the first switch circuit 10, the input end of the first switch circuit 10 is connected to the first level terminal 11, the output end of the first switch circuit 10 is connected to the output end of the second switch circuit 20, and the input end of the second switch circuit 20 is connected to the second level terminal 21; the second switch circuit 20 is provided with a ground terminal DGND.

[0041] Further, the control end of the first switch circuit 10 is connected to the first end of the resistor R between switches, and the second end of the resistor R between switches is connected to the control end of the second switch circuit 20; the first end of the resistor R between switches is also connected to the main control module 30.

[0042] The SD card module terminal 31 is connected to the output end of the first switch circuit 10 and, as well as, to the output end of the second switch circuit 20.

[0043] In the embodiment of the present application, the SD card module terminal 31 needs to complete the conversion of the IO port level, and its conversion principle is as follows. The main control module 30 plays a control role in the SD card IO port level conversion circuit. Specifically, the main control module 30 controls the conduction and cut-off of the first switch circuit 10 and the second switch circuit 20. During the power-on and initialization process of the SD card module terminal 31, the main control module 30 sends a low-level signal to the circuit, the first switch circuit 10 conducts, the second switch circuit 20 cuts off, and the level of the SD card module terminal 31 is 3.3V; when the initialization of the SD card module terminal 31 is completed and there is a high-speed communication requirement, the signal sent by the main control module 30 changes from a low-level signal to a high-level signal, the first switch circuit 10 cuts off, the second switch circuit 20 conducts, and the level of the SD card module terminal 31 becomes 1.8V, so as to meet the timing requirements of the SD card IO level.

[0044] In summary, the embodiment of the present application improves the traditional SD card IO port level conversion circuit. By controlling each switch circuit through the main control module and the conductivity of the first switch circuit and the second switch circuit, the level conversion at the SD card module terminal is completed. Compared with the control circuit design in the related art, the cost of the power supply chip and the impedance chip is reduced, and it has good application and promotion value in various scenarios.

[0045] As Figure 3 shown, Figure 3 Fig. shows the schematic circuit diagram of the SD card IO port level conversion circuit shown in another exemplary embodiment of the present application.

[0046] In the embodiment of the present application, a further description is made of the possible structures of each circuit.

[0047] For the first switch circuit 10, it includes a first MOS transistor Q1 and a first resistor R1. The input end of the first MOS transistor Q1 serves as the input end of the first switch circuit 10, the output end of the first MOS transistor Q1 serves as the output end of the first switch circuit 10, and the control end of the first MOS transistor Q1 serves as the control end of the first switch circuit 10.

[0048] In the first switch circuit 10, the control end of the first MOS transistor Q1 is connected to the first end of the first resistor R1, and the second end of the first resistor R1 is connected to the first level terminal 11.

[0049] For the second switch circuit 20, it includes a second MOS transistor Q2 and a second resistor R2. The input terminal of the second MOS transistor Q2 serves as the input terminal of the second switch circuit 20, the output terminal of the second MOS transistor Q2 serves as the output terminal of the second switch circuit 20, and the control terminal of the second MOS transistor Q2 serves as the control terminal of the second switch circuit 20.

[0050] In the second switch circuit 20, the control terminal of the second MOS transistor Q2 is connected to the first end of the second resistor R2, and the second end of the second resistor R2 is connected to the output terminal of the second MOS transistor Q2; the first end of the second resistor R2 is connected to the ground terminal DGND.

[0051] In a further embodiment, in order to improve the stable transmission of the signal of the first switch circuit, a filter circuit is further provided in the first switch circuit 10. The filter circuit includes a first capacitor C1. The first capacitor C1 is connected in parallel across the two ends of the first resistor R1.

[0052] In a further embodiment, in order to improve the stable transmission of the signal of the second switch circuit, the second switch circuit 20 is further provided with a filter circuit. The filter circuit includes a second capacitor C2 and a third capacitor C3; the second capacitor C2 is connected in parallel across the two ends of the second resistor R2; the first end of the third capacitor C3 is connected to the control terminal of the second MOS transistor Q2, and the second end of the third capacitor C3 is connected to the first end of the second resistor R2.

[0053] Further, in the second switch circuit 20, the filter circuit further includes a fourth capacitor C4. The first end of the fourth capacitor C4 is connected to the input terminal of the second MOS transistor Q2, and the second end of the fourth capacitor C4 is connected to the ground terminal DGND.

[0054] Considering the SPI protocol of the SD card, the voltages of its transmission interface IO ports mainly include 3.3V voltage and 1.8V voltage. In the embodiment of the present application, the first level terminal 11 is a 3.3V power supply terminal, marked as VCC_3.3V, the second level terminal 21 is a 1.8V power supply terminal, marked as VCC_1.8V. In addition, the SD card module terminal 31 is Figure 3 marked as VDD_GPIO_SD in

[0055] In the embodiment of the present application, the first MOS transistor Q1 is of PMOS transistor type. Thus, the source S of the first MOS transistor Q1 serves as the input terminal of the first switch circuit 10, the drain D of the first MOS transistor Q1 serves as the output terminal of the first switch circuit 10, and the gate G of the first MOS transistor Q1 serves as the control terminal of the first switch circuit 10.

[0056] In the embodiment of the present application, the second MOS transistor Q2 is of the NMOS transistor type. Thus, the source S of the second MOS transistor Q2 serves as the input terminal of the second switching circuit 20, the drain D of the second MOS transistor Q2 serves as the output terminal of the second switching circuit 20, and the gate G of the second MOS transistor Q2 serves as the control terminal of the second switching circuit 20.

[0057] In addition, for better application by those skilled in the art, the present application also provides examples of the usage parameters of each resistor and capacitor as illustrative explanations. As Figure 3 shown, the following feasibility suggestions for parameters are given in combination with the simulation effect. The value of R1 is 47K, the value of R2 is 1K, the selected resistor for R is 300R, the value of C1 is 0.1 μF, the value of C2 is 1 μF, the value of C3 is 1 nF, and the value of C4 is 0.1 μF.

[0058] Corresponding to Figure 3 , the principle of SD card level conversion is further described. The main control module 30 plays a controlling role in the SD card IO port level conversion circuit. Specifically, the main control module 30 controls the conduction and cut-off of the first switching circuit 10 and the second switching circuit 20. During the power-on and initialization process of the SD card module terminal 31, the main control module 30 sends a low-level signal to the circuit, the first MOS transistor Q1 conducts, the second MOS transistor Q2 cuts off, and the level at VDD_GPIO_SD is 3.3V; when the initialization of the SD card module terminal 31 is completed and there is a high-speed communication requirement, the signal sent by the main control module 30 changes from a low-level signal to a high-level signal, the first MOS transistor Q1 cuts off, the second MOS transistor Q2 conducts, and the level at VDD_GPIO_SD becomes 1.8V, thus meeting the timing requirements of the SD card IO level.

[0059] Thus, the present application provides a low-cost SD card IO port level conversion circuit, which has broad application prospects in fields such as automotive engineering technology, circuit field, and SD card field. Specifically, this technical solution can be applied to SD card circuits with high-speed communication requirements and has a low cost. With the continuous improvement of people's product requirements and the continuous increase in the high-speed requirements for SD cards, the technical application prospects and market demand of the present invention will also continue to expand, having broad market prospects.

[0060] In addition, the following factors can also be considered to improve the SD card IO port level conversion circuit in the present application.

[0061] I. Consideration of stability and reliability: Ensure that the parameters of the capacitors and resistors used in the filtering circuit are properly selected to meet the requirements of stable transmission. Those skilled in the art can conduct some circuit simulations or actual tests to verify. Consider using higher-precision components such as capacitors and resistors to ensure the stability and long-term reliability of the circuit.

[0062] II. Circuit Protection: Add overcurrent protection and overvoltage protection circuits. Components such as fuses, voltage regulators, and current limiters can be used to protect the circuit from unexpected voltage or current fluctuations. Consider using a Transient Voltage Suppressor (TVS) to prevent the circuit from being damaged when suffering from transient overvoltage.

[0063] III. Environmental Adaptability: Use components and materials certified by industrial standards to ensure the stable operation of the circuit under different environmental conditions. Pay special attention to the impact of temperature changes on circuit performance and perform thermal design. Consider using enclosures or packages with good sealing performance to prevent environmental factors such as humidity and dust from affecting the circuit.

[0064] IV. Standard Compliance: Ensure that the circuit design complies with relevant standards and specifications in the field of automotive engineering technology, such as ISO26262 (Functional Safety Standard), ISO 16750 (Automotive Electrical System Environmental Test Standard), etc., to ensure the safety and reliability of the product in the automotive environment. Conduct necessary certifications and tests to verify that the circuit meets the required standard and specification requirements.

[0065] V. Cost and Efficiency Optimization: Regularly evaluate the cost of circuit components and look for substitutes or bulk purchases to reduce costs. Optimize the circuit structure and layout, reduce the occupied space on the circuit board, and improve circuit efficiency and performance. Consider using programmable devices or integrated circuits to simplify the circuit design and improve flexibility.

[0066] Taking the above improvement directions into comprehensive consideration, the circuit design can be adjusted and optimized to ensure that it meets the expected requirements in terms of stability, protection, environmental adaptability, standard compliance, and cost efficiency.

[0067] The above embodiments of the present utility model are only for description and do not represent the advantages and disadvantages of the embodiments. The above are only optional embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

Claims

1. A SD card IO port level conversion circuit, characterized in that: The circuit comprises a first switch circuit (10), a second switch circuit (20), a main control module (30), an inter-switch resistor (R), a first level end (11), a second level end (21) and an SD card module end (31); The input end of the first switch circuit (10) is connected to the first level end (11), the output end of the first switch circuit (10) is connected to the output end of the second switch circuit (20), and the input end of the second switch circuit (20) is connected to the second level end (21); the second switch circuit (20) is provided with a ground end (DGND); The control end of the first switch circuit (10) is connected to the first end of the inter-switch resistor (R), and the second end of the inter-switch resistor (R) is connected to the control end of the second switch circuit (20); the first end of the inter-switch resistor (R) is also connected to the main control module (30); The SD card module end (31) is connected to the output end of the first switch circuit (10), and is connected to the output end of the second switch circuit (20).

2. The SD card IO port level conversion circuit according to claim 1, characterized in that: The first switch circuit (10) comprises a first MOS tube (Q1) and a first resistor (R1); The input end of the first MOS transistor (Q1) serves as the input end of the first switch circuit (10), the output end of the first MOS transistor (Q1) serves as the output end of the first switch circuit (10), and the control end of the first MOS transistor (Q1) serves as the control end of the first switch circuit (10); In the first switch circuit (10), the control end of the first MOS transistor (Q1) is connected to the first end of the first resistor (R1), and the second end of the first resistor (R1) is connected to the first level end (11).

3. The SD card IO port level conversion circuit according to claim 1, characterized in that: The second switch circuit (20) comprises a second MOS tube (Q2) and a second resistor (R2); The input end of the second MOS transistor (Q2) serves as the input end of the second switch circuit (20), the output end of the second MOS transistor (Q2) serves as the output end of the second switch circuit (20), and the control end of the second MOS transistor (Q2) serves as the control end of the second switch circuit (20); In the second switch circuit (20), the control end of the second MOS transistor (Q2) is connected to the first end of the second resistor (R2), the second end of the second resistor (R2) is connected to the output end of the second MOS transistor (Q2); and the first end of the second resistor (R2) is connected to the ground end (DGND).

4. The SD card IO port level conversion circuit according to claim 2, characterized in that: The first switch circuit (10) is further provided with a filter circuit, and the filter circuit comprises a first capacitor (C1); The first capacitor (C1) is connected in parallel to both ends of the first resistor (R1).

5. The SD card IO port level conversion circuit according to claim 3, characterized in that: The second switch circuit (20) is further provided with a filter circuit, wherein the filter circuit comprises a second capacitor (C2) and a third capacitor (C3); The second capacitor (C2) is connected in parallel to both ends of the second resistor (R2); A first end of the third capacitor (C3) is connected to the control end of the second MOS tube (Q2), and a second end of the third capacitor (C3) is connected to the first end of the second resistor (R2).

6. The SD card IO port level conversion circuit according to claim 5, characterized in that: The filter circuit also includes a fourth capacitor (C4); A first end of the fourth capacitor (C4) is connected to the input end of the second MOS tube (Q2), and a second end of the fourth capacitor (C4) is connected to the ground end (DGND).

7. The SD card IO port level conversion circuit according to any one of claims 1 to 5, characterized in that: The first level end (11) is a 3.3V power supply end, and the second level end (21) is a 1.8V power supply end.

8. The SD card IO port level conversion circuit according to claim 2, characterized in that: The first MOS tube (Q1) is a PMOS tube type; The source of the first MOS transistor (Q1) serves as the input end of the first switch circuit (10), the drain of the first MOS transistor (Q1) serves as the output end of the first switch circuit (10), and the gate of the first MOS transistor (Q1) serves as the control end of the first switch circuit (10).

9. The SD card IO port level conversion circuit according to claim 3, characterized in that: The second MOS tube (Q2) is an NMOS tube type; The source of the second MOS transistor (Q2) serves as the input end of the second switch circuit (20), the drain of the second MOS transistor (Q2) serves as the output end of the second switch circuit (20), and the gate of the second MOS transistor (Q2) serves as the control end of the second switch circuit (20).

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