Frequency locking circuit and DC-DC voltage conversion circuit

Abstract

The utility model discloses a frequency locking circuit, which is applied to a DC-DC voltage conversion circuit, and comprises a turn-on time control circuit for comparing the pulse width of a reference signal with the pulse width of a switch node signal of the voltage conversion circuit, and generating a corresponding control signal; the turn-on time generation circuit is connected with the turn-on time control circuit, and the turn-on time generation circuit is configured to generate a turn-on duration signal based on the control signal; the driving circuit is connected with the conduction time generation circuit, and the driving circuit is configured to drive the voltage conversion circuit based on the conduction duration signal; wherein the pulse width of the conduction duration signal is adjusted to be matched with the pulse width of the reference signal. The utility model further discloses a DC-DC voltage conversion circuit. According to the invention, the working frequency of the circuit is kept stable.

Description

Technical Field

[0001] The embodiments disclosed in the present application relate to the field of electronic technology, and more specifically, to a frequency-locked circuit and a DC-DC voltage conversion circuit. Background Art

[0002] The operating frequency of a circuit is a key parameter in circuit design and analysis. Different frequency selections can lead to significant changes in circuit behavior and performance, and have an important impact on the operating state of the circuit. For example, in a buck circuit in ACOT (Adaptive constant on-time) mode, it is difficult to keep the circuit operating frequency stable. Summary of the Utility Model

[0003] According to the embodiments of the present application, the present application provides a frequency-locked circuit and a DC-DC voltage conversion circuit to solve the above problems.

[0004] A first aspect of the present application discloses a frequency-locked circuit applied to a DC-DC voltage conversion circuit, including: a conduction time control circuit, comparing the pulse width of a reference signal and the pulse width of a switching node signal of the voltage conversion circuit, and generating a corresponding control signal; a conduction time generation circuit, connected to the conduction time control circuit, the conduction time generation circuit being configured to generate a conduction duration signal based on the control signal; a driving circuit, connected to the conduction time generation circuit, the driving circuit being configured to drive the voltage conversion circuit based on the conduction duration signal; wherein the pulse width of the conduction duration signal is adjusted to match the pulse width of the reference signal.

[0005] In some embodiments, the conduction time control circuit includes: a phase detector, receiving the reference signal and the switching node signal, comparing the pulse width of the reference signal and the pulse width of the switching node signal, and generating the control signal; wherein, in response to the pulse width of the reference signal being greater than the pulse width of the switching node signal, the control signal is configured to extend the pulse width of the conduction duration signal; in response to the pulse width of the reference signal being less than the pulse width of the switching node signal, the control signal is configured to shorten the pulse width of the conduction duration signal.

[0006] In some embodiments, the phase detector includes: a logic gate circuit that receives the reference signal and the switch node signal and performs a logic operation to obtain an operation result signal; a first trigger module connected to the logic gate circuit that generates a first trigger signal based on the operation result signal; a second trigger module connected to the logic gate circuit through an inverter that generates a second trigger signal based on the inverted signal of the operation result signal; and a counter connected to the first trigger module and the second trigger module that generates the control signal based on the first trigger signal and the second trigger signal.

[0007] In some embodiments, the logic gate circuit includes: a first NOR gate whose first input terminal receives the reference signal; a second NOR gate whose first input terminal receives the switch node signal, the output terminal of the second NOR gate is connected to the second input terminal of the first NOR gate, the output terminal of the first NOR gate is connected to the second input terminal of the second NOR gate, and the output terminal of the first NOR gate serves as the output terminal of the logic gate circuit to output the operation result signal.

[0008] In some embodiments, the first trigger module and the second trigger module are respectively D flip-flops.

[0009] In some embodiments, the on-time generation circuit includes: an error amplifier whose first input terminal receives a reference voltage, whose second input terminal receives the feedback node voltage of the voltage conversion circuit, and generates a corresponding error output result at the output terminal; a comparator connected to the error amplifier and receiving the inductor current of the voltage conversion circuit, comparing the error output result and the inductor current to generate an on trigger pulse; and a third trigger module connected to the comparator and the on-time control circuit, wherein the control signal generated by the on-time control circuit serves as an off trigger pulse, and the third trigger module generates the on-time duration signal based on the on trigger pulse and the off trigger pulse.

[0010] In some embodiments, a compensation circuit is provided between the output terminal and the second input terminal of the error amplifier.

[0011] In some embodiments, the third trigger module is an RS flip-flop.

[0012] In some embodiments, the voltage conversion circuit includes: an upper transistor, a lower transistor, an inductor, a capacitor, and a feedback network. Among them, the gates of the upper transistor and the lower transistor are respectively connected to the drive circuit, and the drain of the upper transistor receives the input voltage; the source of the upper transistor is connected to the drain of the lower transistor, and the connection point serves as a switching node; the drain of the lower transistor is grounded; the switching node is connected to one end of the inductor, and the other end of the inductor is connected to the capacitor and the feedback network, and the connection point serves as the output terminal; the other ends of the capacitor and the feedback network are grounded; the feedback network includes a plurality of resistors connected in series, and the feedback network has a feedback node.

[0013] The second aspect of the present application discloses a DC-DC voltage conversion circuit, including the frequency locking circuit as described in the first aspect.

[0014] The beneficial effects of the present application are as follows: The frequency locking circuit includes a conduction time control circuit, a conduction time generation circuit, and a drive circuit. The conduction time control circuit is connected to the conduction time generation circuit, and the conduction time generation circuit is connected to the drive circuit. Among them, the conduction time control circuit is configured to compare the pulse width of the reference signal and the pulse width of the switching node signal of the voltage conversion circuit, and generate a corresponding control signal. The conduction time generation circuit is configured to generate a conduction duration signal based on the control signal, and the drive circuit is configured to drive the voltage conversion circuit based on the conduction duration signal. That is, the frequency locking circuit makes the pulse width of the obtained conduction duration signal match the pulse width of the reference signal by comparing the pulse width of the reference signal and the pulse width of the switching node signal of the voltage conversion circuit, so that the operating frequency of the circuit remains stable. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The present application will be further described below in conjunction with the drawings and embodiments. In the drawings:

[0016] Figure 1-2 is a schematic structural diagram of the frequency locking circuit according to an embodiment of the present application;

[0017] Figure 3 is a schematic structural diagram of the conduction time control circuit according to an embodiment of the present application;

[0018] Figure 4 is a schematic diagram of the effect of pulse width comparison according to an embodiment of the present application;

[0019] Figure 5 is a schematic diagram of the effect of pulse width comparison according to another embodiment of the present application;

[0020] Figure 6 is a schematic circuit diagram of the phase discriminator according to an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0021] References to "embodiments" in this application mean that the specific features, structures, or characteristics described in connection with the embodiments can be included in at least one embodiment of this application. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0022] The term "and / or" in this application is merely a description of the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this text generally represents an "or" relationship between the associated objects before and after. Furthermore, "plurality" in this text means two or more. In addition, the term "at least one" in this application means any one of a plurality or any combination of at least two of a plurality. For example, including at least one of A, B, and C can represent including any one or more elements selected from the set composed of A, B, and C. In addition, the terms "first", "second", and "third" in this application are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features.

[0023] To enable those skilled in the art to better understand the technical solutions of this application, the technical solutions of this application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0024] Please refer to Figure 1-2 , Figure 1-2 which is a schematic structural diagram of the frequency locking circuit according to an embodiment of this application. The frequency locking circuit 10 is applied to the DC-DC voltage conversion circuit 20, where the DC-DC voltage conversion circuit 20 can be a buck circuit in ACOT (Adaptive constant on-time) mode, that is, a Buck circuit.

[0025] The voltage conversion circuit 20 includes an upper transistor M0, a lower transistor M1, an inductor L, a capacitor C, and a feedback network 201. Among them, the gates of the upper transistor M0 and the lower transistor M1 are respectively connected to the driving circuit 13, and the drain of the upper transistor M0 receives the input voltage VIN; the source of the upper transistor M0 is connected to the drain of the lower transistor M1, and the connection point is used as the switching node SW; the drain of the lower transistor M1 is grounded; the switching node SW is connected to one end of the inductor L, and the other end of the inductor L is connected to the capacitor C and the feedback network 201, and the connection point is used as the output terminal VOUT; the other ends of the capacitor C and the feedback network 201 are grounded.

[0026] Among them, the feedback network 201 includes a plurality of resistors connected in series, and the feedback network 201 has a feedback node x. For example, the feedback network 201 includes a resistor R_FBH and a resistor R_FBL connected in series, and the feedback node x can be set between the resistor R_FBH and the resistor R_FBL.

[0027] In the voltage conversion circuit 20, when the upper transistor M0 is turned on, the output voltage of the voltage conversion circuit 20 rises. When the lower transistor M1 is turned on, the output voltage of the voltage conversion circuit 20 drops. Thus, by controlling the conduction of the upper transistor M0 and the lower transistor M1, the magnitude of the output voltage is controlled.

[0028] In some embodiments, the frequency locking circuit 10 includes a conduction time control circuit 11, a conduction time generation circuit 12, and a driving circuit 13. The conduction time control circuit 11 is connected to the conduction time generation circuit 12, and the conduction time generation circuit 12 is connected to the driving circuit 13.

[0029] The conduction time control circuit 11 is configured to compare the pulse width of a reference signal and the pulse width of a switching node signal of the voltage conversion circuit 20, and generate a corresponding control signal, where the switching node signal is generated at the switching node SW of the voltage conversion circuit 20. The conduction time generation circuit 12 is connected to the conduction time control circuit 11, receives the control signal generated by the conduction time control circuit 11, and is configured to generate a conduction duration signal based on the control signal. The driving circuit 13 is connected to the conduction time generation circuit 12, receives the conduction duration signal generated by the conduction time generation circuit 12, and is configured to drive the voltage conversion circuit 20 to operate based on the conduction duration signal.

[0030] Among them, the conduction time control circuit 11 generates a corresponding control signal according to the comparison result between the pulse width of the reference signal and the pulse width of the switching node signal, and then adjusts the pulse width of the conduction duration signal, so that the pulse width of the conduction duration signal is adjusted to match the pulse width of the reference signal.

[0031] In this embodiment, the frequency locking circuit 10 includes a conduction time control circuit 11, a conduction time generation circuit 12, and a driving circuit 13. The conduction time control circuit 11 is connected to the conduction time generation circuit 12, and the conduction time generation circuit 12 is connected to the driving circuit 13. Among them, the conduction time control circuit 11 is configured to compare the pulse width of the reference signal and the pulse width of the switching node signal of the voltage conversion circuit 20, and generate a corresponding control signal. The conduction time generation circuit 12 is configured to generate a conduction duration signal based on the control signal, and the driving circuit 13 is configured to drive the voltage conversion circuit 20 based on the conduction duration signal. That is, the frequency locking circuit 10 makes the pulse width of the obtained conduction duration signal match the pulse width of the reference signal by comparing the pulse width of the reference signal and the pulse width of the switching node signal of the voltage conversion circuit 20, thereby realizing the locking of the operating frequency of the circuit and keeping the operating frequency of the circuit stable.

[0032] In some embodiments, the conduction time generation circuit 12 includes an error amplifier EA1, a comparator C1, and a third trigger module FF.

[0033] Among them, the first input terminal of the error amplifier EA1 receives the reference voltage VREF, and the second input terminal of the error amplifier EA1 receives the feedback node voltage FB of the voltage conversion circuit 20, that is, the voltage at the feedback node x of the voltage conversion circuit 20, and generates a corresponding error output result EA_OUT at the output terminal of the error amplifier EA1.

[0034] The comparator C1 is connected to the error amplifier EA1. That is, one input terminal of the comparator C1 receives the error output result EA_OUT, and the other input terminal receives the inductor current I_L of the voltage conversion circuit 20, and compares the error output result EA_OUT and the inductor current I_L to generate an enabling trigger pulse.

[0035] The third trigger module FF is connected to the comparator C1 and the conduction time control circuit 11. Among them, the control signal generated by the conduction time control circuit 11 serves as a cut-off trigger pulse. That is, one input terminal of the third trigger module FF receives the enabling trigger pulse output by the comparator C1, and the other input terminal of the third trigger module FF receives the cut-off trigger pulse. Furthermore, the third trigger module FF generates a conduction duration signal based on the enabling trigger pulse and the cut-off trigger pulse, and outputs it to the driving circuit 13.

[0036] In some embodiments, a compensation circuit 121 is provided between the output terminal and the second input terminal of the error amplifier EA1. For example, the amplification factor and frequency characteristics of the error amplifier EA1 are adjusted through the compensation circuit 121 to suppress distortion and interference.

[0037] In some embodiments, the third trigger module FF in the on-time generation circuit 12 is an RS flip-flop. That is, the input terminal S of the RS flip-flop receives the start trigger pulse output by the comparator C1, and the input terminal R of the RS flip-flop receives the cut-off trigger pulse output by the on-time control circuit 11. Then, the RS flip-flop generates an on-time signal based on the start trigger pulse and the cut-off trigger pulse, and outputs the on-time signal from the output terminal Q to the drive circuit 13.

[0038] In some embodiments, as Figure 3 shown, Figure 3 FIG. is a schematic structural diagram of the on-time control circuit according to an embodiment of the present application. The on-time control circuit 11 includes a phase detector 110. The phase detector 110 receives a reference signal and a switch node signal, compares the pulse widths of the reference signal and the switch node signal, and generates a control signal.

[0039] Among them, in response to the pulse width of the reference signal being greater than the pulse width of the switch node signal, the control signal is configured to extend the pulse width of the on-time signal. As Figure 4 shown, Figure 4 FIG. is a schematic diagram of the effect of pulse width comparison according to an embodiment of the present application. The pulse width Tref 1 of the reference signal is greater than the pulse width Ton 1 of the switch node signal. At this time, the control signal is configured to extend the pulse width of the on-time signal. That is, the on-time control circuit 11 generates a control signal to extend the pulse width of the on-time signal. The on-time generation circuit 12 receives the control signal to extend the pulse width of the on-time signal, and then extends the pulse width of the on-time signal based on the control signal, so that the pulse width of the on-time signal matches the pulse width of the reference signal, and then locks the operating frequency of the voltage conversion circuit 20.

[0040] Alternatively, in response to the pulse width of the reference signal being less than the pulse width of the switch node signal, the control signal is configured to shorten the pulse width of the on-time signal. As Figure 5 shown, Figure 5 FIG. is a schematic diagram of the effect of pulse width comparison according to another embodiment of the present application. The pulse width Tref 2 of the reference signal is less than the pulse width Ton 2 of the switch node signal. At this time, the control signal is configured to shorten the pulse width of the on-time signal. That is, the on-time control circuit 11 generates a control signal to shorten the pulse width of the on-time signal. The on-time generation circuit 12 receives the control signal to shorten the pulse width of the on-time signal, and then shortens the pulse width of the on-time signal based on the control signal, so that the pulse width of the on-time signal matches the pulse width of the reference signal, and then locks the operating frequency of the voltage conversion circuit 20.

[0041] In some embodiments, as Figure 6 shown, Figure 6It is a circuit schematic diagram of a phase discriminator according to an embodiment of the present application. The phase discriminator 110 includes a logic gate circuit 111, a first trigger module 112, a second trigger module 113, and a counter 114. The logic gate circuit 111 is connected to the first trigger module 112 and the second trigger module 113, and the first trigger module 112 and the second trigger module 113 are connected to the counter 114.

[0042] Among them, the logic gate circuit 111 receives a reference signal and a switch node signal and performs a logic operation to obtain an operation result signal. That is, the logic gate circuit 111 receives the reference signal and the switch node signal at the switch node x, and performs a logic operation on the reference signal and the switch node signal to obtain an operation result signal. The first trigger module 112 is connected to the logic gate circuit 111. That is, the first trigger module 112 receives the operation result signal output by the logic gate circuit 111 and generates a first trigger signal based on the operation result signal. The second trigger module 113 is connected to the logic gate circuit 111 through an inverter. That is, the second trigger module 113 receives the inverse signal of the operation result signal and generates a second trigger signal based on the inverse signal of the operation result signal. The counter 114 is connected to the first trigger module 112 and the second trigger module 113. That is, the counter 114 receives the first trigger signal and the second trigger signal and generates a control signal based on the first trigger signal and the second trigger signal.

[0043] In some embodiments, the logic gate circuit 111 includes a first NOR gate N1 and a second NOR gate N2. Among them, the first input terminal of the first NOR gate N1 receives the reference signal, the first input terminal of the second NOR gate N2 receives the switch node signal, the output terminal of the second NOR gate N2 is connected to the second input terminal of the first NOR gate N1, the output terminal of the first NOR gate N1 is connected to the second input terminal of the second NOR gate N2, and the output terminal of the first NOR gate N1 serves as the output terminal of the logic gate circuit 111 to output an operation result signal.

[0044] In some embodiments, the first trigger module 112 and the second trigger module 113 are respectively D flip-flops. That is, the input terminal D of the D flip-flop corresponding to the first trigger module 112 receives the operation result signal output by the logic gate circuit, and the output terminal outputs the first trigger signal to the counter 114; the input terminal D of the D flip-flop corresponding to the second trigger module 113 receives the inverse signal of the operation result signal output by the logic gate circuit, and the output terminal outputs the second trigger signal to the counter 114.

[0045] In some embodiments, the DC-DC voltage conversion circuit 20 includes the above-mentioned frequency locking circuit 10. The voltage conversion circuit 20 includes an upper transistor M0, a lower transistor M1, an inductor L, a capacitor C, and a feedback network 201. The voltage conversion circuit 20 further includes a conduction time control circuit 11, a conduction time generation circuit 12, and a drive circuit 13.

[0046] Among them, the gates of the upper transistor M0 and the lower transistor M1 are respectively connected to the driving circuit 13. The driving circuit 13 is connected to the conduction time generating circuit 12, and the conduction time generating circuit 12 is connected to the conduction time control circuit 11. Among them, the conduction time control circuit 11 is configured to compare the pulse width of the reference signal and the pulse width of the switching node signal of the voltage conversion circuit 20, and generate a corresponding control signal. The conduction time generating circuit 12 is configured to generate a conduction duration signal based on the control signal, and the driving circuit 13 is configured to control the conduction of the upper transistor M0 and the lower transistor M1 based on the conduction duration signal.

[0047] The descriptions of the various embodiments above tend to emphasize the differences between the various embodiments. Their similarities or resemblances can be referred to each other. For the sake of brevity, they will not be elaborated herein.

[0048] In several embodiments provided in the present application, it should be understood that the disclosed methods and related devices can be implemented in other ways. For example, the above-described related device embodiments are merely illustrative. For example, the division of modules or units is only a logical function division. In actual implementation, there may be other division methods. For example, units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the couplings or direct couplings or communication disconnections shown or discussed with each other can be through some interfaces. The indirect couplings or communication disconnections of devices or units can be in electrical, mechanical or other forms.

[0049] In addition, in each embodiment of the present application, the functional units can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

[0050] Those skilled in the art will readily appreciate that many modifications and variations can be made to the apparatus and methods while maintaining the teachings of the present application. Therefore, the above disclosure should be considered to be limited only by the scope of the appended claims.

Claims

1. A frequency locking circuit, applied to a DC-DC voltage conversion circuit, characterized in that: include: A conduction time control circuit compares the pulse width of the reference signal with the pulse width of the switch node signal of the voltage conversion circuit and generates a corresponding control signal; A conduction time generating circuit, connected to the conduction time control circuit, wherein the conduction time generating circuit is configured to generate a conduction time length signal based on the control signal; a driving circuit connected to the on-time generating circuit, wherein the driving circuit is configured to drive the voltage conversion circuit based on the on-time signal; The pulse width of the on-time signal is adjusted to match the pulse width of the reference signal.

2. The frequency locking circuit according to claim 1, characterized in that: The on-time control circuit comprises: a phase detector, receiving the reference signal and the switch node signal, comparing the pulse width of the reference signal with the pulse width of the switch node signal, and generating the control signal; Wherein, in response to the pulse width of the reference signal being greater than the pulse width of the switch node signal, the control signal is configured to extend the pulse width of the on-time signal; In response to the pulse width of the reference signal being smaller than the pulse width of the switch node signal, the control signal is configured to shorten the pulse width of the on-time signal.

3. The frequency locking circuit according to claim 2, characterized in that: The phase detector comprises: A logic gate circuit receives the reference signal and the switch node signal and performs a logic operation to obtain an operation result signal; A first trigger module, connected to the logic gate circuit, generating a first trigger signal based on the operation result signal; A second trigger module, connected to the logic gate circuit via an inverter, and generating a second trigger signal based on an inverse signal of the operation result signal; A counter is connected to the first trigger module and the second trigger module, and generates the control signal based on the first trigger signal and the second trigger signal.

4. The frequency locking circuit according to claim 3, characterized in that: The logic gate circuit comprises: a first NOR gate, wherein a first input terminal of the first NOR gate receives the reference signal; A second NOR gate, wherein the first input terminal of the second NOR gate receives the switch node signal, the output terminal of the second NOR gate is connected to the second input terminal of the first NOR gate, the output terminal of the first NOR gate is connected to the second input terminal of the second NOR gate, and the output terminal of the first NOR gate serves as the output terminal of the logic gate circuit to output the operation result signal.

5. The frequency locking circuit according to claim 3, characterized in that: The first trigger module and the second trigger module are respectively D triggers.

6. The frequency locking circuit according to claim 1, characterized in that: The on-time generating circuit comprises: An error amplifier, wherein a first input terminal thereof receives a reference voltage, a second input terminal thereof receives a feedback node voltage of the voltage conversion circuit, and an output terminal thereof generates a corresponding error output result; A comparator connected to the error amplifier and receiving the inductor current of the voltage conversion circuit, and comparing the error output result with the inductor current to generate a start trigger pulse; A third trigger module is connected to the comparator and the on-time control circuit, wherein the control signal generated by the on-time control circuit serves as a cut-off trigger pulse, and the third trigger module generates the on-time signal based on the on-trigger pulse and the cut-off trigger pulse.

7. The frequency locking circuit according to claim 6, characterized in that: A compensation circuit is provided between the output terminal and the second input terminal of the error amplifier.

8. The frequency locking circuit according to claim 6, characterized in that: The third trigger module is an RS trigger.

9. The frequency locking circuit according to claim 1, characterized in that: The voltage conversion circuit comprises: an upper transistor, a lower transistor, an inductor, a capacitor and a feedback network, wherein the gates of the upper transistor and the lower transistor are respectively connected to the driving circuit, and the drain of the upper transistor receives an input voltage; the source of the upper transistor is connected to the drain of the lower transistor, and the connection point thereof serves as a switch node; the drain of the lower transistor is grounded; the switch node is connected to one end of the inductor, and the other end of the inductor is connected to the capacitor and the feedback network, and the connection point serves as an output end; the other ends of the capacitor and the feedback network are grounded; The feedback network includes a plurality of resistors connected in series, and the feedback network has a feedback node.

10. A DC-DC voltage conversion circuit, characterized in that: Comprising the frequency locking circuit as described in any one of claims 1-9.

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