Low-power-consumption CMOS camera power supply system

Abstract

The utility model relates to the field of power supply systems, in particular to a low-power-consumption CMOS camera power supply system. The power supply system comprises a time schedule controller, a multi-path voltage reduction module, a DC-DC power supply module and an integrated circuit module, the time schedule controller is electrically connected to the multi-path voltage reduction module and the DC-DC power supply module, and the multi-path voltage reduction module and the DC-DC power supply module are electrically connected to the integrated circuit module. According to the utility model, through cooperation of the time schedule controller, the multipath step-down module, the DC-DC power supply module and the integrated circuit module, the power supply efficiency is improved, the stability of the output voltage is improved, and thus the service life of the CMOS camera is prolonged.

Description

Technical Field

[0001] The utility model relates to the field of power supply systems, especially the power supply system of a low-power CMOS camera. Background Art

[0002] A CMOS camera is a photosensitive sensor and a very important machine vision device for industrial automation. However, the performance stability and energy consumption efficiency of existing CMOS cameras are not high. The power supply design of low-power industrial cameras is of great significance for improving the performance of cameras, reducing power consumption, and extending service life. Summary of the Utility Model

[0003] The technical problem to be solved by the utility model is: to solve the technical problems described in the background art, the utility model provides a power supply system for a low-power CMOS camera. Through the coordinated operation of a timing controller, a multi-channel buck module, a DC-DC power module, and an integrated circuit module, the power rail efficiency is improved, the stability of the output voltage is improved, and thus the service life of the CMOS camera is extended.

[0004] The technical solution adopted by the utility model to solve its technical problems is:

[0005] A power supply system for a low-power CMOS camera includes a timing controller, a multi-channel buck module, a DC-DC power module, and an integrated circuit module. The timing controller is electrically connected to the multi-channel buck module and the DC-DC power module respectively, and both the multi-channel buck module and the DC-DC power module are electrically connected to the integrated circuit module.

[0006] Specifically, the timing controller is connected to a DC power adapter or an active Ethernet.

[0007] Specifically, a synchronous buck regulator for providing efficient output is electrically connected to the multi-channel buck module.

[0008] Specifically, the synchronous buck regulator has four channels.

[0009] Specifically, input capacitors C216, C217, C218, C219, output capacitors C223, C224, C225, C226, inductors L1, L2, L3, and L4 are electrically connected to the multi-channel buck module.

[0010] Specifically, the integrated circuit module is an FPGA integrated circuit.

[0011] Specifically, filter capacitors C227, C228, C229, C230, and C231 are connected to the timing controller.

[0012] The beneficial effects of the present utility model are as follows: The present utility model provides a low-power CMOS camera power supply system. Through the coordinated operation of the timing controller, multi-channel buck module, DC-DC power module, and integrated circuit module, the power rail efficiency is improved, the stability of the output voltage is enhanced, thereby prolonging the service life of the CMOS camera. Brief Description of the Drawings

[0013] The present utility model will be further described below in conjunction with the drawings and embodiments.

[0014] Figure 1 is the structural schematic diagram of the present utility model;

[0015] Figure 2 is the circuit diagram of the multi-channel buck module of the present utility model;

[0016] Figure 3 is the circuit diagram of the DC-DC power module of the present utility model;

[0017] Figure 4 is the circuit diagram of the timing controller of the present utility model;

[0018] In the figure, 1. DC power adapter, 2. Timing controller, 3. Multi-channel buck module, 4. DC-DC power

[0019] module, 5. Integrated circuit module, 6. Active Ethernet. Detailed Embodiment

[0020] The present utility model will now be further described in detail in conjunction with the drawings. These drawings are all simplified schematic diagrams, only illustrating the basic structure of the present utility model in a schematic manner, so they only show the components related to the present utility model.

[0021] Figure 1 is the structural schematic diagram of the present utility model; Figure 2 is the circuit diagram of the multi-channel buck module of the present utility model;

[0022] Figure 3 is the circuit diagram of the DC-DC power module of the present utility model; Figure 4 is the circuit diagram of the timing controller of the present utility model.

[0023] As shown in the attached Figure 1 figure, a low-power CMOS camera power supply system includes a timing controller 2, a multi-channel buck module 3, a DC-DC power module 4, and an integrated circuit module 5. The timing controller 2 is electrically connected to the multi-channel buck module 3 and the DC-DC power module 4 respectively, and both the multi-channel buck module 3 and the DC-DC power module 4 are electrically connected to the integrated circuit module 5.

[0024] The power supply system of this CMOS camera consists of input - conversion - output. To achieve low power consumption of the entire CMOS camera, the power efficiency of stepping down the input voltage from 12V is higher than that from 24V. The voltage input is supplied by active Ethernet 6 or a DC power adapter 1 at 12V. When the timing controller 2 receives a signal, it controls the power - on of the multi - step - down module 3 and the DC - DC power module 4 by outputting the PWR_EN signal. After receiving the signal, the multi - step - down module 3 immediately steps down the input 5V voltage and, according to the ratio of the connected resistors, reduces the voltage to the required voltages of 1.0V, 1.35V, 1.8V, 2.5V, and 3.3V for each channel of the FPGA.

[0025] The GMAX0505 CMOS image sensor is selected. This type of image sensor usually requires three power rails with a specific sequence, which are used for the analog part at 3.3V, the pixel part (or interface part) at 3.3V or 1.8V, and the digital part at 1.8V or 1.2V respectively. To improve the noise performance of the CMOS image sensor, large bypass capacitors are sometimes placed in front of the power pins of the CMOS image sensor. The noise performance of the CMOS image sensor can also be improved by reducing the jitter of each power rail. Generally speaking, the analog power rail is the most sensitive to noise; the pixel power rail is also sensitive to noise. Improving the power rail efficiency can thus improve the heat dissipation performance of the CMOS image sensor and avoid the degradation of the color filter effect.

[0026] The timing controller 2 is connected to the DC power adapter 1 or active Ethernet 6.

[0027] The multi - step - down module 3 is powered on and connected to a synchronous buck regulator for providing efficient output.

[0028] The channels of the synchronous buck regulator are four - channel.

[0029] As shown in the Figure 2 attachment, the multi - step - down module 3 is powered on and connected to input capacitors C216, C217, C218, C219, output capacitors C223, C224, C225, C226, inductors L1, L2, L3, and L4.

[0030] Four synchronous buck regulators can provide high-efficiency output during light and heavy load operations. Increasing the input capacitors C216, C217, C218, C219, output capacitors C223, C224, C225, C226 filters the ripple noise on the input voltage, provides additional charge, and enhances the stability of the output voltage. Connecting 2.2uH inductors L1, L2, L3, L4 to the output terminal filters the power supply output, suppresses high-frequency noise and electromagnetic interference signals, and at the same time stabilizes the voltage at the output terminal, thereby improving the power supply load capacity and system reliability. Calculate the resistance ratios (R84 / R85, R86 / R87, R88 / R89, R90 / R91), compare the FB pin voltage with the internal FB reference value (VFB) to obtain the voltage required by integrated circuit module 5.

[0031] Integrated circuit module 5 is an FPGA integrated circuit. The FPGA integrated circuit selects Fudan Microelectronics JFMK50, which has 52K logic cells, 2700kb high-performance RAM modules, 210 available I / Os, and a core voltage of 1.0V.

[0032] As shown in the Figure 3 attachment, the input voltage range of the DC-DC power module 4 is 3V to 5.75V, the maximum output current is 3A, and the adjustable range of the output voltage is 0.8V to 3.7V. It has input undervoltage, output short circuit, output overcurrent, and over-temperature protection functions. When the input voltage is lower than the undervoltage protection point, the DC-DC power module 4 will turn off, and when the input voltage reaches the input undervoltage recovery point, the DC-DC power module 4 will restart. The DC-DC power module 4 adjusts the output voltage by externally connecting a resistor between the FB pin and the GND pin, and can achieve an adjustable output voltage range of 0.8V to 3.7V. The pull-up resistor value between Vos and FB is fixed at 20kΩ.

[0033] As shown in the Figure 4 attachment, the timing controller 2 is connected with filter capacitors C227, C228, C229, C230, C231.

[0034] The timing controller 2 can provide sequential control for the power-on and power-off of multi-channel power supplies. The input and output terminals are connected to 0.1uF filtering capacitors C227, C228, C229, C230, and C231 to filter the input and output signals, reduce interference, and ensure the integrity of signal transmission quality. The device type is selected as TPK1032, which is enabled when the EN pin goes high. The three output channels go high respectively after a selected delay period, in the sequence of FLAG1 - FLAG2 - FLAG3; when disabled when the EN pin goes low, the three output channels go low one by one in the selected order after the selected delay period. The output signal controls the buck module through the PWR_EN signal. At the same time, adding 0.1uF filtering capacitors C229, C230, and C231 for input and output ceramic capacitors and pull-up resistors of 100K: R94~R96 can reduce the noise of the output signal, thereby providing higher accuracy of inter-channel delay.

[0035] Inspired by the above ideal embodiments of the present invention, through the above description, relevant staff can completely make various changes and modifications without departing from the technical idea of this invention. The technical scope of this invention is not limited to the content in the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A low power CMOS camera power supply system, characterized in that: The invention comprises a timing controller (2), a multi-channel voltage reduction module (3), a DC-DC power supply module (4), and an integrated circuit module (5); the timing controller (2) is electrically connected to the multi-channel voltage reduction module (3) and the DC-DC power supply module (4), respectively; and the multi-channel voltage reduction module (3) and the DC-DC power supply module (4) are both electrically connected to the integrated circuit module (5).

2. The low power consumption CMOS camera power supply system according to claim 1, characterized in that: The timing controller (2) is connected to a DC power adapter (1) or an active Ethernet (6).

3. The low power consumption CMOS camera power supply system according to claim 1, characterized in that: The multi-channel buck module (3) is electrically connected to a synchronous buck regulator for providing high-efficiency output.

4. The low power consumption CMOS camera power supply system according to claim 3, characterized in that: The synchronous buck regulator has four channels.

5. The low power consumption CMOS camera power supply system according to claim 1, characterized in that: The multi-channel buck module (3) comprises an input capacitor C216, an input capacitor C217, an input capacitor C218, an input capacitor C219, an output capacitor C223, an output capacitor C224, an output capacitor C225, an output capacitor C226, an inductor L1, an inductor L2, an inductor L3, an inductor L4, and a chip U18; Input capacitor C216, input capacitor C217, input capacitor C218, and input capacitor C219 are connected in parallel to each other and connected to chip U18, output capacitor C223 is connected to inductor L1, output capacitor C224 is connected to inductor L2, output capacitor C225 is connected to inductor L3, output capacitor C226 is connected to inductor L4, inductor L1, inductor L2, inductor L3, and inductor L4 are all connected to chip U18.

6. The low power consumption CMOS camera power supply system according to claim 1, characterized in that: The integrated circuit module (5) is a FPGA integrated circuit.

7. The low power consumption CMOS camera power supply system according to claim 1, characterized in that: The timing controller (2) comprises a filter capacitor C227, a filter capacitor C228, a filter capacitor C229, a filter capacitor C230, a filter capacitor C231, and a chip U19; Filter capacitor C227, filter capacitor C228, filter capacitor C229, filter capacitor C230, and filter capacitor C231 are all connected to chip U19.

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