Semiconductor structure

Abstract

The semiconductor structure includes a substrate, a first transistor, a second transistor, and a third transistor. The first transistor is located on the electrostatic discharge circuit region of the substrate. The second transistor is located on a first buffer circuit region of the substrate, where the first buffer circuit region is located on a first side of the electrostatic discharge circuit region from a top view. The first transistor, the second transistor and the third transistor are parts of an input / output circuit of a first wafer, and the second buffer circuit region is located on a second side opposite to the first side of the electrostatic discharge circuit region from a top view.

Description

Technical Field

[0001] This disclosure relates to a semiconductor structure. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in integrated circuit materials and design have produced generation after generation of integrated circuits, with each generation of circuits smaller and more complex than the previous one. However, these advances have increased the complexity of processing and manufacturing integrated circuits, and the same developments in integrated circuit processing and manufacturing are necessary to achieve these advances.

[0003] In the process of integrated circuit evolution, the functional density (i.e., the number of interconnecting elements per wafer area) generally increases, while the geometric dimensions (i.e., the smallest components (or lines) that can be created using a manufacturing process) have decreased. This process of scaling down generally provides benefits by increasing production efficiency and reducing related costs. This scaling down also results in relatively high power dissipation values, which can be addressed by using low-power dissipation elements such as complementary metal oxide semiconductor (CMOS) elements. Summary of the Utility Model

[0004] In some embodiments, the semiconductor structure includes a substrate, a first transistor, a second transistor, and a third transistor. The first transistor is located on an electrostatic discharge circuit region of the substrate. The second transistor is located on a first buffer circuit region of the substrate, wherein in a top view, the first buffer circuit region is located on a first side of the electrostatic discharge circuit region. The third transistor is located on a second buffer circuit region of the substrate, wherein the first transistor, the second transistor, and the third transistor are part of an input / output circuit of a first wafer, and in a top view, the second buffer circuit region is located on a second side opposite to the first side of the electrostatic discharge circuit region.

[0005] In some embodiments, the semiconductor structure includes a substrate, a first transistor, a second transistor, a third transistor, and a first metal wire. The first transistor is located on the substrate. The second transistor is located on the substrate. The first transistor and the second transistor are part of a buffer circuit in an input / output circuit. The third transistor is located on the substrate. The third transistor is between the first transistor and the second transistor in a cross-sectional view, and the third transistor is part of an electrostatic discharge circuit in the input / output circuit. The first metal wire extends horizontally from above the first transistor across to above the second transistor. The first metal wire is electrically connected to the first transistor, the second transistor, and the third transistor.

[0006] In some embodiments, a semiconductor structure includes a substrate, a plurality of first source / drain regions, a plurality of second source / drain regions, a plurality of third source / drain regions, a plurality of first gate strip structures, a plurality of second gate strip structures, a plurality of third gate strip structures, and metal lines. The plurality of first source / drain regions are located on a first buffer circuit region of the substrate. The plurality of second source / drain regions are located on a second buffer circuit region of the substrate. The plurality of third source / drain regions are located on an electrostatic discharge (ESD) circuit region of the substrate. The first source / drain regions, the second source / drain regions, and the third source / drain regions are part of an input / output circuit of a first wafer, and in a top view, the ESD circuit region is located between the first buffer circuit region and the second buffer circuit region. The plurality of first gate strip structures are located on the first buffer circuit region. In a top view, the plurality of first gate strip structures are interleaved with the plurality of first source / drain regions. The plurality of second gate strip structures are located on the second buffer circuit region. In a top view, the plurality of second gate strip structures are interleaved with the plurality of second source / drain regions. The plurality of third gate strip structures are located on the ESD circuit region. In a top view, the plurality of third gate strip structures are interleaved with the plurality of third source / drain regions. The metal lines are located on the first buffer circuit region, the second buffer circuit region, and the ESD circuit region. The metal lines are electrically connected to one of the plurality of first source / drain regions, one of the plurality of second source / drain regions, and one of the plurality of third source / drain regions. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1A FIG. 1 shows a schematic block diagram of an integrated circuit (IC) device in accordance with some embodiments of the present disclosure;

[0009] Figure 1B FIG. 2 shows a schematic top view circuit diagram of a buffer circuit of an electrostatic discharge (ESD) protection circuit in accordance with some embodiments of the present disclosure;

[0010] Figure 1C FIG. 3 shows a schematic top view circuit diagram of a buffer circuit of an electrostatic discharge protection circuit in accordance with some embodiments of the present disclosure;

[0011] Figure 2A A top view layout pattern of an integrated circuit structure including a buffer circuit with an electrostatic discharge protection circuit according to some embodiments of the present disclosure is shown;

[0012] Figure 2B A top view layout pattern of an integrated circuit structure including a buffer circuit with an electrostatic discharge protection circuit according to some embodiments of the present disclosure is shown;

[0013] Figure 3A A schematic cross-sectional view of an integrated circuit structure including a buffer circuit with an electrostatic discharge protection circuit on a substrate according to some embodiments of the present disclosure is shown;

[0014] Figures 3B to 3K Cross-sectional views of the integrated circuit structure obtained according to some embodiments of the present disclosure at reference cross-sections B1 - B1', B2 - B2', B3 - B3', B4 - B4', B5 - B5' and B6 - B6' in Figure 2A are shown;

[0015] Figure 4 A top view layout pattern of an integrated circuit structure including a buffer circuit with an electrostatic discharge protection circuit on a substrate according to some embodiments of the present disclosure is shown;

[0016] Figures 5A to 5F A schematic cross-sectional view of an integrated circuit structure at an intermediate stage of the manufacturing process according to some embodiments of the present disclosure is shown;

[0017] Figure 6 A schematic diagram of an electronic design automation (EDA) system according to some embodiments of the present disclosure;

[0018] Figure 7 A block diagram of an integrated circuit manufacturing system and related manufacturing processes according to some embodiments of the present disclosure.

[0019]

Symbol Description

[0020] 50: Substrate

[0021] 10A: Electrostatic discharge protection circuit region

[0022] 10B, 10C:

[0023] : First buffer circuit region, second buffer circuit region

[0024] 10D: First conductivity type element region

[0025] 10E: Second conductivity type element region

[0026] 50A: Well of the second conductivity type

[0027] 50B: Well of the first conductivity type

[0028] 100: Integrated circuit element

[0029] 100a: First wafer

[0030] 100b: Second wafer

[0031] 101a, 101b, 101c, 101d: Input / output circuit

[0032] 102a, 102b: Functional circuit

[0033] 103a, 103b, 103c: Buffer circuit

[0034] 104a, 104b, 104c: Protection circuit

[0035] 105a, 105b: Pad structure

[0036] 106a: Inverter

[0037] 110: Transistor

[0038] 111: Channel region

[0039] 112: Gate structure

[0040] 112a: Gate dielectric layer

[0041] 112b: Gate electrode layer

[0042] 113: Shallow trench isolation region

[0043] 114: Cut polycrystalline silicon structure

[0044] 115: Gate spacer structure

[0045] 116, 117: Interlayer dielectric layer

[0046] 118: Interconnection structure

[0047] 120: Source / drain contact structure

[0048] 122: Sacrificial gate structure

[0049] 122a: Sacrificial gate dielectric layer

[0050] 122b: Sacrificial gate

[0051] 130: Source / drain via

[0052] 132: Gate via

[0053] 140, 142, 150, 160: Metal wires

[0054] 145, 155: Through holes

[0055] 1600: Electronic design automation system

[0056] 1602: Processor

[0057] 1604: Storage medium

[0058] 1606: Instruction

[0059] 1607: Design layout

[0060] 1608: Bus

[0061] 1609: Design rule check platform

[0062] 1610: Input / output interface

[0063] 1612: Network interface

[0064] 1614: Network

[0065] 1616: User interface

[0066] 1620, 1750: Integrated circuit manufacturing end

[0067] 1622: Integrated circuit manufacturing tool

[0068] 1630, 1730: Mask shop

[0069] 1632: Mask manufacturing tool

[0070] 1700: Integrated circuit manufacturing system

[0071] 1720: Design end

[0072] 1722: Design layout

[0073] 1732: Data preparation

[0074] 1744: Mask manufacturing

[0075] 1745: Photomask

[0076] 1752: Wafer manufacturing

[0077] 1753: Wafer

[0078] B1 - B1', B2 - B2', B3 - B3', B4 - B4', B5 - B5' and B6 - B6': Reference section I: Signal

[0079] IE, OE: Enable signals

[0080] L1, L3: Lengths

[0081] L2: Dimensions

[0082] M0, M1, M2, M3, M4, M5, M6: Layers

[0083] Rx: Receiver circuit

[0084] S / D: Source / drain regions

[0085] Tx: Transmitter circuit

[0086] Vdd, Vss: Power supply voltage lines Detailed implementation manners

[0087] The following disclosure provides many different implementation manners or examples for implementing different features of the provided subject matter. Specific examples of components and configurations are illustrated below to simplify the present disclosure. Of course, these are only examples and are not intended to be restrictive. For example, in the following illustrations, the formation of a first feature above or on a second feature may include an implementation manner in which the first and second features are formed in direct contact, and may also include an implementation manner in which additional features may be formed between the first and second features such that the first and second features are not in direct contact. In addition, in various examples, the present disclosure may repeatedly reference numbers and / or letters. This repetition is for simplicity and clarity purposes and does not itself specify the relationship between the various implementation manners and / or configurations discussed.

[0088] In addition, for ease of illustration, spatial relative terms such as "beneath", "below", "lower", "above", "upper", and the like may be used herein to depict the relationship of one element or feature to another element or feature as illustrated in the figures. In addition to the orientation depicted in the figures, the plurality of spatial relative terms are intended to also cover different orientations of the elements during use or operation. The elements may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative illustration words used herein may be correspondingly interpreted. As used herein, "about", "substantially", "approximate", or "substantially" may mean within 20%, within 10%, or within 5% of a given value or range. However, those of ordinary skill in the art will understand that the values or ranges recited throughout the illustrations are merely examples and may decrease as the integrated circuit is scaled down. The values given in the present disclosure are approximate, indicating that if not explicitly stated, terms such as "about", "substantially", "approximate", or "substantially" can be inferred.

[0089] Unless otherwise defined, all terms (including technical and scientific terms) used in this disclosure have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It should also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0090] In three-dimensional integrated circuit (3DIC) packages, such as Chip-on-Wafer-on-Substrate (CoWoS), Integrated Fan-Out (InFO) wafer-level packages, System on Integrated Chips (SoIC) packages, etc., the wire widths and vias of the input / output (I / O) circuits between die-to-die need to meet electrostatic discharge (ESD) standards to manage electromigration (EM) issues. One problem is first connecting the die-to-die pads to the ESD circuit and then to the buffer circuit, which creates a horizontal current path, leading to current crowding and worsening of the electromigration situation.

[0091] Accordingly, various embodiments of this disclosure provide a method for improving the performance of die-to-die input / output circuits in three-dimensional integrated circuits. The input / output circuit can integrate a buffer circuit and an electrostatic discharge protection structure. The driving force of the buffer circuit (e.g., 16 PMOS and 16 NMOS transistors) can be divided into two sub-buffer regions (e.g., Figure 2A buffer circuit regions 10B and 10C shown in Figure 2A ), each region having half of the total driving force (e.g., 8 PMOS and 8 NMOS). Especially in the output stage, the transistors in the sub-buffer regions connect their source / drain regions to the corresponding source / drain regions in the electrostatic discharge protection region through horizontal metal lines. These two sub-buffer regions can be located on opposite sides of the electrostatic discharge protection region (e.g.,

[0092] electrostatic discharge protection circuit region 10A shown in Figures 1A to 1C ). This arrangement can split and shorten the horizontal current path, reducing the current path length to 50% to 75% of the original length, thereby reducing the output capacitance load and enhancing the electromigration resistance. Figure 1A FIG. Figure 1BDepicts a schematic plan view of a buffer circuit 103a incorporating an electrostatic discharge (ESD) protection circuit 104a within an integrated circuit element 100. Figure 1C Depicts a schematic plan view of a buffer circuit 103b incorporating an electrostatic discharge protection circuit 104b within an integrated circuit element 100.

[0093] As Figure 1A shown, the integrated circuit element 100 includes a first wafer 100a and a second wafer 100b, which are electrically and / or physically connected to each other. In some embodiments, the first wafer 100a and the second wafer 100b are stacked on top of each other and physically joined and electrically connected in a three-dimensional integrated circuit. In some embodiments, the first wafer 100a and the second wafer 100b are placed side by side on another wafer or substrate and electrically connected through the substrate. In some embodiments, the integrated circuit element 100 includes more than two wafers that are electrically and / or physically connected. In some embodiments, the integrated circuit element 100 includes only one wafer, such as the first wafer 100a, while the other wafer, such as the second wafer 100b, is omitted. In Figure 1A the example configuration, the configuration of the second wafer 100b is similar to that of the first wafer 100a. The first wafer 100a is illustrated in detail herein, and the detailed illustration of the second wafer 100b is omitted. The first wafer 100a may include one or more functional circuits and one or more input / output (I / O) circuits electrically connected to the one or more functional circuits. In Figure 1A it, a representative input / output circuit 101a and a representative functional circuit 102a of the first wafer 100a are illustrated. In some embodiments, the input / output circuit 101b and the functional circuit 102b of the second wafer 100b may correspond to the input / output circuit 101a and the functional circuit 102a of the first wafer 100a.

[0094] In some embodiments, the functional circuit 102a may be configured to perform a predetermined function of the integrated circuit element 100, such as data processing or data storage. One or more circuits, logics, or elements included in the functional circuit 102a include, but are not limited to, AND, OR, NAND, NOR, XOR, INV, OR-AND-Invert (OAI), MUX, Flip-flop, BUFF, Latch, delay, clock, memory, etc. The circuits, logics, or elements included in the functional circuit 102a include functional transistors or core transistors, which need to be protected from antenna effects during the manufacturing process of the integrated circuit element 100. The transistors in the functional circuit 102a and the transistors in other circuits illustrated herein include, but are not limited to, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor transistors (CMOS), P-channel metal-oxide-semiconductor (PMOS), N-channel metal-oxide-semiconductor (NMOS), bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, P-channel and / or N-channel field-effect transistors (PFETs / NFETs), FinFETs, planar MOS transistors with raised source / drain regions, nanosheet transistors, nanowire transistors, etc.

[0095] In some embodiments, the input / output circuit 101a may be electrically connected to the functional circuit 102a and may be configured as an interface between the functional circuit 102a on the first wafer 100a and the external circuits of the first wafer 100a. In Figure 1A an example configuration, the input / output circuit 101a may include a buffer circuit 103a and an electrostatic discharge protection circuit 104a, where the buffer circuit 103a may include a receiving circuit Rx (also referred to as an "input circuit") and a transferring circuit Tx (also referred to as an "output circuit"), all of which are electrically connected to the input / output pad structure 105a. In some embodiments, the buffer circuit 103b, the electrostatic discharge protection circuit 104b, and the pad structure 105b of the second wafer 100b may correspond to the buffer circuit 103a, the electrostatic discharge protection circuit 104a, and the pad structure 105a of the first wafer 100a. In some embodiments, the pad structure 105a may be interchangeably referred to as a metal pad structure, a pad structure, or a wafer-to-wafer pad structure.

[0096] The buffer circuit 103a can be used to enhance and stabilize the signals transmitted inside and outside the wafer 100a. In some embodiments, the buffer circuit 103a may condition the signals, such as inverting them (such as the inverter buffer shown in Figure 1B ), or providing multiple states (such asFigure 1C as shown in the three-state buffer). In some embodiments, the buffer circuit 103a can provide isolation between circuits and protect a certain circuit from potential hazards that the connected circuit may bring. In some embodiments, the buffer circuit 103a can be referred to as an electrostatic discharge victim.

[0097] In some embodiments, the receiving circuit Rx in the buffer circuit 103a can be configured to send a signal from the functional circuit 102a to the pad structure 105a. The receiving circuit Rx can be configured to receive an input enable signal IE. The receiving circuit Rx can be enabled in a certain logic state of the input enable signal IE to send the signal to the functional circuit 102a and disabled in a different logic state without sending the signal to the functional circuit 102a. The transmitting circuit Tx in the buffer circuit 103a can be configured to send the output signal of the functional circuit 102a to the pad structure 105a. The transmitting circuit Tx can be configured to receive an output enable signal OE. The transmitting circuit Tx can be enabled in a certain logic state of the output enable signal OE and disabled in a different logic state. Examples of signals input or output from the pad structure 105a include but are not limited to data, power, clock, control, etc. Examples of at least one or more of the receiving circuit Rx or the transmitting circuit Tx include but are not limited to buffers, latches, level shifters, etc.

[0098] In some embodiments, the electrostatic discharge protection circuit 104a can be configured to protect other circuits electrically connected to the pad structure 105a, including the functional circuit 102a, from electrostatic discharge events occurring on the pad structure 105a during the operation or processing of the first wafer 100a or the integrated circuit element 100. By way of example and not limitation, the electrostatic discharge protection circuit 104a can use components such as diodes to clamp the voltage at a safe level during an electrostatic discharge event, preventing the voltage spike from reaching and damaging sensitive components in the wafer 100a. In some embodiments, the electrostatic discharge protection circuit 104a can be used to divert excessive current from sensitive circuit elements. Examples of the electrostatic discharge protection circuit 104a include but are not limited to diodes, grounded-gate NMOS (ggNMOS), silicon-controlled rectifier (SCR), etc. In some embodiments, the transistors in the electrostatic discharge protection circuit 104a can be larger and / or have a different configuration than the functional transistors or core transistors of the functional circuit 102a to withstand and handle the high voltage and / or current of the electrostatic discharge event.

[0099] In some embodiments, the first wafer 100a is electrically connected to the second wafer 100b through one or more wafer-to-wafer interconnections. In Figure 1A , a representative wafer-to-wafer interconnection is shown and is electrically connected to the pad structure 105a of the first wafer 100a and the corresponding pad structure 105a of the second wafer 100b. Thus, the pad structure 105a of the first wafer 100a is electrically connected to the corresponding pad structure 105b of the second wafer 100b through the wafer-to-wafer interconnection. In some embodiments, the wafer-to-wafer interconnection can be a through-silicon via (TSV) of one or more wafers in the integrated circuit element 100.

[0100] Refer to Figure 1B and Figure 1C . Figure 1B and Figure 1C illustrate different configurations of the input / output circuit 101a within the wafer 100a, with an emphasis on the variations in the buffer circuit 103a. As Figure 1B shown, the buffer circuit 103a can include an inverter 106a. The inverter 106a can be a basic digital logic circuit for flipping the state of an input signal; if the input is high (e.g., 1), the output is low (e.g., 0), and vice versa. The inverter 106a in the buffer circuit 103a can include at least a pair of transistors (e.g., an NMOS transistor and a PMOS transistor). The electrostatic discharge protection circuit 104a can be used to protect the inverter 106a and other components from electrostatic discharge damage. The pad structure 105a can serve as the output interface of the buffer circuit. In this case, the output of the inverter 106a can be routed to the pad structure 105a to provide signal inversion for external communication or further processing within the wafer 100a.

[0101] As Figure 1CAs shown, the buffer circuit 103a may include a tri-state buffer. The tri-state buffer can be in one of three states: high, low, or high impedance, thereby further controlling and interacting with the bus system or shared signal lines. The transistor arrangement in the tri-state buffer may include additional transistors controlled by an enable signal to reach the high impedance state. Signals (e.g., output enable (OE) and output enable bar (OEB)) can control the state of the tri-state buffer. Output enable OE may activate the buffer (allowing normal operation), while output enable bar OEB may place the buffer in the high impedance state, disconnecting it from the output pad structure 105a. The electrostatic discharge protection circuit 104a can be used to protect the tri-state buffer and other components from electrostatic discharge damage. The pad structure 105a can serve as an interface for the tri-state buffer output. In this case, depending on the state controlled by output enable OE and output enable bar OEB, the pad structure 105a may receive a high or low signal, or be electrically disconnected from the buffer circuit 103a.

[0102] Reference Figure 2A and 3A to Figure 3K . Figure 2A FIG. shows a top view layout pattern of the input / output circuit 101a, which includes the buffer circuit 103a and the electrostatic discharge protection circuit 104a. Figure 3A FIG. shows a conceptual cross-sectional view of the input / output circuit 101a including the buffer circuit 103a and the electrostatic discharge protection circuit 104a. Figures 3B to 3K FIG. shows a cross-sectional view of the input / output circuit 101a obtained from the reference cross-sections B1-B1', B2-B2', B3-B3', B4-B4', B5-B5', and B6-B6' in Figure 2A .

[0103] As Figure 2A and Figure 3A shown, the input / output circuit 101a includes an electrostatic discharge protection circuit region 10A, a first buffer circuit region 10B, and a second buffer circuit region 10C, all of which are disposed on a substrate 50 (see Figure 3A ). The electrostatic discharge protection circuit region 10A is located between the first and second buffer circuit regions 10B and 10C. It should be noted that the configurations of the electrostatic discharge protection circuit region 10A and the first and second buffer circuit regions 10B and 10C are only examples and do not limit the scope of the present disclosure. In other words, the transistors in the electrostatic discharge protection circuit region 10A can be interposed between the transistors 110 in the first buffer circuit region 10B and the second buffer circuit region 10C (see Figure 3B ). As an example but not limiting the present disclosure, each of the first and second buffer circuit regions 10B and 10C may include at least one inverter.

[0104] The cushion structure 105a (see Figure 3A ) is first connected to the electrostatic discharge circuit 104a on the electrostatic discharge protection circuit region 10A, and then routed to the buffer circuit 103a located on the first and second buffer circuit regions 10B / 10C. This means that for the buffer circuit 103a, the initial connection can be made with the electrostatic discharge protection circuit 103a. This connection sequence may result in a horizontal current path from the cushion structure 105a to the emitting elements in the first and second buffer circuit regions 10B / 10C (e.g., Figure 3A the metal wire 160 shown in). The cushion structure 105a is electrically connected to the electrostatic discharge protection circuit 103a (e.g., Figure 3B the source / drain region S / D of the transistor 110 in the electrostatic discharge protection region 10A shown in) through various interconnection means such as hybrid bumps, microbumps (u-bumps), or through-silicon vias (TSVs). In Figure 3A the output stage, the source / drain region S / D of the transistor 110 in the electrostatic discharge protection region 10A is electrically connected to the source / drain region S / D of another transistor 110 (as an emitting element) in the buffer circuit regions 10B / 10C through the horizontal metal wire 160. Conversely, for the input stage, the source / drain region S / D of the transistor 110 in the electrostatic discharge protection region 10A is electrically connected to the gate structure of another transistor 110 (as a receiver) in the buffer circuit regions 10B / 10C.

[0105] In some embodiments, the rise and fall times of the signals in the circuit should be less than one-sixth of the operating period. This requirement may indicate that the operating speed of the wafer-to-wafer input / output circuit may be limited by electromigration problems. In some embodiments, the speed of the wafer-to-wafer input / output circuit may be limited by electromigration in the horizontal lines (e.g., Figure 3A the metal wire 160 shown in), where there may be a potential problem of current congestion in the horizontal lines.

[0106] The buffer circuit 103a can be constructed in a semiconductor structure divided into two sub-buffer regions (e.g., the first and second buffer circuit regions 10B and 10C). By placing the first and second buffer circuit regions 10B and 10C opposite the electrostatic discharge protection region 10A, the metal wires (e.g., Figure 3AThe horizontal current path in the metal line 160 shown is segmented and shortened. This reduction in the current path length (to 50% to 75% of the original length) can alleviate problems associated with current congestion and electromigration. In some embodiments, the shorter horizontal metal lines may result in a reduced output capacitance load. This can enhance electromigration resistance, thereby increasing the speed and drive capability under heavy loads, and further improving the electromigration / IR-drop (EMIR) problem without reducing the signal rise / fall time. Therefore, the input / output circuit 101a can reduce the stress caused by electromigration by more than 50%, such as 50, 55, 60, 65, 70, 75, 80, 85, 90, and 95%. By reducing the stress, the input / output circuit 101a can extend the circuit life. In addition, the input / output circuit 101a can achieve an electromigration relaxation greater than 1.7 times, indicating that the circuit has a stronger resistance to the destructive effects of electrons. In addition, the input / output circuit 101a can also provide a speed boost greater than 1.15 times.

[0107] In addition, the total driving force of the buffer circuit 103a consists of a certain number of PMOS and NMOS transistors (e.g., 12 PMOS transistors and 12 NMOS transistors) and is divided into two sub-buffer regions. Each sub-buffer region has a portion of the total driving force (e.g., Figure 2A the 6 PMOS transistors and 6 NMOS transistors shown) and has its own set of transistors. The first and second buffer circuit regions 10B and 10C are located opposite the electrostatic discharge protection region 10A.

[0108] Specifically, as Figure 2A and Figure 3A shown, the input / output circuit 101a may include transistors 110 within a substrate 50 (see Figure 2A ) above a first conductivity type element region 10D (see Figure 2A ) and a second conductivity type element region 10E (see Figure 3A ). In some embodiments, the transistors 110 in the first conductivity type element region 10D may be PMOSFET transistors with a silicon channel region, while the transistors in the second conductivity type element region 10E may be NMOSFET transistors with a silicon channel region. In some embodiments, the transistors may be GAA FETs, so the silicon channel regions of the NMOS and PMOS transistors can be formed by a semiconductor sheet (not shown). In some embodiments, a second conductivity type well 50A (see Figure 2A ) and a first conductivity type well 50B (see Figure 2A)。By way of example and not limitation of the scope of this disclosure, the second conductivity type well 50A may be an n-well, and the first conductivity type well 50B may be a p-well.

[0109] The transistor 110 may include a channel region 111 formed above the first and second conductivity type wells 50B and 50A (see Figure 2A ). The transistor 110 may further include a gate structure 112 located within the electrostatic discharge protection circuit region 10A and the buffer circuit regions 10B and 10C and extending in the Y direction. The gate structure 112 may include a gate dielectric layer 112a surrounding the channel region 111 (see Figure 5E and Figure 5F ), and a gate electrode layer 112b formed above the gate dielectric layer 112a (see Figure 5E and Figure 5F ). In some embodiments, the gate structure 112 may alternatively be referred to as a functional gate, a gate strip structure, a gate pattern, or a gate layer. The transistor 110 may further include source / drain regions S / D located above the channel region 111 and on the opposite side of the gate structure 112. In some embodiments, the dopants in the source / drain regions S / D of the first conductivity type element region 10D (see Figure 2A ) may have a conductivity type opposite to that of the dopants in the source / drain regions S / D of the second conductivity type element region 10E (see Figure 2A ). For example, the source / drain regions S / D of the first conductivity type element region 10C may have p-type dopants, while the source / drain regions S / D of the second conductivity type element region 10E may have n-type dopants.

[0110] Figure 2A As shown, the input / output circuit 101a includes a cut polysilicon (CPO) structure 114, which is used to separate adjacent gate structures 112. The cut polysilicon structure 114 can be used to isolate individual transistors 110 or transistor groups within the input / output circuit 101a. In some embodiments, the cut polysilicon structure 114 may be made of a dielectric material and may be referred to as an isolation structure, an isolation strip, or an isolation line pattern.

[0111] In some embodiments, the source / drain regions S / D may be connected to the interconnect structure 118 (see Figure 3A ) through source / drain contact structures 120 (see Figure 3A ) and source / drain vias 130 (see Figure 3A) is electrically connected to the upper metal line. The gate structure 112 can be electrically connected to another upper metal line in the interconnect structure through the gate via 132. The interconnect structure 118 can be formed above the transistor 110. For example, it may include seven metalization layers, labeled M0, M1, M2, M3, M4, M5, and M6, and includes multiple metalization vias for interconnection. Other embodiments may include more or fewer metalization layers and corresponding via numbers. The metal lines shown here only as examples may have other directions (rotated 90 degrees or other directions).

[0112] In some embodiments, the metal lines located in layer M0 (see Figure 3A ) may include a power supply voltage line Vss (see Figure 2A ), a power supply voltage line Vdd (see Figure 2A ), metal line 140 (see Figure 3A , 3B and 3F) and metal line 142 (see Figure 3A , Figure 3E and Figure 3I ). The metal lines located in layer M0 may be arranged along the length direction of the X direction. In some embodiments, the buffer circuit 103a can be powered by the power supply voltage line Vdd, and the power supply voltage line Vss can provide electrical grounding. The power supply voltage lines Vdd and Vss can be electrically connected to the source ends of the first and second buffer circuit regions 10B and 10C (see Figure 3A ) through the source / drain contact structure 120 (see Figure 2A ) and the source / drain via 130. The metal lines 140 and 142 can be located between the power supply voltage lines Vdd and Vss. The metal line 140 can be electrically connected to the drain ends of the first and second buffer circuit regions 10B and 10C (see Figure 2A , Figure 3A and Figure 3F ) through the source / drain contact structure 120 and the source / drain via 130. The metal line 142 can be electrically connected to the gate structure 112 of the first and second buffer circuit regions 10B and 10C through the gate via 132 (see Figure 2A , Figure 3E and Figure 3I ). In some embodiments, the metal line 142 can extend beyond the opposite boundary of the electrostatic discharge protection region 10A to reach the divided first and second buffer circuit regions 10B and 10C. In some embodiments, the metal line 142 can span the electrostatic discharge protection region 10A and the first and second buffer circuit regions 10B and 10C. In some embodiments, the length of the metal line 142 may be longer than the length of the metal line 140.

[0113] In some embodiments, the metal line 150 located in layer M1 (see Figure 3A ,Figure 3B and Figure 3F ) may be located above layer M0. The metal lines located in layer M1 may be arranged along the length direction in the Y direction. Metal line 150 may be electrically connected to metal lines 140 / 142 (see Figure 3A , Figure 3B and Figure 3F ) in the first and second conductive type element regions 10D and 10E (see Figure 2A ).

[0114] In some embodiments, the metal line 160 located in layer M2 (see Figure 3A , Figure 3B and Figure 3F ) may be located above layer M1. The metal lines located in layer M2 may be arranged along the length direction in the X direction. Metal line 160 may be electrically connected to metal line 150 (see Figure 3A , Figure 3B and Figure 3F ) through the via 155 below. In other words, as shown in Figure 3B and Figure 3F , the source / drain regions S / D of the transistor 110 in the buffer circuit 103a may be electrically connected to the source / drain regions S / D of another transistor 110 in the electrostatic discharge protection circuit 103a through the horizontal metal line 160 (i.e., the horizontal current path). In some embodiments, the speed of the wafer-to-wafer input / output circuit may be limited by electromigration in the metal line 160. Metal line 160 may extend beyond the opposite boundary of the electrostatic discharge protection region 10A to reach the divided first and second buffer circuit regions 10B and 10C, thereby reducing the length of the current path, and thus the current crowding and electromigration problems can be alleviated.

[0115] In some embodiments, the metal line 160 may span across the electrostatic discharge protection region 10A and the first and second buffer circuit regions 10B and 10C, such that the metal line 160 may traverse the gate structures 112 of the electrostatic discharge protection region 10A and the first and second buffer circuit regions 10B and 10C. The metal line 160 may span over the transistor 110 of the first buffer circuit region 10B to the transistor 110 of the electrostatic discharge protection region 10A, and then extend over the transistor 110 of the second buffer circuit region 10C. In some embodiments, the length of the metal line 160 is greater than the underlying metal line 140 connected to the source / drain via 130. In some embodiments, the metal line may be referred to as a trace or a path. In some embodiments, the materials of the lines Vss, Vdd, 140, 142, 150, and 160, the contact structure 120, and / or the source / drain via 130 and the gate via 132 may be made of copper (Cu), cobalt (Co), ruthenium (Ru), platinum (Pt), aluminum (Al), tungsten (W), titanium (Ti), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

[0116] Figures 3B to 3D and Figures 3F to 3H illustrate various ways of connecting the buffer circuit 103a to the electrostatic discharge protection circuit 104a. These methods utilize different metal line levels (e.g., layer M0, layer M2) within the integrated circuit structure to establish this connection. This flexibility can optimize the signal transmission path (e.g., marked by dashed lines in Figures 3B to 3D and Figures 3F to 3H ).

[0117] In Figure 3C and Figure 3G , the metal line 140 of layer M0 can be used to establish the connection between the buffer circuit 103a and the electrostatic discharge protection circuit 104a, which provides a signal transmission path from the buffer circuit 103a to the electrostatic discharge protection circuit 104a and simplifies the overall layout. Figure 3C and Figure 3G The dashed lines in Figure 3D and Figure 3H illustrate the flow of signal I through the metal line 140. In Figure 3D and Figure 3H , both the metal line 140 of layer M0 and the metal line 160 of layer M2 can be used to establish the connection between the buffer circuit 103a and the electrostatic discharge protection circuit 104a, which provides routing flexibility and reduces electromigration or enhances signal integrity. Figure 3D and Figure 3H The dashed lines in Figure 3B and Figure 3FIn [the figure], the metal line 160 of layer M2 can be used to establish a connection between the buffer circuit 103a and the electrostatic discharge protection circuit 104a. In some embodiments, such a higher-level metal line (e.g., layer M4 or layer M6) can be used for longer connections or to bypass other components in the integrated circuit structure. Figure 3B and Figure 3F The dashed line in [the figure] shows the flow of signal I through the metal line 140.

[0118] Figure 2B The top view layout pattern of the input / output circuit 101c is shown, including the buffer circuit 103c and the electrostatic discharge protection circuit 104c, which is consistent with some embodiments in the present disclosure. The buffer circuit 103c and the electrostatic discharge protection circuit 104c can correspond to Figure 2A and Figures 3A to 3K the buffer circuit 103a and the electrostatic discharge protection circuit 104a of the input / output circuit 101c shown in [the figure]. The input / output circuit 101a in Figure 2A and Figures 3A to 3K The version shown in [the figure] is different from this embodiment in that the first and second buffer circuit regions 10B and 10C in the input / output circuit 101c have more transistors 110 arranged along the opposite boundary of the electrostatic discharge protection region 10A (e.g., along the Y direction), thereby increasing the total driving force of the buffer circuit. The additional transistors in regions 10B and 10C enhance the ability of the buffer circuit to drive signals, making the circuit more powerful when dealing with larger loads or faster signal transmissions. In addition, the positions of the additional transistors in regions 10B and 10C make the horizontal current path between the buffer circuit 103c and the electrostatic discharge protection circuit 104c more direct and shorter, thereby minimizing the distance the signal needs to travel and reducing the risk of electromigration. The configuration of the input / output circuit 101c is similar to that of the input / output circuit 101a, maintaining the same basic structure, with the electrostatic discharge protection region 10A located between the first and second buffer circuit regions 10B and 10C.

[0119] Please refer to Figure 4 . Figure 4 The top view layout pattern of the input / output circuit 101d is shown, which includes a buffer circuit and an electrostatic discharge protection circuit (not shown), with the metal line 150 of layer M1 and the metal line 160 of layer M2, as well as the via 155 sandwiched between the metal lines 150 and 160, which is consistent with some embodiments in the present disclosure. The buffer circuit and the electrostatic discharge protection circuit can correspond to Figure 2B the buffer circuit 103c and the electrostatic discharge protection circuit 104c of the input / output circuit 101c shown in [the figure]. As shown in Figure 4As shown, the metal line 150 located in layer M1 can be cut (or severed) to create a forced split current path, thereby more evenly distributing the current flow in the circuit and reducing the risk of electromigration. In some embodiments, the length L1 of the metal line 150 located in layer M1 may be less than the dimension of the buffer region size L2 of the buffer regions 10B / 10C in the length direction (or Y direction) of the metal line 160. In some embodiments, the length L1 of the metal line 150 may be less than the length L3 of the metal line 160.

[0120] In addition, the layout can ensure that the vias 155 under each metal line 160 in layer M2 have a balanced or consistent configuration. This means that the number of vias 155 connected to each metal line 160 remains consistent throughout the circuit. In some embodiments, to maintain consistency, the difference in the number of vias 155 under two adjacent metal lines 160 can be controlled within a certain threshold, such as not greater than 5, such as 4, 3, 2, 1, to ensure that no single metal line 160 bears excessive current, which may lead to an increase in electromigration stress. In some embodiments, the difference in the number of vias 155 under two adjacent metal lines 160 can be controlled to be not greater than 3. The combination of splitting the metal line 150 in layer M1 and balancing the number of vias in layer M2 can result in a more uniform current flow. This distribution can reduce local points of high current density, thereby achieving a reduction in electromigration stress of more than 15%. In some embodiments, the number of vias 155 on the first group of metal lines 160 can be substantially the same as the number of vias 155 on the second group of metal lines 160.

[0121] Please refer to Figures 5A to 5F 。 Figures 5A to 5F FIG. shows a schematic cross-sectional view of the input / output circuit 101a at an intermediate stage of the manufacturing process, corresponding to Figure 3B 。It should be understood that additional operations can be provided before, during, and after the process shown in Figures 5A to 5F , and some of the operations described below may be replaced or omitted for methods of other embodiments. The order of the operations / processes may be interchanged.

[0122] Refer to Figure 5A 。One or more shallow trench isolation (STI) regions 113 are formed in the substrate 50 having the electrostatic discharge protection circuit region 10A and the buffer circuit regions 10B / 10C to define the channel regions 111 (see Figure 5E and Figure 5F)。Forming the shallow trench isolation regions 113 includes, but is not limited to, etching the substrate 50 to form one or more trenches for defining the channel regions 111, then depositing one or more dielectric materials (such as silicon dioxide) to fill the trenches in the substrate 50, and then planarizing the one or more shallow trench isolation regions 113 with the substrate 50 by a chemical mechanical polishing (CMP) process.

[0123] In some embodiments, the substrate 50 may include silicon (Si). Alternatively, the substrate 50 may include germanium (Ge), silicon germanium (SiGe), III-V materials (such as GaAs, GaP, GaAsP, AlInAs, AlGaAs, GaInAs, InAs, GaInP, InP, InSb, and / or GaInAsP; or combinations thereof) or other suitable semiconductor materials. In some embodiments, the substrate 50 may include a semiconductor-on-insulator (SOI) structure. For example, the substrate 50 may include a bulk semiconductor substrate, a buried dielectric layer covering the bulk substrate, and a semiconductor layer covering the buried dielectric layer.

[0124] In some embodiments, depositing the dielectric material for the one or more shallow trench isolation regions 113 may be performed by a chemical vapor deposition (CVD) process, a sub-atmospheric CVD (SACVD) process, a flowable CVD process, an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, and / or other suitable processes. In some embodiments, the dielectric layer may include a multi-layer structure, such as having one or more liner layers. In some embodiments, the shallow trench isolation regions 113 may include silicon dioxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low dielectric constant dielectrics, combinations thereof, etc. or other suitable materials.

[0125] Please refer to Figure 5BOnce one or more shallow trench isolation regions 113 are formed, a sacrificial gate structure 122 is formed on the channel regions 111 in the electrostatic discharge protection circuit region 10A and the buffer circuit regions 10B / 10C. The sacrificial gate structure 122 may include a sacrificial gate dielectric layer 122a and a sacrificial gate 122b covering the sacrificial gate dielectric layer 122a. By way of example and not limitation, a sacrificial gate dielectric material (such as silicon dioxide, silicon nitride, etc.) may first be deposited on the substrate 50, and then a sacrificial gate material (such as doped or undoped polysilicon) may be deposited on the dummy gate dielectric material, followed by planarization (such as by CMP), and then the sacrificial gate material and the sacrificial gate dielectric material are patterned using appropriate lithography and etching techniques to form a sacrificial gate structure 122 including the sacrificial gate dielectric material and the sacrificial gate material, serving as its sacrificial gate dielectric layer 122a and sacrificial gate 122b.

[0126] Please refer to Figure 5C Thereafter, gate spacer structures 115 are formed on the opposite sidewalls of each sacrificial gate structure 122. The gate spacer structures 115 may be formed, for example, by depositing and anisotropically etching a spacer dielectric layer, which is performed after the sacrificial gate patterning is completed. In some embodiments, the spacer dielectric layer may include one or more dielectrics, such as silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, etc., or a combination thereof. The anisotropic etching process removes the spacer dielectric layer from the top of the sacrificial gate structure 122 while leaving the gate spacer structures 115 on the sidewalls of the sacrificial gate structure 122.

[0127] Please refer to Figure 5D The active regions of the substrate 50 exposed by the sacrificial gate structure 122 and the gate spacer structures 115 may be recessed by an appropriate process, such as etching. Thereafter, source / drain regions S / D may be formed on the exposed surfaces of the remaining active regions, and the source / drain. In other words, the source / drain regions S / D may be formed in the active regions and self-aligned to the gate spacer structures 115. The portions between the active regions (such as fin structures) may serve as the channel regions 111. The source / drain regions S / D may be formed by growing an epitaxial semiconductor material from the active regions by performing an epitaxial growth process. The source / drain regions S / D may be doped with an n-type impurity (such as phosphorus) or a p-type impurity (such as boron), depending on the conductivity type of the corresponding transistor.

[0128] Please refer to Figure 5E。Then, an interlayer dielectric layer 116 is formed on the source / drain regions S / D by first depositing a dielectric material on the substrate 50 and then planarizing the dielectric material (e.g., using CMP) until the sacrificial gate structure 122 is exposed. Thereafter, the sacrificial gate structure 122 is replaced with a metal gate structure 112. The fabrication of the source / drain regions and gate structures of the transistor can be referred to as front-end-of-line (FEOL) processing.

[0129] In some embodiments, the interlayer dielectric layer 116 may include silicon dioxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), low dielectric constant (low-k) dielectrics such as fluorosilicate glass (FSG), silicon oxycarbide (SiOCH), carbon-doped oxide (CDO), flowable oxide or porous oxide (e.g., xerogels / aerogels), etc., or a combination thereof. The dielectric material for forming the interlayer dielectric layer 116 can be deposited using any suitable method, such as CVD, physical vapor deposition (PVD), ALD, PEALD, PECVD, SACVD, FCVD, spin coating, etc., or a combination thereof, followed by a chemical mechanical polishing process to level the interlayer dielectric layer 116 with the sacrificial gate structure.

[0130] After the chemical mechanical polishing process is completed, a gate replacement process is performed to replace the sacrificial gate structure 122 with a metal gate structure 112. The gate replacement process includes, by way of example and not limitation, removing the sacrificial gate structure 122 using one or more etching techniques (e.g., dry etching, wet etching, or a combination thereof) to create a gate trench between the corresponding gate spacer structures 115. Next, a gate dielectric layer 112a including one or more dielectrics and then a gate electrode layer 112b including one or more metals are deposited to completely fill the gate trench. The excess portions of the gate dielectric layer 112a and the gate electrode layer 112b are then removed from the top surface of the interlayer dielectric layer 116, e.g., using a chemical mechanical polishing process. Figure 5EThe structure shown may include residual portions of the gate dielectric layer 112a and the gate electrode layer 112b, embedded between the respective gate spacer structures 115, serving as the metal gate structure 112. The material for forming the metal gate structure 112 can be deposited by any suitable method, such as CVD, PECVD, PVD, ALD, PEALD, electrochemical plating (ECP), electroless plating, etc.

[0131] In some embodiments, the gate dielectric layer 112a may comprise, for example, hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), lanthanum oxide (LaO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta 2 O 5 ), yttrium oxide (Y 2 O 3 ), strontium titanate (SrTiO 3 , STO), barium titanate (BaTiO 3 , BTO), barium zirconate (BaZrO), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), aluminum oxide (Al 2 O 3 ), etc. dielectric materials, or combinations thereof. In some embodiments, the gate electrode layer 112b may comprise TiN, TaN, TiAl, TiAlN, TaAl, TaAlN, TaAlC, TaCN, WNC, Cu, Al, Co, Ni, Pt, W, etc., or combinations thereof.

[0132] Please refer to Figure 5F。The source / drain contact structure 120 may be formed in the interlayer dielectric layer 116 and on the source / drain regions S / D. In some embodiments, a source / drain silicide region (not shown) may be formed between the source / drain contact structure 120 and the source / drain regions S / D. Subsequently, the source / drain vias 130 may be formed in the interlayer dielectric layer 116 on the interlayer dielectric layer 117 and land on the source / drain contact structure 120. The gate vias 132 may be formed in the interlayer dielectric layer 117 and land on the gate structure 112. In some embodiments, the source / drain contact structure 120, the source / drain vias 130, and the gate vias 132 may comprise metal-containing materials such as titanium nitride, titanium oxide, tungsten, cobalt, ruthenium, aluminum, copper, etc., or combinations, multi-layer structures, etc. The interlayer dielectric layer 117 may be made of oxides such as silicon dioxide, nitrides such as silicon nitride, etc., or combinations thereof, and may be formed by a chemical vapor deposition (CVD) process, such as high density plasma CVD (HDP-CVD), flowable chemical vapor deposition (FCVD), etc., or combinations thereof.

[0133] Specifically, once the deposition of the interlayer dielectric layer 116 is completed, the gate vias 132 and the source / drain vias 130 will be formed by using lithography, etching, and deposition techniques. For example, a patterned mask may be formed on the interlayer dielectric layer 116 for etching trenches extending into the interlayer dielectric layer 116 to expose the source / drain contact structure 120 or the gate structure 112. Subsequently, one or more metals are deposited to fill the trenches in the interlayer dielectric layer 116, using any acceptable deposition technique (such as CVD, ALD, PEALD, PECVD, PVD, ECP, electroless plating, etc., or combinations thereof). Next, a planarization process (such as chemical mechanical polishing) may be used to remove the excess metal from the top surface of the interlayer dielectric layer 116. The remaining metal extends in the interlayer dielectric layer 116, constituting the source / drain vias 130 or the gate vias 132, and making physical and electrical connections with the source / drain contact structure 120 or the gate structure 112.

[0134] Subsequently, an interconnect structure 118 may be formed above the gate vias 132 and the source / drain vias 130. The interconnect structure 118 may include, for example, seven metallization layers formed in an inter-metal dielectric (IMD) layer 119, labeled M0, M1, M2, M3, M4, M5, and M6, which include multi-layer metallization vias connected together. Other embodiments may include more or fewer metallization layers and correspondingly more or fewer vias. The metal lines shown here are only examples, and the metal lines may have other orientations (such as rotated 90 degrees or other orientations). In some embodiments, the metal lines in layer M0 above the substrate 50 may include a power supply voltage line Vss (see Figure 2A 、Figure 3J and Figure 3K ), a power supply voltage line Vdd (see Figure 2A , Figure 3J and Figure 3K ), metal lines 140 and 142 (see Figure 3E and Figure 3I ). Metal lines in layer M1 above layer M0 may include metal line 150 (see Figure 3A , Figure 3B and Figure 3F ). Metal lines in layer M2 above layer M1 may include metal line 160. Although not shown (for simplicity and clarity), other metal lines are also formed above the interconnect structure 118. In some embodiments, the metallization layer may include metal-containing materials such as titanium nitride, titanium oxide, tungsten, cobalt, ruthenium, aluminum, copper, etc., or combinations thereof, multi-layer structures, etc. The inter-metal dielectric layer 119 may be made of oxides or nitrides such as silicon dioxide, silicon nitride, etc., or combinations thereof, and may be formed by a chemical vapor deposition (CVD) process, such as high density plasma CVD (HDP-CVD), flowable chemical vapor deposition (FCVD), etc., or combinations thereof. In some embodiments, the metal lines and / or metal vias in each metallization layer may contain metal-containing materials such as titanium nitride, titanium oxide, tungsten, cobalt, ruthenium, aluminum, copper, etc., or combinations thereof, multi-layer structures, etc.

[0135] Refer to Figure 6 . Figure 6 is a schematic diagram of an electronic design automation (EDA) system, according to some embodiments herein. As described above, the method of generating the design layout of the input / output circuits 101a, 101b, 101c, and / or 101d may be implemented, for example, using the electronic design automation system 1600, according to some embodiments. At least the input / output circuits 101a, 101b, 101c, and / or 101d are manufactured through the corresponding layout designs, similar to the corresponding integrated circuits. For simplicity, Figures 1A - 5F is shown as the corresponding integrated circuit, but in some embodiments, Figures 1A - 5Falso corresponds to a layout design having a structure and pattern relationship similar to that of the input / output circuits 101a, 101b, 101c, and / or 101d, including alignment, length, and width, and the configuration and hierarchy of the corresponding layout design are similar to the structural relationship, configuration, and hierarchy of the corresponding integrated circuit, and are not shown in detail to maintain brevity. In some embodiments, the electronic design automation system 1600 is a computing element capable of performing one or more automatic placement & routing (APR) operations. The electronic design automation system 1600 includes a hardware processor 1602 and a non-volatile, readable and writable storage medium 1604. Encoded in the storage medium 1604, that is, stored, is a set of executable instructions 1606, a design layout 1607, a design rule check (DRC) suite 1609, or any intermediate data for executing the instruction set. Each design layout 1607 may include a graphical representation of an integrated wafer, such as a GSII file. Each design rule check platform 1609 may include a list of design rules for a selected semiconductor process. The hardware processor 1602 executes the instructions 1606, the design layout 1607, and the design rule check platform 1609, representing (at least in part) an electronic design automation tool, implementing part or all of the methods such as those illustrated herein, according to one or more embodiments (hereinafter, the processes and / or methods).

[0136] The processor 1602 is electrically connected to the readable storage medium 1604 through a bus 1608. The processor 1602 is also electrically connected to an input / output interface 1610 through the bus 1608. A network interface 1612 is also electrically connected to the processor 1602 through the bus 1608. The network interface 1612 is connected to a network 1614 so that the processor 1602 and the readable storage medium 1604 can be connected to external components through the network 1614. The processor 1602 is configured to execute the instructions 1606 encoded in the readable storage medium 1604 so that the electronic design automation system 1600 can perform the partial or all of the processes and / or methods described above. In one or more embodiments, the processor 1602 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0137] In one or more embodiments, the readable storage medium 1604 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device). For example, the readable storage medium 1604 includes semiconductor or solid state memories, magnetic tapes, removable computer disks, random access memories (RAMs), read-only memories (ROMs), hard disks, and / or optical disks. In one or more embodiments using optical disks, the readable storage medium 1604 includes compact disk read-only memories (CD-ROMs), compact disk read / write (CD-R / W) disks, and / or digital video disks (DVDs).

[0138] In one or more embodiments, the readable storage medium 1604 stores instructions 1606, design layouts 1607 (e.g., the layouts of the input / output circuits 101a, 101b, 101c, and / or 101d discussed previously), and DRC decks 1609, configured to enable the electronic design automation system 1600 (wherein such execution at least partially represents electronic design automation tools) to perform some or all of the processes and / or methods described. In one or more embodiments, the storage medium 1604 also stores information that facilitates the execution of some or all of the processes and / or methods described.

[0139] The electronic design automation system 1600 includes an input / output interface 1610. The input / output interface 1610 is connected to an external circuit. In one or more embodiments, the input / output interface 1610 includes a keyboard, numeric keypad, mouse, trackball, touchpad, touch screen, and / or cursor direction keys for transmitting information and commands to the processor 1602.

[0140] The electronic design automation system 1600 also includes a network interface 1612 connected to the processor 1602. The network interface 1612 allows the electronic design automation system 1600 to communicate with one or more other computer systems connected to the network 1614. The network interface 1612 includes a wireless network interface such as Bluetooth, WiFi, WiMAX, GPRS, or WCDMA; or a wired network interface such as Ethernet, USB, or IEEE-1388. In one or more embodiments, some or all of the processes and / or methods described are implemented in two or more electronic design automation systems 1600.

[0141] The electronic design automation system 1600 is configured to receive information through the input / output interface 1610. The information received through the input / output interface 1610 includes instructions, data, design rules, standard component libraries, and / or other parameters for processing by the processor 1602. The information is transmitted to the processor 1602 via the bus 1608. The electronic design automation system 1600 is configured to receive information related to the user interface (UI) 1616 through the input / output interface 1610. This information is stored in the computer-readable medium 1604 as the user interface 1616.

[0142] Figure 6 Also illustrated are manufacturing tools related to the electronic design automation system 1600. For example, a mask shop 1630 receives a design layout from the electronic design automation system 1600 via the network 1614, and the mask shop 1630 has a mask manufacturing tool 1632 (e.g., a photomask writer) for manufacturing one or more photomasks (e.g., photomasks for manufacturing the input / output circuits 101a, 101b, 101c, and / or 101d discussed previously) based on the design layout generated from the electronic design automation system 1600. An integrated circuit fabrication facility ("Fab") 1620 can be connected to the mask shop 1630 and the electronic design automation system 1600 via the network 1614. The integrated circuit fabrication facility 1620 includes an integrated circuit manufacturing tool 1622 for manufacturing integrated circuit wafers using the masks manufactured by the mask shop 1630 (e.g., using the layout for manufacturing the input / output circuits 101a, 101b, 101c, and / or 101d manufactured by the mask shop 1630). By way of example and not limitation, the integrated circuit manufacturing tool 1622 includes one or more cluster tools for manufacturing integrated circuit wafers. The cluster tool can be a multi-reaction chamber type composite device that includes a polyhedral transfer chamber with a wafer handling robot inserted in the center and multiple process chambers (e.g., CVD chambers, PVD chambers, etching chambers, annealing chambers, or the like) located on each wall of the polyhedral transfer chamber. And a load chamber is mounted on a different wall of the transfer chamber.

[0143] Referring Figure 7 。 Figure 7 is a block diagram of an IC manufacturing system and related manufacturing processes according to some embodiments disclosed herein. In some embodiments, one or more photomasks and one or more integrated circuits are manufactured using the manufacturing system 1700 based on one or more design layouts, e.g., the layouts of the input / output circuits 101a, 101b, 101c, and / or 101d as described above.

[0144] In Figure 7In this case, the integrated circuit manufacturing system 1700 includes entities that interact with each other, such as a design end 1720, a mask shop 1730, and an integrated circuit manufacturing end 1750, which interact in the design, development, and manufacturing cycles and / or in services related to manufacturing the integrated circuit 1760. The entities in the integrated circuit manufacturing system 1700 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design end 1720, the mask shop 1730, and the integrated circuit manufacturing end 1750 are owned by a larger company. In some embodiments, two or more of the design end 1720, the mask shop 1730, and the integrated circuit manufacturing end 1750 coexist in a common facility and use common resources.

[0145] The design end (or design team) 1720 generates a design layout 1722 (e.g., the layout of the input / output circuits 101a, 101b, 101c, and / or 101d as described above). The design layout 1722 includes various geometric patterns designed for the ICs 1760 to be manufactured (e.g., the input / output circuits 101a, 101b, 101c, and / or 101d with a resistor circuit as described above). These geometric patterns correspond to the patterns of the various metal, oxide, or semiconductor layers that make up the integrated circuit 1760. The various layers combine to form various device features. For example, a portion of the design layout 1722 includes various circuit features, such as active regions, passive regions, functional gate structures, resistor structures, gate contacts, resistor contacts, source / drain contacts, and / or metal lines, to be formed on a semiconductor wafer. The design end 1720 implements appropriate design procedures to form the design layout 1722. The design procedures include one or more of logic design, physical design, or layout design. The design layout 1722 is represented by one or more electronic data files containing geometric pattern information and various networks. For example, the design layout 1722 can be represented in the GDSII file format or the DFII file format.

[0146] The mask factory 1730 includes data preparation 1732 and mask manufacturing 1744. The mask factory 1730 manufactures one or more photomasks 1745 for various layers of the IC 1760 according to the design layout 1722 (e.g., the layout of the input / output circuits 101a, 101b, 101c, and / or 101d as described above). The mask factory 1730 performs mask data preparation 1732, in which the design layout 1722 is converted into a representative data file ("RDF"). The mask data preparation 1732 provides the RDF to the mask manufacturing 1744. The mask manufacturing 1744 includes a mask writer. The mask writer converts the RDF into an image on a substrate, e.g., a photomask (mask) 1745. The mask data preparation 1732 operates on the design layout 1722 to conform to the specific characteristics of the mask writer and / or the rules of the integrated circuit manufacturing end 1750. In Figure 7 FIG., the mask data preparation 1732 and the mask manufacturing 1744 are shown as separate elements. In some embodiments, the mask data preparation 1732 and the mask manufacturing 1744 may be collectively referred to as mask data preparation.

[0147] In some embodiments, the mask data preparation 1732 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those caused by diffraction, interference, other process effects, etc. The optical proximity correction adjusts the design layout 1722. In some embodiments, the mask data preparation 1732 further includes resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shift masks, other suitable techniques, etc., or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, treating the optical proximity correction as an inverse imaging problem.

[0148] In some embodiments, the mask data preparation 1732 includes a mask rule checker (MRC), which checks the design layout 1722 that has been processed by optical proximity correction, using a set of mask creation rules that include some geometric and / or connectivity restrictions to ensure sufficient margins to account for variability in the semiconductor manufacturing process, etc. In some embodiments, the mask rule checker modifies the design layout 1722 diagram to compensate for limitations during mask manufacturing 1744, which may undo some of the modifications performed by the optical proximity correction to meet the mask creation rules.

[0149] In some embodiments, mask data preparation 1732 includes lithography process checking (LPC), which simulates the processing that will be implemented by the integrated circuit fabrication end 1750 to fabricate ICs 1760. The lithography process checking simulates this processing based on the design layout 1722 to create a simulated fabricated integrated circuit, such as integrated circuit 1760. The processing parameters in the lithography process checking simulation can include parameters related to various processes of the integrated circuit manufacturing cycle, parameters related to the tools used to manufacture the integrated circuit, and / or other aspects of the manufacturing process. The lithography process checking takes into account various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, etc., or a combination thereof. In some embodiments, if the shape of the simulated fabricated device created by the lithography process checking is not close enough to the shape that meets the design rules, optical proximity correction and / or mask rule checker is repeated to further optimize the design layout 1722.

[0150] After mask data preparation 1732 and during mask manufacturing 1744, one or a set of masks 1745 are fabricated according to the design layout 1722. In some embodiments, mask manufacturing 1744 includes performing one or more lithographic exposures according to the design layout 1722. In some embodiments, an electron beam (e-beam) or multiple electron beam mechanisms are used to form a pattern on the mask 1745 according to the design layout 1722. The mask 1745 can be formed using various techniques. In some embodiments, the mask 1745 is formed using a binary technique. In some embodiments, the mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, is used to expose a radiation-sensitive material layer (such as photoresist) coated on a wafer, and the radiation beam is blocked by the opaque regions and penetrates the transparent regions. In one example, the binary version of the mask 1745 includes a transparent substrate (such as fused quartz) and an opaque material (such as chromium) coated on the opaque regions of the binary mask. In another example, the mask 1745 is formed using a phase shift technique. In the phase shift mask (PSM) version of the mask 1745, various features in the pattern are configured to have an appropriate phase difference to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated phase shift mask or an alternating phase shift mask. The mask(s) generated by mask manufacturing 1744 are used in various processes. For example, such mask(s) are used in an ion implantation process to form various doped regions in the semiconductor wafer 1753, in an etching process to form various etched regions in the semiconductor wafer 1753, and / or in other suitable processes.

[0151] The integrated circuit manufacturing end 1750 may include wafer manufacturing 1752. The integrated circuit manufacturing end 1750 is an integrated circuit manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various different integrated circuit products. In some embodiments, the integrated circuit manufacturing end 1750 is a semiconductor foundry. For example, there may be a manufacturing facility for front-end manufacturing of multiple integrated circuit products (front-end-of-line (FEOL) manufacturing), while a second manufacturing facility may provide back-end manufacturing of the integrated circuit products for connecting and packaging the integrated circuit products (back-end-of-line (BEOL) manufacturing), and a third manufacturing facility may provide other services for the foundry business.

[0152] The integrated circuit manufacturing end 1750 uses photomask(s) 1745, which are manufactured by the mask shop 1730, to manufacture the integrated circuit 1760. Thus, the integrated circuit manufacturing end 1750 at least indirectly uses the design layout(s) 1722 (e.g., the layout of the input / output circuits 101a, 101b, 101c, and / or 101d as described above) to manufacture the integrated circuit 1760. In some embodiments, the wafer 1753 is processed by the integrated circuit manufacturing end 1750 using photomask(s) 1745 to form the integrated circuit 1760. In some embodiments, device manufacturing includes performing one or more lithographic exposures at least indirectly based on the design layout 1722.

[0153] Therefore, based on the above discussion, the advantages disclosed herein can be seen. However, it should be understood that other embodiments may provide additional advantages, not all advantages must be disclosed herein, and not all embodiments require specific advantages. In various embodiments, the disclosure herein provides a method for enhancing the performance of wafer-to-wafer input / output circuits in three-dimensional integrated circuits. The input / output circuit can integrate a buffer circuit with an electrostatic discharge protection structure. The drive strength of the buffer circuit (e.g., 16 PMOS and 16 NMOS transistors) can be divided into two sub-buffer regions (e.g., Figure 2A the buffer circuit regions 10B and 10C shown in ), and each sub-buffer region has half of the total drive strength (e.g., 8 PMOS and 8 NMOS). Specifically, for the output stage, the transistors in the sub-buffer regions connect their source / drain regions to the transistors in the electrostatic discharge protection region through a horizontal metal line. The two sub-buffer regions can be placed in opposite positions of the electrostatic discharge protection region (e.g., Figure 2A the electrostatic discharge protection circuit region 10A shown in ). The arrangement can split and shorten the horizontal current path, reducing the length of the current path to 50% to 75% of the original length, thereby reducing the output capacitance load and improving the electromigration resistance.

[0154] In some embodiments, a semiconductor structure and a method of forming the same include forming a first transistor and a second transistor on a substrate, wherein the first transistor and the second transistor are part of a buffer circuit in an input / output circuit; forming a third transistor on the substrate, wherein the third transistor is between the first transistor and the second transistor in a cross-sectional view, and the third transistor is part of an electrostatic discharge circuit in the input / output circuit; forming a first metal line extending horizontally from above the first transistor across to above the second transistor, wherein the first metal line is electrically connected to the first transistor, the second transistor, and the third transistor. In some embodiments, the buffer circuit is a tri-state buffer circuit. In some embodiments, the buffer circuit is an emitter element. In some embodiments, the first metal line is connected from a source / drain region of the first transistor of the buffer circuit to a source / drain region of the third transistor of the electrostatic discharge circuit. In some embodiments, the method of forming the semiconductor structure further includes: before forming the first metal line, forming a second metal line on the source / drain region of the first transistor. The second metal line is electrically connected to the source / drain region of the first transistor, and after forming the first metal line and the second metal line, in a top view, the second metal line extends in a direction perpendicular to a length direction of the first metal line. In some embodiments, in a top view, a length of the second metal line is less than a length of the first metal line. In some embodiments, the method of forming the semiconductor structure further includes: before forming the first metal line, forming a plurality of metal vias on the substrate, and after forming the first metal line, a first group of the plurality of metal vias is directly located below the first metal line and in contact with the first metal line; forming a second metal line at the same height position as the first metal line. The second metal line is electrically connected to the buffer circuit and the electrostatic discharge circuit. A second group of the plurality of metal vias is directly located below the second metal line and in contact with the second metal line. A quantity difference between the first group of the plurality of metal vias and the second group of the plurality of metal vias is not greater than 3. In some embodiments, the method of forming the semiconductor structure further includes: forming a third metal line at the same height position as the first metal line and the second metal line. The third metal line is electrically connected to the buffer circuit and the electrostatic discharge circuit. A third group of the plurality of metal vias is directly located below the third metal line and in contact with the third metal line. A quantity difference between the first group of the plurality of metal vias and the third group of the plurality of metal vias is not greater than 3. In some embodiments, a quantity difference between the second metal vias and the third group of the plurality of metal vias among the plurality of metal vias is not greater than 3. In some embodiments, the method of forming the semiconductor structure further includes: before forming the first metal line, forming a metal contact on the source / drain region of the first transistor; forming a metal via on the metal contact. After forming the first metal line, the first metal line lands on the metal via.

[0155] In some embodiments, a semiconductor structure and a method of forming the same include forming a plurality of first source / drain regions on a first buffer circuit region of a substrate, forming a plurality of second source / drain regions on a second buffer circuit region of the substrate, and forming a plurality of third source / drain regions on an electrostatic discharge (ESD) circuit region of the substrate, wherein the first source / drain regions, the second source / drain regions, and the third source / drain regions are part of an input / output circuit of a first wafer, and in a top view, the ESD circuit region is located between the first buffer circuit region and the second buffer circuit region; forming a plurality of first gate strip structures on the first buffer circuit region, and in a top view, the plurality of first gate strip structures are interleaved with the plurality of first source / drain regions, forming a plurality of second gate strip structures on the second buffer circuit region, and in a top view, the plurality of second gate strip structures are interleaved with the plurality of second source / drain regions, and forming a plurality of third gate strip structures on the ESD circuit region, and in a top view, the plurality of third gate strip structures are interleaved with the plurality of third source / drain regions; forming metal lines on the first buffer circuit region, the second buffer circuit region, and the ESD circuit region, the metal lines being electrically connected to one of the plurality of first source / drain regions, one of the plurality of second source / drain regions, and one of the plurality of third source / drain regions. In some embodiments, the method of forming the semiconductor structure further includes: forming a first metal pad on the metal line, wherein the first metal pad is electrically connected to the metal line. In some embodiments, the method of forming the semiconductor structure further includes: bonding the first metal pad of the first wafer to a second metal pad of a second wafer. In some embodiments, the metal lines span across the first gate strip structures, the second gate strip structures, and the third gate strip structures. In some embodiments, the method of forming the semiconductor structure further includes: forming a plurality of fourth gate strip structures on the first buffer circuit region, and forming a plurality of fifth gate strip structures on the second buffer circuit region. The first gate strip structures and the fourth gate strip structures are arranged along a length direction of the first gate strip structures. The second gate strip structures and the fifth gate strip structures are arranged along a length direction of the second gate strip structures. The fourth gate strip structures and the fifth gate strip structures are part of the input / output circuit of the first wafer.

[0156] In some embodiments, a semiconductor structure includes a substrate, a first transistor, a second transistor, and a third transistor. The first transistor is located on an electrostatic discharge circuit region of the substrate. The second transistor is located on a first buffer circuit region of the substrate, wherein in a top view, the first buffer circuit region is located on a first side of the electrostatic discharge circuit region. The third transistor is located on a second buffer circuit region of the substrate, wherein the first transistor, the second transistor, and the third transistor are part of an input / output circuit of a first wafer, and in a top view, the second buffer circuit region is located on a second side opposite to the first side of the electrostatic discharge circuit region. In some embodiments, the semiconductor structure further includes a first metal wire. The first metal wire extends horizontally above the first buffer circuit region, the second buffer circuit region, and the electrostatic discharge circuit region. The first metal wire is electrically connected to a source / drain region of the first transistor, a source / drain region of the second transistor, and a source / drain region of the third transistor. In some embodiments, the semiconductor structure further includes a second metal wire, a plurality of first metal vias, and a plurality of second metal vias. The second metal wire extends above the first buffer circuit region, the second buffer circuit region, and the electrostatic discharge circuit region, and is at the same height position as the first metal wire. The first metal vias contact a bottom surface of the first metal wire. The second metal vias contact a bottom surface of the second metal wire. A quantity difference between the plurality of first metal vias and the plurality of second metal vias is not greater than 3. In some embodiments, the semiconductor structure further includes a pad structure. The pad structure is located above the first metal wire, wherein the pad structure is electrically connected to the first metal wire. In some embodiments, the second transistor and the third transistor are part of a tri-state buffer circuit, an inverter circuit, or a combination of the foregoing two.

[0157] In some embodiments, a semiconductor structure includes a substrate, a first transistor, a second transistor, a third transistor, and a first metal wire. The first transistor is located on the substrate. The second transistor is located on the substrate. The first transistor and the second transistor are part of a buffer circuit in an input / output circuit. The third transistor is located on the substrate. The third transistor is between the first transistor and the second transistor in a cross-sectional view, and the third transistor is part of an electrostatic discharge circuit in the input / output circuit. The first metal wire extends horizontally from above the first transistor across to above the second transistor. The first metal wire is electrically connected to the first transistor, the second transistor, and the third transistor. In some embodiments, the first metal wire connects from a source / drain region of the first transistor of the buffer circuit to a source / drain region of the third transistor of the electrostatic discharge circuit. In some embodiments, the buffer circuit is an emitting element.

[0158] In some embodiments, a semiconductor structure includes a substrate, a plurality of first source / drain regions, a plurality of second source / drain regions, a plurality of third source / drain regions, a plurality of first gate strip structures, a plurality of second gate strip structures, a plurality of third gate strip structures, and metal lines. The plurality of first source / drain regions are located on a first buffer circuit region of the substrate. The plurality of second source / drain regions are located on a second buffer circuit region of the substrate. The plurality of third source / drain regions are located on an electrostatic discharge circuit region of the substrate. The first source / drain regions, the second source / drain regions, and the third source / drain regions are part of an input / output circuit of a first wafer, and in a top view, the electrostatic discharge circuit region is located between the first buffer circuit region and the second buffer circuit region. The plurality of first gate strip structures are located on the first buffer circuit region. In a top view, the plurality of first gate strip structures are staggered with the plurality of first source / drain regions. The plurality of second gate strip structures are located on the second buffer circuit region. In a top view, the plurality of second gate strip structures are staggered with the plurality of second source / drain regions. The plurality of third gate strip structures are located on the electrostatic discharge circuit region. In a top view, the plurality of third gate strip structures are staggered with the plurality of third source / drain regions. The metal lines are located on the first buffer circuit region, the second buffer circuit region, and the electrostatic discharge circuit region. The metal lines are electrically connected to one of the plurality of first source / drain regions, one of the plurality of second source / drain regions, and one of the plurality of third source / drain regions. In some embodiments, the semiconductor structure further includes a first metal pad. The first metal pad is located on the metal line. The first metal pad is electrically connected to the metal line.

[0159] The foregoing has outlined features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations therein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: include: a substrate; a first transistor located on an electrostatic discharge circuit region of the substrate; a second transistor located on a first buffer circuit region of the substrate, wherein the first buffer circuit region is located on a first side of the electrostatic discharge circuit region from a top view; as well as A third transistor is located on a second buffer circuit area of ​​the substrate, wherein the first transistor, the second transistor and the third transistor are part of an input / output circuit of a first chip, and from the top view, the second buffer circuit area is located on a second side opposite to the first side of the electrostatic discharge circuit area.

2. The semiconductor structure according to claim 1, wherein: Further including: A first metal line extends horizontally above the first buffer circuit area, the second buffer circuit area and the electrostatic discharge circuit area, wherein the first metal line is electrically connected to a source / drain area of ​​the first transistor, a source / drain area of ​​the second transistor and a source / drain area of ​​the third transistor.

3. The semiconductor structure according to claim 2, wherein: Further including: a second metal line extending above the first buffer circuit region, the second buffer circuit region and the electrostatic discharge circuit region and being at the same height as the first metal line; as well as A plurality of first metal vias contacting a bottom surface of the first metal line; A plurality of second metal vias are in contact with a bottom surface of the second metal line, wherein a number difference between the plurality of first metal vias and the plurality of second metal vias is not greater than three.

4. The semiconductor structure according to claim 2, characterized in that Further including: A pad-shaped structure is located above the first metal line, wherein the pad-shaped structure is electrically connected to the first metal line.

5. The semiconductor structure according to claim 1, wherein: The second transistor and the third transistor are part of a tri-state buffer circuit, an inverter circuit or a combination of the two.

6. A semiconductor structure, characterized in that: include: a substrate; A first transistor is located on the substrate; A second transistor is located on the substrate, wherein the first transistor and the second transistor are part of a buffer circuit in an input / output circuit; a third transistor disposed on the substrate, wherein the third transistor is between the first transistor and the second transistor in a cross-sectional view, and the third transistor is a part of an electrostatic discharge circuit in the input / output circuit; as well as A first metal line horizontally extends from above the first transistor to above the second transistor, wherein the first metal line is electrically connected to the first transistor, the second transistor and the third transistor.

7. The semiconductor structure according to claim 6, wherein: The first metal line is connected from a source / drain region of the first transistor of the buffer circuit to a source / drain region of the third transistor of the electrostatic discharge circuit.

8. The semiconductor structure according to claim 6, wherein: The buffer circuit is a transmitting element.

9. A semiconductor structure, characterized in that: include: a substrate; A plurality of first source / drain regions are located on a first buffer circuit region of the substrate; A plurality of second source / drain regions are located on a second buffer circuit region of the substrate; A plurality of third source / drain regions are located on an electrostatic discharge circuit region of the substrate, wherein the first source / drain region, the second source / drain region and the third source / drain region are part of an input / output circuit of a first chip, and from a top view, the electrostatic discharge circuit region is located between the first buffer circuit region and the second buffer circuit region; A plurality of first gate strip structures are located on the first buffer circuit region, wherein from the top view, the plurality of first gate strip structures are staggered with the plurality of first source / drain regions; A plurality of second gate strip structures are located on the second buffer circuit region, wherein from the top view, the plurality of second gate strip structures are staggered with the plurality of second source / drain regions; A plurality of third gate strip structures are located on the electrostatic discharge circuit region, wherein from the top view, the plurality of third gate strip structures and the plurality of third source / drain regions are arranged alternately; as well as A metal line is located on the first buffer circuit area, the second buffer circuit area and the electrostatic discharge circuit area, wherein the metal line is electrically connected to one of the multiple first source / drain areas, one of the multiple second source / drain areas and one of the multiple third source / drain areas.

10. The semiconductor structure according to claim 9, wherein: Further including: A first metal pad is located on the metal line, wherein the first metal pad is electrically connected to the metal line.

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