Display panel and display device

Abstract

The display panel and the display device provided by the embodiment of the utility model comprise a plurality of sub-pixels, and each sub-pixel comprises a light-emitting device and a pixel circuit coupled with a first pole of the light-emitting device; the pixel circuit in the nth row of sub-pixels is coupled with the first pole of the light emitting device in the (n + 1) th row of sub-pixels through at least one driving control circuit, and the driving control circuits are configured to respond to a signal of a first control signal end; and transmitting a first driving current generated by the pixel circuit in the nth row of sub-pixels and / or a second driving current generated according to the data voltage in the pixel circuit in the nth row of sub-pixels to a light emitting device in the (n + 1) th row of sub-pixels. The pixel circuit and the drive control circuit cooperate with each other to improve the problem of inconsistent luminance between two adjacent rows of sub-pixels, and avoid the problem of black scanning lines on the display panel, thereby improving the display effect and competitiveness of the product.

Description

Technical Field

[0001] The utility model relates to the technical field of displays, and particularly to a display panel and a display device. Background Art

[0002] Light-emitting devices such as organic light-emitting diodes (OLEDs), quantum dot light-emitting diodes (QLEDs), micro light-emitting diodes (Micro LEDs), and mini light-emitting diodes (Mini LEDs) have the advantages of self-luminescence and low power consumption, and are one of the hotspots in the field of application research of current display devices. In general display devices, pixel circuits are used to drive the light-emitting devices to emit light. Summary of the Utility Model

[0003] The display panel provided by the embodiment of the utility model includes:

[0004] A plurality of sub-pixels, each of the sub-pixels including: a light-emitting device and a pixel circuit coupled to a first pole of the light-emitting device;

[0005] A plurality of drive control circuits, the pixel circuits in the nth row of sub-pixels are coupled to a first pole of the light-emitting devices in the (n + 1)th row of sub-pixels through at least one of the drive control circuits, and the drive control circuit is configured to respond to a signal at a first control signal terminal and transmit a first drive current generated by the pixel circuit in the nth row of sub-pixels and / or a second drive current generated according to a data voltage in the pixel circuit in the nth row of sub-pixels to the light-emitting devices in the (n + 1)th row of sub-pixels; where n is a positive integer greater than 0.

[0006] In some possible embodiments, the drive control circuit includes: a first switching transistor;

[0007] The gate of the first switching transistor is coupled to the first control signal terminal, the first pole of the first switching transistor is coupled to the light-emitting device in the pixel circuit in the nth row of sub-pixels, and the second pole of the first switching transistor is coupled to the light-emitting device in the pixel circuit in the (n + 1)th row of sub-pixels.

[0008] In some possible embodiments, the pixel circuit further includes: a first drive transistor;

[0009] The drive control circuit includes: a second drive transistor and a second switching transistor;

[0010] The gate of the second driving transistor is coupled to the gate of the first driving transistor in the pixel circuit of the sub-pixels in the n-th row, the first pole of the second driving transistor is coupled to the first pole of the first driving transistor in the pixel circuit of the sub-pixels in the n-th row, and the second pole of the second driving transistor is coupled to the first pole of the second switching transistor;

[0011] The gate of the second switching transistor is coupled to the first control signal terminal, and the second pole of the second switching transistor is coupled to the light-emitting device in the (n + 1)-th row of sub-pixels.

[0012] In some possible implementation manners, the pixel circuit further includes: a first driving transistor;

[0013] The driving control circuit includes: a third driving transistor, a third switching transistor, and a fourth switching transistor;

[0014] The gate of the third driving transistor is coupled to the gate of the first driving transistor in the pixel circuit of the sub-pixels in the n-th row, the first pole of the third driving transistor is coupled to the first pole of the first driving transistor in the pixel circuit of the sub-pixels in the n-th row, and the second pole of the third driving transistor is coupled to the first pole of the third switching transistor;

[0015] The gate of the third switching transistor is coupled to the first control signal terminal, and the second pole of the third switching transistor is coupled to the second pole of the first driving transistor in the pixel circuit of the sub-pixels in the n-th row;

[0016] The gate of the fourth switching transistor is coupled to the first control signal terminal, the first pole of the fourth switching transistor is coupled to the light-emitting device in the pixel circuit of the sub-pixels in the n-th row, and the second pole of the fourth switching transistor is coupled to the light-emitting device in the (n + 1)-th row of sub-pixels.

[0017] In some possible implementation manners, a driving control circuit is provided for each sub-pixel in the first row to the (N - 1)-th row in a one-to-one correspondence, and the first pole of the light-emitting device in the sub-pixels in the (n + 1)-th row is coupled to the sub-pixels in the n-th row through the corresponding driving control circuit.

[0018] In some possible implementation manners, the driving control circuit is located between the pixel circuits of adjacent two rows of sub-pixels.

[0019] In some possible implementation manners, the driving control circuit is located between the pixel circuits of adjacent two columns of sub-pixels.

[0020] In some possible implementation manners, the driving control circuit is integrally provided in the pixel circuit of the corresponding sub-pixel.

[0021] In some possible embodiments, it further includes: at least one row of virtual sub-pixels and a plurality of switch control circuits, and the switch control circuits are arranged in one-to-one correspondence with the virtual sub-pixels;

[0022] The virtual sub-pixel includes a virtual pixel circuit, and the virtual pixel circuit is coupled to a light-emitting device in the first row of sub-pixels through the corresponding switch control circuit. The switch control circuit is configured to, in response to a signal from the first control signal terminal, provide a driving current generated by the virtual pixel circuit to the light-emitting device in the first row of sub-pixels.

[0023] The display device provided by an embodiment of the present invention includes the above-mentioned display panel.

[0024] A driving method for a display panel provided by an embodiment of the present invention includes: controlling, row by row, a pixel circuit in the sub-pixel to drive the light-emitting device to emit light;

[0025] When the pixel circuit is operating, it is successively in a data writing stage, a reset stage, and a light-emitting stage;

[0026] When the pixel circuit in the nth row of sub-pixels is in the light-emitting stage, the pixel circuit in the (n + 1)th row of sub-pixels is in the data writing stage, and the driving control circuit connected between a first pole of the pixel circuit in the nth row of sub-pixels and the light-emitting device in the (n + 1)th row of sub-pixels, in response to a signal from the first control signal terminal, transmits a first driving current generated by the pixel circuit in the nth row of sub-pixels and / or a second driving current generated according to a data voltage in the pixel circuit in the nth row of sub-pixels to the light-emitting device in the (n + 1)th row of sub-pixels.

[0027] In some possible embodiments, the cut-off moment of the effective level of the first control signal terminal in the driving control circuit corresponding to the nth row pixel circuit is not earlier than the cut-off moment of the data writing stage of the pixel circuit in the (n + 1)th row of sub-pixels.

[0028] In some possible embodiments, the time when the first control signal terminal in the driving control circuit corresponding to the nth row pixel circuit is loaded with an effective level does not overlap with the reset stage of the pixel circuit in the (n + 1)th row of sub-pixels. Description of the Drawings

[0029] Figure 1 Some structural schematic diagrams of the display panel provided by an embodiment of the present invention;

[0030] Figure 2 Some other structural schematic diagrams of the display panel provided by an embodiment of the present invention;

[0031] Figure 3 Some other structural schematic diagrams of the display panel provided by the embodiment of the present utility model;

[0032] Figure 4 Some other structural schematic diagrams of the display panel provided by the embodiment of the present utility model;

[0033] Figure 5 Some signal timing diagrams provided by the embodiment of the present utility model;

[0034] Figure 6 Some other structural schematic diagrams of the display panel provided by the embodiment of the present utility model;

[0035] Figure 7 Some other structural schematic diagrams of the display panel provided by the embodiment of the present utility model;

[0036] Figure 8 Some other structural schematic diagrams of the display panel provided by the embodiment of the present utility model;

[0037] Figure 9 Some other structural schematic diagrams of the display panel provided by the embodiment of the present utility model;

[0038] Figure 10 Some other structural schematic diagrams of the display panel provided by the embodiment of the present utility model;

[0039] Figure 11 Some other structural schematic diagrams of the display panel provided by the embodiment of the present utility model;

[0040] Figure 12 Some other signal timing diagrams provided by the embodiment of the present utility model. Detailed implementation manners

[0041] To make the objectives, technical solutions and advantages of the embodiments of the present utility model clearer, the technical solutions of the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present utility model. Obviously, the described embodiments are some but not all of the embodiments of the present utility model. And without conflict, the embodiments in the present utility model and the features in the embodiments can be combined with each other. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present utility model without creative efforts shall fall within the protection scope of the present utility model.

[0042] Unless otherwise defined, the technical terms or scientific terms used in this utility model shall have the ordinary meanings understood by those of ordinary skill in the field to which this utility model belongs. The "first", "second" and similar terms used in this utility model do not denote any order, quantity or importance, but are only used to distinguish different components. Words such as "comprising" or "including" mean that the elements or objects appearing before this word cover the elements or objects listed after this word and their equivalents, without excluding other elements or objects. Words such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0043] It should be noted that the sizes and shapes of the various figures in the drawings do not reflect the true proportions, and the purpose is only to schematically illustrate the content of this utility model. Also, the same or similar reference numerals throughout denote the same or similar elements or elements having the same or similar functions.

[0044] The display device provided by the embodiment of this utility model includes: a display panel, and the display area of the display panel includes a plurality of pixel units arranged in an array. Exemplarily, each pixel unit includes a plurality of sub-pixels. For example, each pixel unit may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, so that color mixing can be performed through red, green, and blue to achieve color display. Or, the pixel unit may also include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, so that color mixing can be performed through red, green, blue, and white to achieve color display. Of course, in actual applications, the emission colors of the sub-pixels in the pixel unit can be designed and determined according to the actual application environment, and are not limited herein.

[0045] In the embodiment of this utility model, each sub-pixel includes a pixel circuit, and the pixel circuit includes a driving transistor and a light-emitting device to drive the light-emitting device to emit light, so that the display panel realizes the function of displaying an image. Due to reasons such as process manufacturing and device aging, the threshold voltage Vth of the driving transistor is non-uniform, which causes the current flowing through different light-emitting devices to change, resulting in uneven display brightness and affecting the display effect of the entire image. In order to make the brightness of the display panel more uniform and the display more perfect, generally, an additional data writing stage is required to eliminate the influence of the drift or non-uniformity of the threshold voltage Vth of the driving transistor through internal compensation and other methods.

[0046] During the data writing stage, data is written line by line to the pixel circuits in the sub-pixels. At this time, the light-emitting devices in the sub-pixels do not emit light and present a dark state; during the light-emitting stage, the light-emitting devices in the sub-pixels emit light and present a bright state. The data writing stage is shorter in time compared to the light-emitting stage, so the human eye cannot perceive it, that is, the human eye can only observe the uniform display during the light-emitting stage. However, the camera can sense it. For a display panel with a relatively low refresh rate (for example, less than 1000HZ), when writing data line by line, the shutter of the camera can capture the black scan lines of the display panel.

[0047] Currently, the black scan lines of the display panel can be eliminated by increasing the refresh rate of the display panel. However, for a display panel with a relatively low refresh rate, there will still be black scan lines. Therefore, other methods other than increasing the refresh rate are needed to solve the problem of black scan lines.

[0048] Based on the above problems, the display panel provided by the embodiments of the present invention, as Figure 1 shown, the display panel includes:

[0049] A plurality of sub-pixels spx, each sub-pixel spx includes: a light-emitting device L and a pixel circuit 10 coupled to the first pole of the light-emitting device L;

[0050] A plurality of driving control circuits 20, the pixel circuit 10 in the nth row of sub-pixels is coupled to the first pole of the light-emitting device L in the (n + 1)th row of sub-pixels through at least one driving control circuit 20. The driving control circuit 20 is configured to respond to the signal of the first control signal terminal CS1 and transmit the first driving current generated by the pixel circuit 10 in the nth row of sub-pixels and / or the second driving current generated according to the data voltage in the pixel circuit 10 in the nth row of sub-pixels to the light-emitting device L in the (n + 1)th row of sub-pixels; wherein, n is a positive integer greater than 0.

[0051] The embodiments of the present invention can improve the problem that the light-emitting brightness of the nth row of sub-pixels is inconsistent with the light-emitting brightness of the (n + 1)th row of sub-pixels, that is, improve the problem of inconsistent light-emitting brightness between adjacent two rows of sub-pixels, and avoid the problem of black scan lines on the display panel by setting the driving control circuit to transmit the first driving current generated by the pixel circuit in the nth row of sub-pixels and / or the second driving current generated according to the data voltage in the pixel circuit in the nth row of sub-pixels to the light-emitting device in the (n + 1)th row of sub-pixels, thereby improving the display effect and competitiveness of the display product.

[0052] In the embodiments of the present invention, as Figure 2As shown, the pixel circuit 10 further includes: a first driving transistor M0; the driving control circuit 20 is configured to transmit a second driving current generated according to the data voltage in the pixel circuit 10 in the sub-pixels of the n-th row to the light-emitting device L in the sub-pixels of the (n + 1)-th row in response to the signal at the first control signal terminal CS1; wherein, the driving control circuit 20 includes: a second driving transistor T02 and a second switching transistor T2; the gate of the second driving transistor T02 is coupled to the gate of the first driving transistor M0 in the pixel circuit 10 in the sub-pixels of the n-th row, the first pole of the second driving transistor T02 is coupled to the first pole of the first driving transistor M0 in the pixel circuit 10 in the sub-pixels of the n-th row, and the second pole of the second driving transistor T02 is coupled to the first pole of the second switching transistor T2; the gate of the second switching transistor T2 is coupled to the first control signal terminal CS1, and the second pole of the second switching transistor T2 is coupled to the light-emitting device L in the sub-pixels 10 of the (n + 1)-th row.

[0053] Wherein, if the first driving current and the second driving current are the same, the light-emitting brightness of the light-emitting device L in the sub-pixels of the n-th row is the same as the light-emitting brightness of the light-emitting device L in the sub-pixels of the (n + 1)-th row.

[0054] Exemplarily, the second switching transistor T2 can be turned on under the control of the effective level of the first control signal transmitted on the first control signal terminal CS1 and can be turned off under the control of the invalid level of the first control signal. For example, if the second switching transistor T2 is set as an N-type transistor, the effective level of the first control signal is a high level and the invalid level of the first control signal is a low level. Alternatively, if the second switching transistor T2 is set as a P-type transistor, the effective level of the first control signal is a low level and the invalid level of the first control signal is a high level.

[0055] The present utility model Figure 2 The driving control circuit 20 therein can ensure that the light-emitting brightness of the light-emitting device in the sub-pixels of the n-th row is the same as the light-emitting brightness of the light-emitting device in the sub-pixels of the (n + 1)-th row, and a second driving transistor is provided. Since a first driving transistor is provided in the pixel circuit, the light-emitting brightness of the light-emitting device in the sub-pixels of the n-th row and the light-emitting brightness of the light-emitting device in the sub-pixels of the (n + 1)-th row can be ensured respectively, avoiding the problem that the light-emitting device is not bright enough, and improving the problem of inconsistent light-emitting brightness between adjacent two rows of sub-pixels, thereby avoiding the problem of black scan lines in the display panel and improving the display effect.

[0056] In the embodiment of the present utility model, the first driving transistor M0 and the second driving transistor T02 can be set as N-type transistors; wherein, the first pole of the first driving transistor M0 and the second driving transistor T02 can be their source electrodes, the second pole of the first driving transistor M0 and the second driving transistor T02 can be their drain electrodes, and when the first driving transistor M0 and the second driving transistor T02 are in the saturation state, the current flows from the drain electrodes of the first driving transistor M0 and the second driving transistor T02 to their source electrodes; of course, the first driving transistor M0 and the second driving transistor T02 can also be set as P-type transistors, and when the first driving transistor M0 and the second driving transistor T02 are in the saturation state, the current flows from the source electrodes of the first driving transistor M0 and the second driving transistor T02 to their drain electrodes; this is not limited herein.

[0057] Moreover, the light-emitting device L generally emits light under the action of the current when the first driving transistor M0 and the second driving transistor T02 are in the saturation state. Of course, in the embodiment of the present utility model, only the case where the first driving transistor M0 and the second driving transistor T02 are P-type transistors is taken as an example for illustration. For the case where the first driving transistor M0 and the second driving transistor T02 are N-type transistors, the design principle is the same as that of the present utility model and also falls within the protection scope of the present utility model.

[0058] In the embodiment of the present utility model, as Figure 2 shown, the second pole of the light-emitting device L is coupled to the second power supply terminal VSS; exemplarily, the light-emitting device L can be an electroluminescent diode. For example, the light-emitting device L can include at least one of: Organic Light Emitting Diode (OLED), Quantum Dot Light Emitting Diodes (QLED), Micro Light Emitting Diode (Micro LED), Mini Light Emitting Diode (Mini LED), etc. Exemplarily, the light-emitting device L can include an anode, a light-emitting layer, and a cathode arranged in a stacked manner. Further, the light-emitting layer can also include film layers such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer. Of course, in actual applications, the specific structure of the light-emitting device L can be determined according to the actual application requirements, and this is not limited herein.

[0059] In the embodiment of the present utility model, as Figure 2As shown, the pixel circuit 10 further includes: a data writing circuit, coupled to the first pole of the first driving transistor M0, and configured to provide the data voltage of the data signal terminal DA to the first pole of the first driving transistor M0 in response to the signal of the first scan signal terminal SS1; wherein, the data writing circuit includes: a first transistor M1; the gate of the first transistor M1 is coupled to the first scan signal terminal SS1, the first pole of the first transistor M1 is coupled to the first pole of the first driving transistor M0, and the second pole of the first transistor M1 is coupled to the data signal terminal DA.

[0060] Exemplarily, the first transistor M1 can be turned on under the control of the effective level of the first scan signal transmitted on the first scan signal terminal SS1, and can be turned off under the control of the invalid level of the first scan signal. For example, the first transistor M1 can be set as an N-type transistor, then the effective level of the first scan signal is a high level, and the invalid level of the first scan signal is a low level. Or, the first transistor M1 can be set as a P-type transistor, then the effective level of the first scan signal is a low level, and the invalid level of the first scan signal is a high level.

[0061] In the embodiment of the present invention, as Figure 2 shown, the pixel circuit 10 further includes: a conduction control circuit, coupled to the second pole and the gate of the first driving transistor M0, and configured to conduct the second pole and the gate of the first driving transistor M0 in response to the signal of the first scan signal terminal SS1; wherein, the conduction control circuit includes: a second transistor M2 and a first capacitor C1; the gate of the second transistor M2 is coupled to the first scan signal terminal SS1, the first pole of the second transistor M2 is coupled to the second pole of the first driving transistor M0, and the second pole of the second transistor M2 is coupled to the gate of the first driving transistor M0; the first electrode of the first capacitor C1 is coupled to the first power supply terminal VDD, and the second electrode of the first capacitor C1 is coupled to the gate of the first driving transistor M0.

[0062] Exemplarily, the second transistor M2 can be turned on under the control of the effective level of the first scan signal transmitted on the first scan signal terminal SS1, and can be turned off under the control of the invalid level of the first scan signal. For example, the second transistor M2 can be set as an N-type transistor, then the effective level of the first scan signal is a high level, and the invalid level of the first scan signal is a low level. Or, the second transistor M2 can be set as a P-type transistor, then the effective level of the first scan signal is a low level, and the invalid level of the first scan signal is a high level.

[0063] In the embodiment of the present invention, as Figure 2As shown, the pixel circuit 10 further includes: a reset circuit, coupled to the gate of the first driving transistor M0 and the light-emitting device L, configured to provide the signal of the initialization signal terminal Vint to the gate of the first driving transistor M0 in response to the signal of the first reset signal terminal RE1, and provide the signal of the initialization signal terminal Vint to the light-emitting device L in response to the signal of the second reset signal terminal RE2; wherein, the reset circuit includes: a third transistor M3 and a fourth transistor M4; the gate of the third transistor M3 is coupled to the first reset signal terminal RE1, the first pole of the third transistor M3 is coupled to the gate of the first driving transistor M0, and the second pole of the third transistor M3 is coupled to the initialization signal terminal Vint; the gate of the fourth transistor M4 is coupled to the second reset signal terminal RE2, the first pole of the fourth transistor M4 is coupled to the light-emitting device L, and the second pole of the fourth transistor M4 is coupled to the initialization signal terminal Vint.

[0064] Exemplarily, the third transistor M3 can be turned on under the control of the effective level of the first reset signal transmitted on the first reset signal terminal RE1, and can be turned off under the control of the invalid level of the first reset signal. For example, if the third transistor M3 is set as an N-type transistor, the effective level of the first reset signal is a high level, and the invalid level of the first reset signal is a low level. Alternatively, if the third transistor M3 is set as a P-type transistor, the effective level of the first reset signal is a low level, and the invalid level of the first reset signal is a high level.

[0065] Exemplarily, the fourth transistor M4 can be turned on under the control of the effective level of the second reset signal transmitted on the second reset signal terminal RE2, and can be turned off under the control of the invalid level of the second reset signal. For example, if the fourth transistor M4 is set as an N-type transistor, the effective level of the second reset signal is a high level, and the invalid level of the second reset signal is a low level. Alternatively, if the fourth transistor M4 is set as a P-type transistor, the effective level of the second reset signal is a low level, and the invalid level of the second reset signal is a high level.

[0066] In the embodiment of the present utility model, as Figure 2As shown, the pixel circuit 10 further includes: a light-emitting control circuit, coupled to the first pole of the first driving transistor M0, the second pole of the first driving transistor M0, and the light-emitting device L, and configured to, in response to a signal of the light-emitting control signal terminal EM, provide a signal of the first power supply terminal VDD to the first pole of the first driving transistor M0, and conduct the second pole of the first driving transistor M0 and the light-emitting device L; wherein, the light-emitting control circuit includes: a fifth transistor M5 and a sixth transistor M6; a gate of the fifth transistor M5 is coupled to the light-emitting control signal terminal EM, a first pole of the fifth transistor M5 is coupled to the first power supply terminal VDD, and a second pole of the fifth transistor M5 is coupled to the first pole of the first driving transistor M0; a gate of the sixth transistor M6 is coupled to the light-emitting control signal terminal EM, a first pole of the sixth transistor M6 is coupled to the second pole of the first driving transistor M0, and a second pole of the sixth transistor M6 is coupled to the light-emitting device L.

[0067] Exemplarily, the fifth transistor M5 and the sixth transistor M6 can be turned on under the control of the effective level of the light-emitting control signal transmitted on the light-emitting control signal terminal EM, and can be turned off under the control of the invalid level of the light-emitting control signal. For example, the fifth transistor M5 and the sixth transistor M6 can be set as N-type transistors, then the effective level of the light-emitting control signal is a high level, and the invalid level of the light-emitting control signal is a low level. Or, the fifth transistor M5 and the sixth transistor M6 can also be set as P-type transistors, then the effective level of the light-emitting control signal is a low level, and the invalid level of the scanning signal is a high level.

[0068] Exemplarily, the first pole of the above transistor can be its source pole, and the second pole can be its drain pole. Or, the first pole is its drain pole, and the second pole is its source pole. This is not limited herein.

[0069] Generally, the leakage current of a transistor using a metal oxide semiconductor material as the active layer is small. Therefore, in some embodiments of the present invention, in order to reduce the leakage current, the material of the active layer of the above transistor can include a metal oxide semiconductor material. For example, it can be IGZO (Indium Gallium Zinc Oxide), and of course, it can also be other metal oxide semiconductor materials, which is not limited herein. In this way, the above transistor can be set as an oxide thin film transistor (Oxide Thin Film Transistor) to reduce the leakage current of the pixel circuit.

[0070] Generally, low temperature poly-silicon (LTPS) materials are used as the active layer of transistors, which have high mobility, can be made thinner, smaller, and have lower power consumption. In specific implementations, the material of the active layer of the above transistors can also be set to low temperature poly-silicon materials. In this way, the above transistors can be set as LTPS transistors, so that the pixel circuit can achieve high mobility, be made thinner, smaller, and have lower power consumption.

[0071] Exemplarily, all transistors in the pixel circuit and the drive control circuit of the present invention can be set as oxide transistors, or all transistors in the pixel circuit and the drive control circuit of the present invention can be set as LTPS transistors, or some transistors in the pixel circuit and the drive control circuit of the present invention can be set as oxide transistors, and the other part of the transistors can be set as LTPS transistors.

[0072] In the embodiments of the present invention, the first power supply terminal VDD can be configured to load a constant first power supply voltage vdd, and the first power supply voltage vdd is generally positive. Also, the second power supply terminal VSS can load a constant second power supply voltage vss, and the second power supply voltage vss can generally be a ground voltage or a negative value. In practical applications, the specific values of the first power supply voltage vdd and the second power supply voltage vss can be designed and determined according to the actual application environment, and are not limited herein.

[0073] The above is only an example to illustrate the specific structures of the respective circuits in the pixel circuit provided by the embodiments of the present invention. In specific implementations, the specific structure of the above pixel circuit is not limited to the above structure provided by the embodiments of the present invention, and can also be other structures known to those skilled in the art, as long as these are within the protection scope of the present invention, and are not specifically limited herein.

[0074] In the embodiments of the present invention, as Figure 1 shown, a drive control circuit 20 is correspondingly provided for each sub-pixel spx in the first row to the (N - 1)th row, and the first pole of the light-emitting device L in the nth row sub-pixel spx and the (n + 1)th row sub-pixel spx in the same column is coupled through the corresponding drive control circuit 20.

[0075] In the embodiments of the present invention, as Figure 1 shown, the drive control circuit 20 is integrally provided in the pixel circuit 10 of the corresponding sub-pixel spx. Such a setting can save more space and improve the space utilization rate of the circuit.

[0076] In the embodiments of the present invention, as Figure 3As shown, the driving control circuit 20 is located between the pixel circuits 10 in two adjacent rows of sub-pixels spx. Such an arrangement can flexibly adjust the position of the driving control circuit, facilitate wiring, and simplify the circuit design.

[0077] In an embodiment of the present invention, as Figure 4 shown, the driving control circuit 20 is located between the pixel circuits 10 in two adjacent columns of sub-pixels spx. Such an arrangement can flexibly adjust the position of the driving control circuit, facilitate wiring, and simplify the circuit design.

[0078] In the embodiment of the present invention, an example will be given in which the driving control circuit is integrally arranged in the pixel circuit of the corresponding sub-pixel.

[0079] Next, taking Figure 2 the circuit structure shown as an example, combined with Figure 5 the signal timing diagram shown, the working process of the circuit provided in the embodiment of the present invention will be described.

[0080] Among them, as Figure 5 shown, em(n) represents the emission control signal of the emission control signal terminal EM in the nth row of sub-pixels; re1(n) represents the first reset signal of the first reset signal terminal RE1 in the nth row of sub-pixels; ss1(n) represents the first scan signal of the first scan signal terminal SS1 in the nth row of sub-pixels; re2(n) represents the second reset signal of the second reset signal terminal RE2 in the nth row of sub-pixels; cs1(n) represents the first control signal of the first control signal terminal CS1 in the driving control circuit corresponding to the nth row of sub-pixels; em(n + 1) represents the emission control signal of the emission control signal terminal EM in the (n + 1)th row of sub-pixels; re1(n + 1) represents the first reset signal of the first reset signal terminal RE1 in the (n + 1)th row of sub-pixels; ss1(n + 1) represents the first scan signal of the first scan signal terminal SS1 in the (n + 1)th row of sub-pixels; re2(n + 1) represents the second reset signal of the second reset signal terminal RE2 in the (n + 1)th row of sub-pixels.

[0081] When the pixel circuit in the n-th row of sub-pixels is in the light-emitting stage F3, for the pixel circuit 10 in the n-th row of sub-pixels, the fifth transistor M5 and the sixth transistor M6 are turned on under the control of the low level of the light-emitting control signal em(n), and the second switching transistor T2 in the driving control circuit 20 correspondingly set for the n-th row of sub-pixels is turned on under the control of the low level of the first control signal cs1(n); the first driving transistor M0 in the pixel circuit 10 in the n-th row of sub-pixels generates a first driving current according to the data voltage; the second driving transistor T02 in the driving control circuit 20 correspondingly set for the n-th row of sub-pixels generates a second driving current according to the data voltage; the turned-on fifth transistor M5 supplies the signal of the first power supply terminal VDD to the first pole of the first driving transistor M0, and the turned-on sixth transistor M6 conducts the second pole of the first driving transistor M0 and the light-emitting device L, that is, supplies the first driving current to the light-emitting device L in the n-th row of sub-pixels, so that the light-emitting device L in the n-th row of sub-pixels emits light normally; the turned-on second switching transistor T2 supplies the second driving current to the light-emitting device L in the (n + 1)-th row of sub-pixels, so that the light-emitting device L in the (n + 1)-th row of sub-pixels also emits light normally;

[0082] At this time, the pixel circuit in the (n + 1)-th row of sub-pixels is in the data writing stage F1. For the pixel circuit 10 in the (n + 1)-th row of sub-pixels, first, the third transistor M3 is turned on under the control of the low level of the first reset signal re1(n), and supplies the signal of the initialization signal terminal Vint to the gate of the first driving transistor M0 to initialize the gate of the first driving transistor M0; secondly, the first transistor M1 and the second transistor M2 are turned on under the control of the low level of the first scanning signal ss1(n). The turned-on first transistor M1 supplies the data voltage of the data signal terminal DA to the first pole of the first driving transistor M0, and the turned-on second transistor M2 conducts the second pole of the first driving transistor M0 and the gate of the first driving transistor M0, so as to complete the compensation of the threshold voltage Vth of the first driving transistor M0 and the compensation of the threshold voltage Vth of the second driving transistor T02 in the driving control circuit 20 correspondingly set for the (n + 1)-th row of sub-pixels.

[0083] The embodiment of the present invention provides another structural schematic diagram of the driving control circuit, as Figure 6 shown, which is a deformation of the implementation manner in the above embodiment. Only the differences between this embodiment and the above embodiment will be described below, and the same parts will not be elaborated here.

[0084] In the embodiment of the present invention, as Figure 6As shown, the driving control circuit 20 is configured to transmit a first driving current generated by the pixel circuit 10 in the n-th row of sub-pixels and a second driving current generated according to the data voltage in the pixel circuit 10 in the n-th row of sub-pixels to the light-emitting device L in the (n + 1)-th row of sub-pixels in response to a signal at the first control signal terminal CS1; wherein, the driving control circuit 20 includes: a third driving transistor T03, a third switching transistor T3, and a fourth switching transistor T4; the gate of the third driving transistor T03 is coupled to the gate of the first driving transistor M0 in the pixel circuit 10 in the n-th row of sub-pixels, the first pole of the third driving transistor T03 is coupled to the first pole of the first driving transistor M0 in the pixel circuit 10 in the n-th row of sub-pixels, and the second pole of the third driving transistor T03 is coupled to the first pole of the third switching transistor T3; the gate of the third switching transistor T3 is coupled to the first control signal terminal CS1, and the second pole of the third switching transistor T3 is coupled to the second pole of the first driving transistor T3 in the pixel circuit 10 in the n-th row of sub-pixels; the gate of the fourth switching transistor T4 is coupled to the first control signal terminal CS1, the first pole of the fourth switching transistor T4 is coupled to the light-emitting device L in the pixel circuit 10 in the n-th row of sub-pixels, and the second pole of the fourth switching transistor T4 is coupled to the light-emitting device L in the (n + 1)-th row of sub-pixels.

[0085] The driving control circuit in the present utility model Figure 6 compared with the driving control circuit in Figure 2 the driving control circuit in the present embodiment of the utility model can more accurately ensure that the magnitudes of the driving currents transmitted to the light-emitting devices in the n-th row of sub-pixels and the (n + 1)-th row of sub-pixels are the same, avoiding the problem of inconsistent driving current magnitudes caused by process differences between the third driving transistor in the driving control circuit and the first driving transistor in the pixel circuit. That is, the driving control circuit in the present embodiment of the utility model further ensures that the light-emitting brightness of the light-emitting devices in adjacent rows of sub-pixels is the same, thereby more effectively improving the black scan line problem of the display panel, and further enhancing the display effect and competitiveness of the product.

[0086] Next, taking the Figure 6 circuit structure shown as an example and combining with the Figure 5 signal timing diagram shown, the working process of the circuit provided in the embodiment of the present utility model will be described.

[0087] When the pixel circuit in the n-th row of sub-pixels is in the light-emitting stage F3, for the pixel circuit 10 in the n-th row of sub-pixels, the fifth transistor M5 and the sixth transistor M6 are turned on under the control of the low level of the light-emitting control signal em(n). The third switching transistor T3 and the fourth switching transistor T4 in the driving control circuit 20 correspondingly set for the n-th row of sub-pixels are turned on under the control of the low level of the first control signal cs1(n). The first driving transistor M0 in the pixel circuit 10 of the n-th row of sub-pixels generates a first driving current according to the data voltage. The third driving transistor T03 in the driving control circuit 20 correspondingly set for the n-th row of sub-pixels generates a second driving current according to the data voltage. The turned-on fifth transistor M5 supplies the signal of the first power supply terminal VDD to the first pole of the first driving transistor M0. The turned-on third switching transistor T3 supplies the second driving current to the first pole of the sixth transistor M6. The turned-on sixth transistor M6 conducts the second pole of the first driving transistor M0 to the light-emitting device L, that is, supplies the first driving current and the second driving current to the light-emitting device L in the n-th row of sub-pixels, so that the light-emitting device L in the n-th row of sub-pixels emits light normally. The turned-on fourth switching transistor T4 supplies the first driving current and the second driving current to the light-emitting device L in the (n + 1)-th row of sub-pixels, so that the light-emitting device L in the (n + 1)-th row of sub-pixels also emits light normally.

[0088] At this time, the pixel circuit in the (n + 1)-th row of sub-pixels is in the data writing stage F1. For the pixel circuit 10 in the (n + 1)-th row of sub-pixels, first, the third transistor M3 is turned on under the control of the low level of the first reset signal re1(n), and supplies the signal of the initialization signal terminal Vint to the gate of the first driving transistor M0 to initialize the gate of the first driving transistor M0. Secondly, the first transistor M1 and the second transistor M2 are turned on under the control of the low level of the first scan signal ss1(n). The turned-on first transistor M1 supplies the data voltage of the data signal terminal DA to the first pole of the first driving transistor M0. The turned-on second transistor M2 conducts the second pole of the first driving transistor M0 to the gate of the first driving transistor M0, thereby completing the compensation of the threshold voltage Vth of the first driving transistor M0 and the compensation of the threshold voltage Vth of the third driving transistor T03 in the driving control circuit 20 correspondingly set for the (n + 1)-th row of sub-pixels.

[0089] Some structural schematic diagrams of the driving control circuit are provided in the embodiments of the present invention, such as Figure 7 shown, which are deformed for the implementation manners in the above embodiments. Only the differences between this embodiment and the above embodiments will be described below, and the same parts will not be elaborated here.

[0090] In the embodiments of the present invention, as Figure 7As shown, the driving control circuit 20 is configured to transmit the first driving current generated by the pixel circuit 10 in the n-th row of sub-pixels to the light-emitting device L in the (n + 1)-th row of sub-pixels in response to the signal of the first control signal terminal CS1; wherein, the driving control circuit 20 includes: a first switching transistor T1; the gate of the first switching transistor T1 is coupled to the first control signal terminal CS1, the first pole of the first switching transistor T1 is coupled to the light-emitting device L in the pixel circuit 10 in the n-th row of sub-pixels, and the second pole of the first switching transistor T1 is coupled to the light-emitting device L in the pixel circuit 10 in the (n + 1)-th row of sub-pixels.

[0091] The driving control circuit in the present utility model Figure 7 compared with the driving control circuit in Figure 2 the driving control circuit in the driving control circuit in the embodiment of the present utility model only requires one switching transistor, which can reduce the production cost and also reduce the power consumption.

[0092] Next, taking the Figure 7 circuit structure shown as an example and combining with the Figure 5 signal timing diagram shown, the working process of the circuit provided by the embodiment of the present utility model will be described.

[0093] When the pixel circuit in the n-th row of sub-pixels is in the light-emitting stage F3, for the pixel circuit 10 in the n-th row of sub-pixels, the fifth transistor M5 and the sixth transistor M6 are turned on under the control of the low level of the light-emitting control signal em(n), and the first switching transistor T1 in the driving control circuit 20 corresponding to the n-th row of sub-pixels is turned on under the control of the low level of the first control signal cs1(n); the first driving transistor M0 in the pixel circuit 10 in the n-th row of sub-pixels generates a first driving current according to the data voltage; the turned-on fifth transistor M5 provides the signal of the first power supply terminal VDD to the first pole of the first driving transistor M0; the turned-on sixth transistor M6 conducts the second pole of the first driving transistor M0 to the light-emitting device L, that is, provides the first driving current to the light-emitting device L in the n-th row of sub-pixels, so that the light-emitting device L in the n-th row of sub-pixels emits light normally; the turned-on first switching transistor T1 provides the first driving current to the light-emitting device L in the (n + 1)-th row of sub-pixels, so that the light-emitting device L in the (n + 1)-th row of sub-pixels also emits light normally;

[0094] At this time, the pixel circuits in the sub-pixels of the (n + 1)-th row are in the data writing stage F1. For the pixel circuit 10 in the sub-pixels of the (n + 1)-th row, first, the third transistor M3 is turned on under the control of the low level of the first reset signal re1(n), and the signal of the initialization signal terminal Vint is provided to the gate of the first driving transistor M0 to initialize the gate of the first driving transistor M0. Secondly, the first transistor M1 and the second transistor M2 are turned on under the control of the low level of the first scanning signal ss1(n). The turned-on first transistor M1 provides the data voltage of the data signal terminal DA to the first pole of the first driving transistor M0, and the turned-on second transistor M2 connects the second pole of the first driving transistor M0 to the gate of the first driving transistor M0, thereby completing the compensation of the threshold voltage Vth of the first driving transistor M0.

[0095] In the embodiment of the present invention, as Figure 8 shown, it further includes: at least one row of virtual sub-pixels spx0 and a plurality of switch control circuits 40, and the switch control circuits 40 are arranged in one-to-one correspondence with the virtual sub-pixels spx0;

[0096] The virtual sub-pixel spx0 includes a virtual pixel circuit 30. The virtual pixel circuit 30 is coupled to the light-emitting device L in the sub-pixels of the first row through the corresponding switch control circuit 40. The switch control circuit 40 is configured to respond to the signal of the first control signal terminal CS1 and provide the driving current generated by the virtual pixel circuit 30 to the light-emitting device L in the sub-pixels of the first row.

[0097] Through the mutual cooperation of the virtual pixel circuit and the switch control circuit in the virtual sub-pixel in the present invention, the problem that the light-emitting device in the sub-pixels of the first row cannot emit light during the data writing stage is avoided, that is, the problem that the brightness of the light-emitting device in the sub-pixels of the first row is inconsistent with that of the light-emitting device in the sub-pixels of the second row is avoided, and the black scan line problem of the display panel is better improved, and the display effect is improved.

[0098] In the embodiment of the present invention, when the virtual pixel circuit works, it is successively in the data writing stage, the reset stage, and the light-emitting stage. However, since there is no light-emitting device in the virtual sub-pixel, the virtual sub-pixel does not emit light.

[0099] In the embodiment of the present invention, as Figures 9 to 11 shown, the switch control circuit 40 includes: a switch control transistor T0. The gate of the switch control transistor T0 is coupled to the first control signal terminal CS1. The first pole of the switch control transistor T0 is coupled to the second pole of the sixth transistor M6 in the virtual pixel circuit 30. The second pole of the switch control transistor T0 is coupled to the first pole of the light-emitting device L in the sub-pixels of the first row.

[0100] Exemplarily, the switching control transistor T0 can be turned on under the control of the effective level of the first scan signal transmitted on the first scan signal terminal SS1, and can be turned off under the control of the ineffective level of the first scan signal. For example, if the switching control transistor T0 is set as an N-type transistor, the effective level of the first scan signal is a high level, and the ineffective level of the first scan signal is a low level. Alternatively, if the switching control transistor T0 is set as a P-type transistor, the effective level of the first scan signal is a low level, and the ineffective level of the first scan signal is a high level.

[0101] In the embodiment of the present invention, drive control circuits can be respectively and correspondingly arranged for the last row of sub-pixels in the display panel. Among them, no effective level signal is loaded on the first control signal terminal in the drive control circuit correspondingly arranged for the last row of sub-pixels. Such an arrangement can simplify the process and simplify the circuit layout setting.

[0102] In the embodiment of the present invention, the last row of sub-pixels in the display panel may not be correspondingly provided with a drive control circuit. Such an arrangement can reduce costs and reduce power consumption.

[0103] Next, taking Figure 9 the circuit structure shown as an example, in combination with Figure 12 the signal timing diagram shown, the working process of the circuit of the present invention will be described.

[0104] Among them, as Figure 12 shown, em(0) represents the light emission control signal of the light emission control signal terminal EM in the virtual sub-pixel; re1(0) represents the first reset signal of the first reset signal terminal RE1 in the virtual sub-pixel; ss1(0) represents the first scan signal of the first scan signal terminal SS1 in the virtual sub-pixel; re2(0) represents the second reset signal of the second reset signal terminal RE2 in the virtual sub-pixel; cs1(0) represents the first control signal of the first control signal terminal CS1 in the corresponding switching control circuit in the virtual sub-pixel; em(1) represents the light emission control signal of the light emission control signal terminal EM in the first row of sub-pixels; re1(1) represents the first reset signal of the first reset signal terminal RE1 in the first row of sub-pixels; ss1(1) represents the first scan signal of the first scan signal terminal SS1 in the first row of sub-pixels; re2(1) represents the second reset signal of the second reset signal terminal RE2 in the first row of sub-pixels.

[0105] When the virtual pixel circuit in the virtual sub-pixel is in the light-emitting stage F3, for the virtual pixel circuit 30 in the virtual sub-pixel, the fifth transistor M5 and the sixth transistor M6 are turned on under the control of the low level of the light-emitting control signal em(0), and the switching control transistor T0 in the switching control circuit 40 corresponding to the virtual sub-pixel is turned on under the control of the low level of the first control signal cs1(0); the first driving transistor M0 in the virtual pixel circuit 30 in the virtual sub-pixel generates a driving current according to the data voltage; the turned-on fifth transistor M5 supplies the signal of the first power supply terminal VDD to the first pole of the first driving transistor M0, and the turned-on sixth transistor M6 conducts the second pole of the first driving transistor M0 and the first pole of the switching control transistor T0, that is, supplies the driving current to the first pole of the switching control transistor T0; the turned-on switching control transistor T0 supplies the driving current at the first pole to the light-emitting device L in the first row of sub-pixels, and then the light-emitting device L in the first row of sub-pixels emits light normally when in the data writing stage F1.

[0106] At this time, the pixel circuit in the first row of sub-pixels is in the data writing stage F1. For the pixel circuit 10 in the first row of sub-pixels, first, the third transistor M3 is turned on under the control of the low level of the first reset signal re1(0), and supplies the signal of the initialization signal terminal Vi0t to the gate of the first driving transistor M0 to initialize the gate of the first driving transistor M0; secondly, the first transistor M1 and the second transistor M2 are turned on under the control of the low level of the first scan signal ss1(0). The turned-on first transistor M1 supplies the data voltage of the data signal terminal DA to the first pole of the first driving transistor M0, and the turned-on second transistor M2 conducts the second pole of the first driving transistor M0 and the gate of the first driving transistor M0, thereby completing the compensation of the threshold voltage Vth of the first driving transistor M0 and the compensation of the threshold voltage Vth of the second driving transistor T02 in the driving control circuit 20 corresponding to the first row of sub-pixels.

[0107] Based on the same inventive concept, an embodiment of the present invention further provides a display device, including the above display panel provided by the embodiment of the present invention. The principle of the display device to solve the problem is similar to that of the foregoing display panel. Therefore, the implementation of the display device can refer to the implementation of the foregoing display panel, and the repeated parts will not be described herein again.

[0108] In specific implementation, in the embodiment of the present invention, the display device may be: a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any product or component with a display function. Other essential components of the display device should be understood by those of ordinary skill in the art and will not be described herein, nor should it be regarded as a limitation to the present invention.

[0109] Although the preferred embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications once they learn the basic creative concepts. Therefore, the appended claims are intended to be construed as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0110] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and variations of the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these modifications and variations.

Claims

1. A display panel, wherein: include: A plurality of sub-pixels, each of the sub-pixels comprising: a light emitting device and a pixel circuit coupled to a first electrode of the light emitting device; A plurality of drive control circuits, wherein the pixel circuit in the nth row of sub-pixels is coupled to the first electrode of the light-emitting device in the n+1th row of sub-pixels through at least one of the drive control circuits, and the drive control circuit is configured to transmit a first drive current generated by the pixel circuit in the nth row of sub-pixels and / or a second drive current generated according to a data voltage in the pixel circuit in the nth row of sub-pixels to the light-emitting device in the n+1th row of sub-pixels in response to a signal at a first control signal terminal; wherein n is a positive integer greater than 0.

2. The display panel according to claim 1, wherein: The drive control circuit comprises: a first switch transistor; The gate of the first switch transistor is coupled to the first control signal terminal, the first electrode of the first switch transistor is coupled to the light-emitting device in the pixel circuit in the nth row of sub-pixels, and the second electrode of the first switch transistor is coupled to the light-emitting device in the pixel circuit in the n+1th row of sub-pixels.

3. The display panel according to claim 1, wherein: The pixel circuit further includes: a first driving transistor; The drive control circuit comprises: a second drive transistor and a second switch transistor; A gate of the second driving transistor is coupled to a gate of a first driving transistor in a pixel circuit in the n-th row of sub-pixels, a first electrode of the second driving transistor is coupled to a first electrode of the first driving transistor in the pixel circuit in the n-th row of sub-pixels, and a second electrode of the second driving transistor is coupled to a first electrode of the second switch transistor; A gate electrode of the second switch transistor is coupled to the first control signal terminal, and a second electrode of the second switch transistor is coupled to the light emitting device in the sub-pixel of the (n+1)th row.

4. The display panel according to claim 1, wherein: The pixel circuit further includes: a first driving transistor; The driving control circuit comprises: a third driving transistor, a third switching transistor and a fourth switching transistor; The gate of the third driving transistor is coupled to the gate of the first driving transistor in the pixel circuit of the n-th row of sub-pixels, the first electrode of the third driving transistor is coupled to the first electrode of the first driving transistor in the pixel circuit of the n-th row of sub-pixels, and the second electrode of the third driving transistor is coupled to the first electrode of the third switch transistor; The gate of the third switch transistor is coupled to the first control signal terminal, and the second electrode of the third switch transistor is coupled to the second electrode of the first driving transistor in the pixel circuit of the nth row of sub-pixels; The gate of the fourth switch transistor is coupled to the first control signal terminal, the first electrode of the fourth switch transistor is coupled to the light-emitting device in the pixel circuit in the nth row of sub-pixels, and the second electrode of the fourth switch transistor is coupled to the light-emitting device in the n+1th row of sub-pixels.

5. The display panel according to any one of claims 1 to 4, wherein: A driving control circuit is correspondingly arranged for each sub-pixel in the first row to the N-1th row, and the sub-pixels in the nth row in the same column are coupled to the first electrodes of the light-emitting devices in the sub-pixels in the n+1th row through the corresponding driving control circuit.

6. The display panel according to claim 5, wherein: The driving control circuit is located between pixel circuits in two adjacent rows of sub-pixels.

7. The display panel according to claim 5, wherein: The driving control circuit is located between pixel circuits in two adjacent columns of sub-pixels.

8. The display panel according to claim 5, wherein: The driving control circuit is integrated into the pixel circuit of the corresponding sub-pixel.

9. The display panel according to any one of claims 1 to 4, wherein: Also includes: At least one row of virtual sub-pixels and a plurality of switch control circuits, wherein the switch control circuits are arranged in a one-to-one correspondence with the virtual sub-pixels; The virtual sub-pixel includes a virtual pixel circuit, which is coupled to the light-emitting device in the first row of sub-pixels through the corresponding switch control circuit, and the switch control circuit is configured to provide the driving current generated by the virtual pixel circuit to the light-emitting device in the first row of sub-pixels in response to the signal at the first control signal terminal.

10. A display device, wherein: Comprising a display panel as described in any one of claims 1 to 9.

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