Input / output circuit and memory circuit

Abstract

The utility model discloses an input / output circuit and a memory circuit. The input / output circuit comprises a bypass circuit, a first latch, a second latch, a first transistor and a second transistor. The bypass circuit is configured to directly receive a data signal and indirectly receive a write start signal. The first latch is coupled between the first data line and the second data line. The second latch is coupled to the first latch and is configured to generate a data output signal based on a voltage level present on the second data line. The first transistor is coupled to the first latch and is gated by an inductive start signal. The second transistor is coupled to the first latch and gated by the clock signal. The first transistor and the second transistor are alternately activated in each of a plurality of operation modes of the input / output circuit.

Description

Technical Field

[0001] This disclosure relates to an input / output circuit and a memory circuit, and more particularly to an input / output circuit and a memory circuit that provide improved layout area utilization, reduced leakage current, and reduced power consumption. Background Art

[0002] A memory circuit designed for testability (DFT) incorporates a number of components, including D flip-flop circuits, write latch circuits, read sense amplifiers, and output Q latch circuits. However, during the DFT test mode, the sense amplifier and output Q latch circuits remain idle, while in the write mode, only the sense amplifier is idle. The DFT memory circuit may further include write and shadow latch circuits, a 3-to-1 multiplexer (MUX), a passive matrix (PM) isolation (ISO) clamp circuit, and power saving logic circuits. The presence of these additional features creates significant dead zones in the memory design, thereby affecting the overall size of the circuit. Summary of the Utility Model

[0003] This disclosure provides an input / output circuit, including a bypass circuit, a first latch, a second latch, a first transistor, and a second transistor. The bypass circuit is configured to directly receive a data signal and indirectly receive a write enable signal. The first latch is coupled between a first data line and a second data line, and includes a first switch and a second switch, where the first switch is coupled between the first data line and the output of the bypass circuit, and where the second switch is coupled between the second data line and the output of the bypass circuit. The second latch is coupled to the first latch and is configured to generate a data output signal based on a voltage level present on the second data line. The first transistor is coupled to the first latch and is gated by a sense enable signal. The second transistor is coupled to the first latch and is gated by a clock signal. The first transistor and the second transistor are alternately enabled in each of a plurality of operating modes of the input / output circuit.

[0004] The present disclosure provides a memory circuit, including a memory array and an input / output circuit. The memory array includes memory cell units coupled between a first data wire and a second data wire. The input / output circuit is coupled to the memory array and includes a bypass circuit, a first latch, and a second latch. The bypass circuit is configured to receive a data signal and a write enable signal to generate a bypass data signal. The first latch is coupled to the first data wire and the second data wire and includes a first switch and a second switch, where the first switch is configured to selectively couple the bypass data signal to the first data wire, and the second switch is configured to selectively couple an inverted signal of the bypass data signal to the second data wire. The second latch is coupled to the first latch and is configured to generate a data output signal based on a voltage level present on the second data wire.

[0005] The present disclosure provides a memory circuit, including a memory array and an input / output circuit. The memory array includes memory cell units coupled between a first data wire and a second data wire. The input / output circuit is coupled to the memory array and includes a bypass circuit, a first latch, and a second latch. The bypass circuit is configured to receive a data signal and a write enable signal to generate a bypass data signal. The first latch is coupled to the first data wire and the second data wire and includes a first switch and a second switch, where the first switch is configured to selectively couple the bypass data signal to the first data wire, and the second switch is configured to selectively couple an inverted signal of the bypass data signal to the second data wire. The second latch is coupled to the first latch. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the embodiments of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of each feature may be arbitrarily increased or decreased.

[0007] Figure 1 A block diagram of a memory device in accordance with some embodiments of the present disclosure is shown;

[0008] Figure 2 A detailed schematic diagram of a memory device in accordance with some embodiments of the present disclosure is shown; Figure 1 of the memory device

[0009] Figure 3 A detailed schematic diagram of a memory device in accordance with some embodiments of the present disclosure in a read mode is shown; Figure 1 of the memory device

[0010] Figure 4 A detailed schematic diagram of a memory device in accordance with some embodiments of the present disclosure in a write mode is shown; Figure 1 of the memory device

[0011] Figure 5 illustrates the waveforms of signals in a memory device according to some embodiments of the present disclosure Figure 3 and Figure 4 in the memory device;

[0012] Figure 6 illustrates a detailed schematic diagram of a memory device in a test mode according to some embodiments of the present disclosure Figure 1 of the memory device;

[0013] Figure 7 illustrates the waveforms of signals in a memory device according to some embodiments of the present disclosure Figure 6 in the memory device;

[0014] Figure 8 illustrates a detailed schematic diagram of a memory device according to some embodiments of the present disclosure Figure 1 of the memory device;

[0015] Figure 9 illustrates a detailed schematic diagram of a memory device according to some embodiments of the present disclosure Figure 1 of the memory device; and

[0016] Figure 10 is a flowchart of an example method for operating a memory device according to some embodiments of the present disclosure Figure 1 of the memory device.

[0017]

Description of Symbols

[0018] 100: Memory device

[0019] 102: Bypass circuit

[0020] 103: Exclusive-OR (XOR) gate

[0021] 104: First latch

[0022] 106: Second latch

[0023] 108: First transistor

[0024] 109: Input circuit

[0025] 110: Second transistor

[0026] 112: First switch

[0027] 114: Second switch

[0028] 116: D-latch circuit

[0029] 118: Inverter

[0030] 120: NOR gate

[0031] 132: Data signal D

[0032] 134: Write enable signal BWEB

[0033] 136: Bypass data signal SXOR / XOR output

[0034] 138: Data wire DL / First data wire

[0035] 140: Data wire DLB / Second data wire

[0036] 142: Output signal Q

[0037] 144: Write enable signal BWE / Sense enable signal SAE

[0038] 146: Clock signal DCK

[0039] 148: Control signal / Test enable signal DFTB

[0040] 150: Memory array

[0041] 160: Input / output circuit

[0042] 210: Clock generator

[0043] 212,220: Inverter

[0044] 222: NAND gate

[0045] 224: NOR gate

[0046] 226,228: Inverter

[0047] 230,232: Transmission gate

[0048] 234: NOR gate

[0049] 236,238: Inverter

[0050] 240: NOR gate

[0051] 242: Inverter

[0052] 244: NOR gate

[0053] 250: Read gating circuit

[0054] 251: Write control circuit

[0055] 252: Latch circuit

[0056] 254: Precharge circuit

[0057] 262: Inverted bypass data signal XORB / Inverted bypass data signal

[0058] 302: Signal GLB_DCK / Global clock signal CLK

[0059] 304: Signal IWEB

[0060] 306: Signal GLB_SAE

[0061] 502: Rising clock edge

[0062] 504: Second rising clock edge

[0063] 510: Enable signal D_SAEB

[0064] 520: Precharge enable signal DLEQB

[0065] 530: Write enable signal (WEB)

[0066] 800: Memory device

[0067] 802: First switch / Transistor

[0068] 804: Second switch / Transistor

[0069] 806: P-type transistor

[0070] 810: Read gating circuit

[0071] 900: Memory device

[0072] 909: Input circuit

[0073] 1000: Example method for operating a memory device

[0074] 1002, 1004: Operations

[0075] 1006, 1008: Operations

[0076] BL: Voltage

[0077] BLB: Voltage

[0078] BWE, BWEB: Write enable signal

[0079] CLK: Global clock signal

[0080] DB: Data signal bus

[0081] DCK: Clock signal

[0082] DFTB: Test enable signal

[0083] DL, DLB: Data connection

[0084] DLEQB: Pre-charge start signal

[0085] D_C, D_T: Signals

[0086] D_SAEB: Start signal

[0087] D_SAE: Start signal

[0088] D, DS: Data signals

[0089] GLB_DCK: Signal

[0090] GLB_SAE: Signal

[0091] HIT, HITB: Control signals

[0092] IBWE, IBWBE: Outputs

[0093] N1: First NOR gate

[0094] N2: Second NOR gate

[0095] N3~N8: N-type transistors

[0096] n1~n3: Nodes

[0097] P3~P9: P-type transistors

[0098] PM, PMB: Start control signals

[0099] Q: Output signal

[0100] SAE, SAEB: Start signals

[0101] SQ: Data output signal

[0102] SXOR: Bypass data signal

[0103] T1~T5: Times

[0104] VSS, VDDM: Power supply voltage / voltage terminal

[0105] WC: Write complement

[0106] WCLK: Signal / write clock

[0107] WT: Write true value

[0108] XOR: Data signal / bypass data signal

[0109] XORB: Inverted bypass data signal / data signal bus Detailed implementation mode

[0110] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the embodiments of this disclosure. Of course, these are only examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features are not in direct contact. In addition, embodiments of this disclosure may repeat element symbols and / or letters in each example. This repetition is for purposes of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0111] In addition, for ease of description, spatially relative terms (such as "below", "beneath", "lower", "above", "upper", and the like) may be used herein to describe the relationship of one element or feature shown in the figures to another element (or elements) or feature (or features). In addition to the orientation depicted in the figures, spatially relative terms are intended to encompass different orientations of the element in use or operation. The device may be otherwise oriented (rotated 90 degrees or in other orientations) and thus the spatially relative descriptors used herein may be interpreted similarly.

[0112] A memory design may be required to have a design for testability (DFT) function. The memory design may include at least one of the following: a latch circuit, a flip-flop circuit, or a combinational logic circuit. In some methods, test patterns (e.g., binary vectors) are applied as SI inputs to the DFT circuit. This disclosure provides a DFT function for a memory device by using existing sense amplifiers and data output latch circuits (e.g., referred to as Q latches) to replace the DFT D flip-flop circuit and the write latch circuit. This disclosure can eliminate the need for circuits related to write and shadow latches in each input / output (I / O) circuit, thereby improving the use of area and reducing the additional consumption of area. This effect is achieved by eliminating the need for additional logic circuits such as write latches, shadow latches, 3-to-1 multiplexers (MUXes), passive matrix (PM) clamping circuits, and power saving logic circuits.

[0113] In some embodiments, the sense amplifier may cooperate with a data output latch circuit (e.g., a so-called Q latch) to generate test results in test mode, rather than being idle as in some methods. Accordingly, an additional shadow latch circuit for shifting test patterns in test mode is eliminated from the DFT circuit. Further, as described above, since the write latch may be idle during a read operation and the sense amplifier is precharging during a write operation, the write latches for performing the write operation generally cannot operate simultaneously. The present disclosure replaces the write latch by modifying an existing sense amplifier to reduce the area occupied by the original write latch. By this method, power consumption and leakage current can be reduced because the replacement operation does not require any additional power consumption or induce new leakage current.

[0114] Figure 1 FIG. shows a block diagram of a memory device 100 in accordance with some embodiments of the present disclosure. The memory device 100 may include an input circuit 109, a bypass circuit 102, a first latch 104, a second latch 106, a first transistor 108, and a second transistor 110. The input circuit 109 may be operatively coupled to the bypass circuit 102. The input circuit 109 may include a D latch circuit 116, an inverter 118, and a NOR gate 120. The memory device 100 may include an input / output circuit 160 and a memory array 150.

[0115] The bypass circuit 102 may include an exclusive OR (XOR) gate 103 having two input terminals. The XOR gate 103 is coupled between the output of the input circuit 109 and the first latch 104. The bypass circuit 102 can be used to directly receive the data signal D 132 and indirectly receive the write enable signal BWEB 134. In some embodiments, the bypass circuit 102 can use one of its input terminals to receive the write enable signal BWEB 134 at least via the inverter 118 and the NOR gate 120. In some embodiments, BWEB represents the bit write enable bus function, which performs the logical inversion of the write enable bit signal. The NOR gate 120 can use one of its input terminals to receive the control signal 148 (e.g., the test enable signal DFTB). When the control signal 148 is in the first logic state (e.g., "1"), the memory device 100 is set to the non-test mode, and when the control signal 148 is in the second logic state (e.g., "0"), the memory device 100 is set to the test mode. The NOR gate 120 can use its other input terminal to receive the write enable signal BWE 144. The D input of the D latch circuit 116 can be used to receive the write enable signal BWEB 134. In some embodiments, the D latch circuit 116 is a low-pass latch circuit that allows data to pass when the clock phase is low (e.g., low logic state, "0"). In various embodiments, the D latch circuit 116 is shared among the normal, shift, and capture modes and paths. The XOR gate 103 can be used to generate the bypass data signal SXOR 136 based on the data signal D 132 and the write enable signal BWEB 134. The output terminal of the bypass circuit 102 is coupled to the first latch 104 to transmit the bypass data signal SXOR 136 to the first switch 112 and the second switch 114.

[0116] The first latch 104 may be operatively coupled between a first data line 138 (e.g., a data line (DL)) and a second data line 140 (e.g., a data line bar (DLB)). The first latch 104 may include a first switch 112 and a second switch 114 operatively coupled between an output of the bypass circuit 102 and a second latch 106. The first switch 112 is operatively coupled between the first data line 138 and the output of the bypass circuit 102 (e.g., the bypass data signal SXOR 136). The second switch 114 is operatively coupled between the second data line 140 and the output of the bypass circuit 102 (e.g., the bypass data signal SXOR 136). In some embodiments, the first latch 104 may be a sense amplifier. The first latch 104 may be the master latch of the data signal D132. The first latch 104 may replace the write latch of the data signal D 132. The first latch 104 may be used to sense signals from the data line DL138 and the data line DLB 140, respectively, which signals represent data bits (1 or 0) stored in respective memory cells, and to amplify small voltage swings to identify a logic low level such that the data can be properly interpreted by the logic circuitry of the memory device 100. In some embodiments, the first latch 104 may be coupled to the memory array 150 via the first data line 138 and the second data line 140.

[0117] The second latch 106 may be operatively coupled to the first latch 104. The second latch 106 may be used to generate an output signal Q 142 based on a voltage level present on the second data line 140. In some embodiments, the second latch 106 is implemented as a high-pass latch circuit that allows data to pass when the clock phase is high (e.g., a high logic state, “1”). The first latch 104 and the second latch 106 operate together as a data flip-flop (e.g., a D flip-flop) in at least one of a plurality of operating modes (e.g., a normal mode or a test mode), in which a clock signal (e.g., the clock signal DCK 146) is deactivated and a sense enable signal (e.g., the sense enable signal SAE 144) serves as the clock source for the data flip-flop to perform a bistable toggle.

[0118] The first transistor 108 may be coupled to the first latch 104 and gated by the sense enable signal SAE 144. The second transistor 110 may be coupled to the first latch 104 and gated by the clock signal DCK 146. The first transistor 108 and the second transistor 110 may be alternately enabled in each of a plurality of operating modes (e.g., a normal mode or an operating mode) of the memory device 100 (e.g., an input / output circuit).

[0119] In some embodiments, the memory device 100 has different operating modes including a normal mode (e.g., read and write modes) and a DFT test mode (e.g., shift mode and capture mode), where the shift mode includes two sub-modes called a scan mode and a debug mode.

[0120] In the normal mode (e.g., read mode or write mode), the memory device 100 does not perform any tests; instead, the memory device 100 performs its normal functions designed to be executed, such as starting to read data from a memory (e.g., static random access memory (SRAM)) and writing data to the memory. In some embodiments, the normal path travels through an input section, a memory core logic section, and an output section. Specifically, for example, in the write mode or read mode, the normal path travels through the bypass circuit 102, the first latch 104, and the second latch 106. For example, in the non-DFT test mode, the test enable signal DFTB 148 can be set to "1", which causes the bypass circuit 102 to pass the directly received data signal D 132 through the XOR gate 103 and causes the bypass circuit 102 to output the bypass data signal SXOR 136 (data signal D132) to the first latch 104. When the memory device 100 is in the read mode, the second transistor 110, the first switch 112, and the second switch 114 are deactivated, and the first transistor 108 is activated. When the memory device 100 is in the write mode, the first transistor 108 is deactivated, and the second transistor 110, the first switch 112, and the second switch 114 are activated.

[0121] In the DFT test mode, test-related features are implemented, and specific input data (e.g., data signal D132 and write enable signal BWEB 134) are applied to the memory device 100 to perform various test functions on the memory device 100. For example, in the DFT test mode, the test enable signal DFTB 148 can be set to "0", which causes the bypass circuit 102 to generate an XOR output 136 based on the directly received signal signal D 132 and the indirectly received write enable signal BWEB 134. The memory device 100 can compare the output data (e.g., Figure 1The output signal Q 142) therein and the "designed" output data that the memory device 100 is designed to generate. If the observed output matches the "designed" output, the memory device 100 passes the test; if the observed output does not match the "designed" output, the memory device 100 fails the test. When the memory device 100 is in the test mode, the first transistor 108, the first switch 112, and the second switch 114 are activated, and the second transistor 110 is deactivated.

[0122] In the shift mode and the capture mode, which can be regarded as test modes, the tests are performed on different parts of the memory device 100. In the capture mode of the DFT test mode, the data signal D 132 is directly output to the first input terminal of the bypass circuit 102; and the write enable signal BWEB 134 is output to the second input terminal of the bypass circuit 102 via the D latch circuit 116, the inverter 118, and the NOR gate 120. The data of the data signal D 132 can be further latched in the first latch 104 and the second latch 106, and read out as the output signal Q 142. In some embodiments, the write enable signal BWEB 134 can be programmed to perform the test. In the shift mode of the DFT test mode, the data signal D 132 is directly output to the first input terminal of the bypass circuit 102; and the write enable signal BWEB 134 is output to the second input terminal of the bypass circuit 102 via the D latch circuit 116, the inverter 118, and the NOR gate 120. The first latch 104 can provide a data signal corresponding to the data signal D 132 to the second latch 106 for temporary storage of test data. In some embodiments, both the capture path and the shift path are passed through the input section and travel through the memory core logic section, and then travel to the output section. Specifically, for example, both the capture path and the shift path travel through the first latch 104 and the second latch 106 in the memory core logic section. Details of the configuration and operation will be described in the following paragraphs.

[0123] In some embodiments, the system includes a plurality of memory devices 100 coupled to each other in sequence, wherein the first memory device 100 receives a data signal (referred to as the data signal D input as Figure 1 the input data of the data signal) from an external test device, and the read data from the first memory device 100 (e.g., the signal generated by Figure 2 the inverter 212 therein) is transmitted as a data signal (input as the data signal D 132 as Figure 1 the input data of the data signal) to the subsequent memory device 100, and so on.

[0124] Figure 1The configuration is given for illustrative purposes. Various embodiments are within the scope of this disclosure. For example, in some embodiments, the D-latch circuit 116 is not included in the input circuit 102.

[0125] Figure 2 illustrates a detailed schematic diagram of a Figure 1 memory device 100 according to some embodiments of this disclosure. The memory device 100 may include an input circuit 109, a bypass circuit 102, a first latch 104, a second latch 106, a first transistor 108, and a second transistor 110. The input circuit 109 may be used to transmit signals corresponding to the data signal D 132 and the write enable signal BWEB 134 to the bypass circuit 102. The data signal D 132 is directly transmitted to the bypass circuit 102. The write enable signal BWEB 134 may be transmitted to the bypass circuit 102 via at least an inverter 118 and a NOR gate 120. The bypass circuit 102 may include an XOR gate 103, and the XOR gate 103 is used to generate a bypass data signal SXOR136 (e.g., signal D or signal XOR) according to the data signal D and the write enable signal BWEB.

[0126] In the input circuit 109, additional logic circuits such as the inverter 118 and the NOR gate 120 may be used to eliminate the need for incoming data latches and shadow latch related circuits. One of the inputs of the NOR gate 120 may be used to receive the test enable signal DFTB 148. Due to the additional logic circuits, two test modes (e.g., non-DFT test mode and DFT test mode) may be defined. In the non-DFT test mode, the first latch 104 may act as a write latch. In the DFT test mode, the first latch 104 and the second latch 106 operate together as data flip-flops (e.g., D flip-flops).

[0127] In the non-DFT test mode, the test start signal DFTB 148 can be at “1”, which can cause the NOR gate 120 to output “0”. The XOR gate 103 can receive the data signal D 132 and the output “0” of the NOR gate 120. In this situation, the XOR gate 103 can generate a bypass data signal SXOR 136 (data signal D 132), and can transmit the bypass data signal SXOR 136 (data signal D 132) to the first latch 104. The inverter 118 of the first latch 104 can generate an inverted bypass data signal 262 according to the bypass data signal SXOR 136 (data signal D 132). The first latch 104 can use the data signal D132 and the inverted bypass data signal 262 as outputs to operate as a write latch. In the non-DFT test mode, the first latch 104 can act as a write latch. In some embodiments, the first latch 104 can be a sense amplifier.

[0128] In the DFT test mode, the test start signal DFTB 148 can be at “0”, which can cause the NOR gate 120 to output a write start signal BWEB 134. The XOR gate 103 can receive the data signal D 132 and the write start signal BWEB134. In this situation, the XOR gate 103 can generate a bypass data signal SXOR 136 (data signal XOR) according to the data signal D 132 and the write start signal BWEB 134. The XOR gate 103 can transmit the bypass data signal SXOR 136 (data signal XOR) to the first latch 104. The inverter 118 of the first latch 104 can generate an inverted bypass data signal XORB 262 according to the bypass data signal SXOR 136 (data signal XOR). The first latch 104 can use the bypass data signal SXOR 136 (data signal XOR) and the inverted bypass data signal XORB 262 as inputs to operate as a DFT D flip-flop. In the DFT test mode, the first latch 104 and the second latch 106 jointly operate as a data flip-flop (e.g., D flip-flop), where the clock signal (e.g., clock signal DCK 146) is deactivated and the sense start signal (e.g., sense start signal SAE 144) is used as the clock source of the data flip-flop for bistable toggling.

[0129] The D input of the D-latch circuit 116 can be used to receive the write enable signal BWEB 134. In some embodiments, the D-latch circuit 116 is a low-pass latch circuit that allows data to pass when the clock (e.g., the write enable signal BWEB 134) is in the low phase (e.g., low logic state, "0"). The low-pass latch circuit can be triggered by a short low signal in the input signal, which allows low-frequency or slowly changing signals to pass while blocking high-frequency signals. In some embodiments, the D-latch circuit 116 can be a BWEB input latch that changes the state of the latch according to the input write enable signal BWEB134. The D-latch circuit 116 can be controlled by the write enable signal BWEB 134.

[0130] In some embodiments, the first latch 104 can include a read gating circuit 250, a latch circuit 252, a precharge circuit 254, and an inverter 220 having a terminal coupled to the bypass circuit 102. The read gating circuit 250 can transmit the bypass data signal SXOR 136 and the inverted bypass data signal 262 to the data line DL 138 and the data line DLB 140, respectively, in response to the enable signals D_SAE and D_SAEB. For ease of illustration, the read gating circuit 250 is coupled between the data line DL 138, the data line DLB 140, the bypass circuit 102, and the inverter 220 of the first latch 104. The read gating circuit 250 can include a first switch 112 and a second switch 114. The first switch 112 can include a transmission gate that, in response to the enable signals D_SAE and D_SAEB, couples to the data line DL 138 in the bypass circuit 102, the terminal of the inverter 220, and the output of the XOR gate 103, and is used to transmit the bypass data signal SXOR 136 from the XOR gate 103 to the data line DL 138. The second switch 114 can include a transmission gate coupled to the other terminal of the inverter 220 and the data line DLD 140. The second switch 114 can be used to transmit the inverted bypass data signal 262 (e.g., the DB or XORB signal) from the inverter 220 to the data line DLB 140 in response to the enable signals D_SAE and D_SAEB. Each of the switches 112-114 (e.g., the transmission gate) can include a P-type transistor and an N-type transistor, as Figure 2 shown in.

[0131] The latch circuit 252 may have terminals coupled to the data line DL 138 and the data line DLB 140. When signaled (e.g., read mode or DFT test mode), the latch circuit 252 may transfer an input state to an output state by the data line DL 138 and the data line DLB 140, and the output remains insensitive to changes in the input state thereafter until signaled again. In other words, the first switch 112 is coupled between the bypass circuit 102 and one of the terminals of the latch circuit 252, and the second switch 114 is coupled between the inverter 220 and the other terminal of the latch circuit 252. For ease of explanation, the latch circuit 252 may include P-type transistors P1 to P2 coupled to a voltage terminal (e.g., providing a power supply voltage VDDM and hereinafter labeled VDDM), and N-type transistors N1 to N2 coupled to the first transistor 108 and the second transistor 110. The first transistor 108 and the second transistor 110 may be N-type transistors N3 to N4. The first transistor 108 may be coupled to the power supply voltage VSS (e.g., providing a ground potential and hereinafter labeled VSS) and is operative in response to the sense activation signal SAE144, which is referred to as a periodic signal, to activate the first latch 104 (e.g., sense amplifier) for a particular mode (e.g., read mode or DFT test mode). The first transistor 108 may be gated by the sense activation signal SAE 144. The second transistor 110 may be coupled to the power supply voltage VSS (e.g., providing a ground potential) and is operative in response to the clock signal DCK 146, which is referred to as a periodic signal, to activate the first latch 104 (e.g., sense amplifier) for a particular mode (e.g., write mode). The second transistor 110 may be gated by the clock signal DCK146. Transistors N1 and P1 form an inverter, and this inverter is cross-coupled with the inverter formed by transistors N2 and P2.

[0132] The precharge circuit 254 is coupled to the data line DL 138 and the data line DLB 140. In some embodiments, during the test mode, when the activation signal SAE has a low logic state, the precharge circuit 254 is operative to turn off in response to the precharge activation signal DLEQB having a high logic state. In some embodiments, the precharge circuit 254 may include P-type transistors P3 to P5 having a control terminal receiving the precharge activation signal DLEQB. Specifically, the transistor P3 is coupled between the data line DL138 and the voltage terminal VDDM, and the transistor P4 is coupled between the data line DLB 140 and the voltage terminal VDDM. The transistor P5 is coupled between the data line DL 138 and the data line DLB 140.

[0133] The second latch 106 (e.g., an output latch circuit) may include P-type transistors P6 to P9, N-type transistors N5 to N8, and a NAND gate 222. When signaled, the second latch 106 may transfer the output state from the self-latch circuit 252 to the inverter 212 (e.g., read mode or DFT test mode), and the second latch 106 may even maintain the output state (e.g., the output state from the latch circuit 252) after removing the input. In Figure 2 an embodiment, the second latch 106 may further include an inverter 212. In some embodiments, the transistor P6 is coupled between the voltage terminal VDDM and the transistor P7. The transistor P7 is coupled to the transistors N5, N7, P9, the input terminal of the inverter 212, and the first input terminal of the NAND gate 222 at the node n1. The transistor N6 is coupled between the voltage terminal VSS and the transistor N5. The transistor P8 is coupled between the voltage terminal VDDM and the transistor P9. The transistor N8 is coupled between the voltage terminal VSS and the transistor N7. The transistors N6 and P8 have control terminals coupled to the data wire DLB 140 and are operative to respond to a data signal DS generated by the first latch 104. The transistors P7 and N7 are operative to switch in response to an enable signal SAEB. The transistors P9 and N5 are operative to switch in response to an enable signal SAE, while the control terminal of the transistor N5 is coupled to the control terminal of the transistor N3. The control terminals of the transistors P8 and N8 are coupled to the output terminal of the NAND gate 222. The NAND gate 222 may receive an enable control signal PMB (having a logic state different from the enable control signal PM). In some embodiments, the memory device 100 further includes a write control circuit 251, which is coupled to the latch circuit 252 to operate in different operation modes.

[0134] The write control circuit 251 can capture data from a temporary storage source (e.g., the latch circuit 252 or the second latch 106) via complementary DLB inputs and DL inputs. The latch circuit 252 can provide signals via the complementary DLB inputs and DL inputs. These signals can control rows of transistors, thereby affecting voltages BL and BLB, which are converted into binary signals for the write control unit 251. In this configuration, during a clock cycle for writing to a memory cell, the write latch holds the DL data. During a read operation (e.g., write clock (WCLK) = 1 (non-write mode)), the write latch is largely inactive. The write control circuit 251 can include a first NOR gate N1, a second NOR gate N2, a write truth (WT) transistor, and a write complement (WC) transistor. The first NOR gate N1 can receive the write clock and the DLB input and thereby generate a WC drive signal via a NOR operation. The second NOR gate N2 can also use the write clock but pairs the write clock with the DL input to thereby generate a WT drive signal. These signals activate the WC transistor and the WT transistor, respectively, to write to voltages BL and BLB, which are complementary signals. This configuration facilitates a write operation based on the input, thereby enabling data to be stored in the corresponding location.

[0135] The memory device 100 further includes a clock generator 210, which includes inverters 236, 238, 242 and NOR gates 240, 244. The NOR gate 240 is coupled between the inverter 238 and the inverter 242 (or NOR gate 244). Specifically, the inverter 236 is used to invert the signal GLB_SAE 306 to generate the enable signal SAEB. The inverter 238 is used to invert the enable signal SAEB to generate the enable signal SAE. The NOR gate 240 is used to generate the enable signal D_SAEB based on the enable signal SAE and the signal GLB_DCK 302. In some embodiments, the signal GLB_DCK 302 has a low logic state ("0") during the test mode and a high logic state ("1") in other operating modes (e.g., read mode). The inverter 242 is used to generate the enable signal D_SAE based on the enable signal D_SAEB. In the test mode, the enable signal D_SAEB is referred to as a delayed signal associated with the enable signal SAEB, and the enable signal D_SAE is referred to as a delayed signal associated with the enable signal SAE. In some embodiments, the NOR gate 240 is used to generate the enable signal D_SAEB based on the enable signal SAE and the signal GLB_DCK 302. The NOR gate 244 is used to generate the clock signal DCK based on the enable signal D_SAEB and the signal IWEB 304. The clock generator 210 can be an electronic circuit that generates a regular and repetitive electrical signal referred to as a clock signal (e.g., D_SAE signal, DCK signal). This signal can be used to synchronize the operation of digital elements in various devices (e.g., the latch circuit 252 or the second latch 106). The clock generator 210 ensures that different parts of the system operate together in a coordinated manner.

[0136] The memory device 100 may further include a NOR gate 224 and inverters 226, 228. The NOR gate 224 may have a first input coupled to the second latch 106 at node n2 and a second input receiving the test enable signal DFTB. In some embodiments, the latch circuit 252 and the second latch 106 (e.g., the output latch circuit) are referred to as read path D flip-flops. Thus, for scan-based testing during the shift mode of the test mode, the data output signal generated by the second latch 106 is transmitted via the NOR gate 224 and the inverters 226, 228 as an input signal (e.g., data signal D 132) in the subsequent memory device 100.

[0137] The memory device 100 may further include transmission gates 230 and 232, which are used to operate in response to control signals HIT and HITB having different logic states. In some embodiments, the transmission gate 230 is coupled to the second latch 106 at node n2, and is coupled to an output driver circuit including a NOR gate 234 at node n3. The NOR gate 234 has a first input terminal receiving a signal from the transmission gate 230 and a second input terminal receiving a start control signal PM, and is used to generate an output signal Q 142.

[0138] Figure 2 The configuration is given for illustrative purposes. Various implementations are within the intended scope of the present disclosure. Figure 2 The operation of circuit 100 is substantially similar to Figure 1 Operation of the circuit 100. Figure 1 and Figure 2 The detailed operation configuration of the memory device 100 will be referred to in Figures 3 to 7 Explain in the following paragraphs. Figure 5 Some embodiments of the present disclosure are shown in FIG. Figures 1 to 4 The waveform of the signal in the memory device 100. Figure 7 Some embodiments of the present disclosure are shown in FIG. Figure 1 , Figure 2 and Figure 6 The waveform of the signal of the memory device 100.

[0139] Figure 3 FIG. 1 shows a diagram of a display in a read mode according to some embodiments of the present disclosure. Figure 1 and Figure 2 Detailed schematic diagram of memory device 100 in FIG. 1 . In read mode, test enable signal DFTB 148 may be set to “1”, which may cause NOR gate 120 to output “0”. XOR gate 103 may receive data signal D 132 and output “0” of NOR gate 120. In this case, XOR gate 103 may generate bypass data signal SXOR 136 (data signal D 132), and may transmit bypass data signal SXOR 136 (data signal D 132) to first latch 104. When memory device 100 is in read mode, second transistor 110 (e.g., sense amplifier pull-down transistor N4), first switch 112, and second switch 114 are disabled, and first transistor 108 is enabled.

[0140] In the read mode, the signals GLB_DCK 302, signal IWEB 304, and test start signal DFTB 148 are set to the logic high state (“1”), while the signal GLB_SAE 306 can be bistable and thus simulate the normal operation mode. In the read mode, the first latch 104, which serves as a sense amplifier, is triggered at an accurate timing as in a normal read operation. The D latch circuit 116 (BWEB latch) can be latched during the read operation. The data wire pair (the first data wire 138 and the second data wire 140) is precharged in response to the precharge start signal DLEQB. Specifically, the voltage BL is enabled, and then the read-column-select is initiated to transfer data to the first data wire 138 (e.g., data wire DL).

[0141] Figure 4 Illustrated is a detailed schematic diagram of the memory device 100 in the write mode according to some embodiments of the present disclosure. Figure 1 and Figure 2 In the write mode, the test start signal DFTB 148 can be set to “1”, which can cause the NOR gate 120 to output “0”. The XOR gate 103 can receive the data signal D 132 and the output “0” of the NOR gate 120. In this situation, the XOR gate 103 can generate the bypass data signal SXOR 136 (data signal D 132) and can transmit the bypass data signal SXOR 136 (data signal D 132) to the first latch 104. When the memory device 100 is in the write mode, the first transistor 108 is deactivated, and the second transistor 110, the first switch 112, and the second switch 114 are activated. The first switch 112 and the second switch 114, which are gated by the activation signal D_SAE and / or the activation signal D_SAEB respectively, can transfer the data signal D and the data signal bus DB to the first latch (sense amplifier) 104.

[0142] In the write mode, the signals GLB_SAE 306 and IWEB 304 are set to the low logic state ("0"), while the test start signal DFTB 148 is set to the high logic state ("1"). The signal GLB_DCK 302 can be bistable, thereby simulating a normal write operation. In the write mode, the sense start signal SAE 144 is set to 0, and the start signal SAEB is set to 1. The second latch 106 (e.g., a Q latch) can hold / latch the readout data from the previous read cycle, thereby ensuring its preservation. The precharge circuit 254 (e.g., a DL precharger) is turned off in response to the precharge start signal DLEQB being set to "1". The first latch 104 (sense amplifier) can act as an incoming data latch during the write operation.

[0143] The output (IBWE) of the D-latch circuit 116 (e.g., a BWEB latch) and the data lines DL 138 / data line DLB 140 can form a write circuit, which is gated by a write clock to control the writing of data to the BL pair of the write control circuit 251.

[0144] Figure 5 illustrates the waveforms of the signals in the memory device 100 according to some embodiments of the present disclosure. Figure 3 and Figure 4 The operating principle of the memory circuit 100 can be explained by using a timing diagram as illustrated in Figure 5 . Generally, a cycle can include a read operation and a subsequent write operation, and the transistors (e.g., transistors P1, P2, N1, N3) of the latch circuit 252 are first precharged before each read operation.

[0145] At time T1, when the sense start signal SAE 144 has a low logic state, the precharge circuit 254 precharges the data signal DL 138 and the data signal DLB 140 in response to the precharge start signal DLEQB 520 having a high logic state. After the precharge period, a signal (e.g., the sense start signal SAE 144 or the clock signal DCK 146) can turn on the transistors 108, 110, since the transistors 108, 110 may take time to recharge. During the phase when the Din latch is disabled, the start signal D_SAEB 510 is set to low. During the rising clock edge 502, the voltage level of the write enable signal (WEB) 530 triggers the start of a read operation or a write operation. In Figure 5In the example, at the first rising clock edge 502, WEB 530 is set high to trigger a read operation. During the read operation, the transistors of the first latch 104 (sense amplifier circuit) are activated.

[0146] At time T2, the precharge start signal DLEQB 520 is set low after the precharge ends. During the read operation, the clock signal DCK 146 and the start signal D_SAEB 510 can remain low. The sense start signal SAE 144 can temporarily rise to activate the sensing function of the first latch 104 (sense amplifier circuit). After performing the sensing function, the sense start signal SAE 144 can fall and remain low during the write operation. The clock signal DCK 146 is low during the read operation, and the sense start signal SAE 144 is also set low at the start of the read cycle. During the rising clock edge 502, the voltage level of the write enable signal (WEB) 530 triggers the start of the read operation. At the end of the read operation, the sense start signal SAE 144 is then temporarily set high to perform the sensing of differential signals (e.g., data signals DL, DLB) in order to sense binary values. As the sense start signal SAE 144 falls to a low voltage, the start signal D_SAEB 510 is set high while the Din latch is in the transparent phase. After the read operation ends, the write operation can begin. At the second rising clock edge 504, WEB 530 is set low to trigger a write operation. During the write operation, the transistors of the first latch 104 (sense amplifier circuit) are always deactivated.

[0147] At time T3, before the data is latched during the write operation, the Din signal can persist for a period when the Din latch is considered transparent and the start signal D_SAEB 510 is set high. More specifically, the precharge start signal DLEQB 520 is first set high to turn on the voltage precharge circuit 254 (e.g., transistors P3, P4, P5) to equalize and precharge the first latch 104 (sense amplifier circuit). The start signal D_SAEB 510 is set high during the phase when the Din latch is transparent. During the period from the end of the read operation to the start of the write operation, the precharge start signal DLEQB 520 can become high voltage to turn on the voltage precharge circuit 254 throughout the write operation and precharge the first latch 104 (sense amplifier circuit). The precharge start signal DLEQB 520 remains high until the start of the next cycle, and the sense start signal SAE 144 also remains low throughout the write operation because during the write operation, the first latch 104 (sense amplifier circuit) may not be needed except to latch the data received via the Din latch and the DinB latch. To latch the data received from the Din latch and the DinB latch, the clock signal DCK 146 can be temporarily set high to perform the sensing of differential signals (e.g., data signals DL, DLB) to sense the binary value and latch the binary value stored in the latch circuit 252.

[0148] At time T4, while the Din signal is being latched, the clock signal DCK 146 is set high. At the start of the write operation, the start signal D_SAEB 510 is set high while the Din latch is in the transparent phase. When latching the data received from the Din latch and the DinB latch, the start signal D_SAEB 510 can go low because the relationship between the start signal D_SAEB 510 and the clock signal DCK 146 is complementary during the write operation. After the write operation ends, another cycle of the read operation following the write operation can start.

[0149] Figure 6 Illustrated is a detailed schematic diagram of the memory device 100 in write mode according to some embodiments of the present disclosure Figure 1 and Figure 2 of.

[0150] In the DFT test mode, the test start signal DFTB 148 can be set to “0”, which can cause the NOR gate 120 to output the write start signal BWEB 134. The XOR gate 103 can receive the data signal D 132 and the write start signal BWEB 134. In this condition, the XOR gate 103 can generate a bypass data signal SXOR 136 (data signal XOR), and can transmit the bypass data signal SXOR 136 (data signal XOR) to the first latch 104. When the memory device 100 is in the DFT test mode, the first transistor 108, the first switch 112, and the second switch 114 are activated, and the second transistor 110 (e.g., sense amplifier pull-down transistor N4) is deactivated. The first switch 112 and the second switch 114, which are gated by the start signal D_SAE and / or the start signal D_SAEB respectively, can transmit the data signal XOR and the data signal bus XORB to the first latch 104 (sense amplifier).

[0151] In the DFT test mode, the signals GLB_DCK 302 and the test start signal DFTB 148 are set to the low logic state (“0”), while the signal IWEB 304 is set to the high logic state (“1”). The signal GLB_SAE 306 can be used as the single clock source of the DFT D flip-flop for bistable toggling. The precharge start signal DLEQB is set to 1, thereby deactivating the precharger of the data wiring. Although the D latch circuit 116 (e.g., BWEB latch) can perform bistable toggling, the write operation is deactivated. The first latch 104 (sense amplifier) can act as the master latch during the DFT operation. The second latch 106 can act as the shadow latch in the DFT D flip-flop. The first latch 104 and the second latch 106 operate together as data flip-flops (e.g., D flip-flops) in the DFT test mode. During the DFT test mode, it may not be necessary to hold the previously read data.

[0152] Figure 7 Illustrated are Figure 6 the waveforms of the signals of the memory device 100 in Figure 7 accordance with some embodiments of the present disclosure. The principle of the DFT test operation of the memory circuit 100 can be explained by using the timing diagram illustrated in

[0153] At time T1, as the global clock signal CLK 302 of the memory device 100 rises, in response to the sense activation signal SAE 144 rising to a high logic state and the test activation signal DFTB 148 having a low logic state, the NOR gate 120 generates an activation signal D_SAEB 510 having a low logic value. The inverter 242 can invert the activation signal D_SAEB 510 to generate an activation signal D_SAE 144 having a high logic state.

[0154] During the time period from T1 to T2, the data signal D 132 is input and rises to have a high logic state. The XOR gate 103 generates and transmits a bypass data signal XOR 136 having a high logic state at time T2 to the first latch 104 (sense amplifier).

[0155] At time T3, in the test mode, when the second latch 106 (e.g., referred to as a high-pass latch circuit) has a low logic state in response to the sense activation signal SAE 144 and the activation signal SAEB 510 has a high logic state, the read gating circuit 250 turns on in response to the activation signal D_SAEB 510 having a logic high state and the activation signal D_SAE 144 having a low logic state to transmit the bypass data signal XOR 136 to the latch circuit 252. Specifically, the bypass data signal XOR 136 having a logic high state is transmitted to the data wire DL 138 via the transmission gate 112, and the bypass data signal XORB 262 having a low logic state is transmitted to the data wire DLB 140 via the transmission gate 114. Thus, during the test mode, in response to the sense activation signal SAE 144 having a low logic state and the activation signal D_SAEB 510 having a high logic state, the first latch 104 adjusts the voltage levels of the data wires DL 138 and DLB 140 according to the bypass data signal XOR 136 corresponding to the data signal D 132.

[0156] At time T4, the second latch 106 with a high-pass output turns on in response to the sense activation signal SAE 144 rising to a high logic state and the activation signal SAEB 510 having a low logic state. Specifically, the transistor P6 turns on in response to the data wire DLB 140 having a low voltage level corresponding to the bypass data signal XORB 262, and in response to the activation signal SAEB 510, supplies the supply voltage VDDM to the node n1 via the turned-on transistor P7. Thus, the second latch 106 generates a data output signal SQ by the inverter 212 therein, where the data output signal SQ has a low logic state.

[0157] At time T5, transmission gate 230 transmits data output signal SQ to NOR gate 234 in response to control signal HIT having a high logic state and control signal HITB having a low logic state. NOR gate 234 generates output signal Q 142 having a high logic state in response to start control signal PM having a low logic state and data output signal SQ having a low logic state. Thus, output signal Q 142 and data signal D 132 have the same logic state. In other words, the data of data signal D 132 is latched by first latch 104 and second latch 106 and transmitted to output signal Q 142 in the test mode.

[0158] Under the configuration of the present disclosure, first latch (sense amplifier) 104 that reads data from a memory cell in a read mode and second latch (Q latch circuit 106) that temporarily latches the read data for further operations are used to scan, capture, or hit test data in a test mode, which achieves area and power savings because there is no need to provide additional D flip-flop circuits, shadow latches, and / or other related logic circuits. In addition, for the above reasons, the leakage current in the memory device is improved by reducing the number of circuits and logic gates.

[0159] Figure 8 illustrates a detailed schematic diagram of Figure 1 memory device 100 according to some embodiments of the present disclosure. Memory device 800 may include input circuit 109, bypass circuit 102, first latch 104, second latch 106, first transistor 108, and second transistor 110. Figure 8 memory device 800 is substantially similar to Figure 1 and Figure 2 memory device 100, except that first switch 802 and second switch 804 are both replaced by N-type transistors. For the sake of brevity, the specific operations of similar components that have been described in detail in the previous paragraphs are omitted, unless it is necessary to introduce the common operation relationship with the components illustrated in Figure 8 FIG.

[0160] Compared with Figure 2 Figure 8 ​The read gating circuit 810 therein includes a plurality of N-type transistors instead of having transmission gates 112 and 114 for transmitting bypass data signals SXOR and SXORB. For ease of illustration, transistor 802 is coupled to data wire DL 138 and is configured to turn on in response to an enable signal D_SAEB to transmit the bypass data signal SXOR to data wire DL138. Transistor 804 is coupled to data wire DLB 140 and is configured to turn on in response to an enable signal D_SAEB to transmit the bypass data signal SXORB to data wire DLB 140. The read gating circuit 810 is coupled between data wire DL 138, data wire DLB 140, bypass circuit 102, and inverter 220 of the first latch 104.

[0161] In addition, the first latch 104 includes a P-type transistor 806 coupled between a precharge circuit 254 and a latch circuit 252. Specifically, transistor 806 has a first terminal coupled between transistors P3 and P4 at a voltage terminal VDDM and a second terminal coupled between transistors P1 and P2.

[0162] During test mode operation, transistor 806 is turned off to prevent data wires DL 138 and DLB140 from being affected by other signals in the memory device 100. In other words, the voltage levels of data wires DL 138 and DLB 140 are modulated only based on the bypass data signals SXOR and SXORB.

[0163] Figure 9 Illustrated is a detailed schematic diagram of a Figure 1 memory device 100 according to some embodiments of the present disclosure. The memory device 900 may include an input circuit 909, a bypass circuit 102, a first latch 104, a second latch 106, a first transistor 108, and a second transistor 110. Figure 9 The memory device 900 of Figure 1 and Figure 2 is substantially similar to the memory device 100 of Figure 9 except for the input circuit 909. For the sake of brevity, the specific operations of similar components that have been described in detail in the previous paragraphs are omitted unless it is necessary to introduce the co - operating relationships with the components illustrated in

[0164] In the memory device 900, the bypass circuit 102 may be configured to directly receive a write enable signal BWEB 134 and indirectly receive a data signal D 132. Figure 9 The operation of the memory device 900 of Figure 1 and Figure 2Operation of the memory device 100. The input circuit 909 can be used to eliminate the need for circuits related to the BWEB latch and the shadow latch. In the DFT test mode, the first latch 104 and the second latch 106 jointly operate as a data flip-flop (e.g., D flip-flop), where the clock signal (e.g., clock signal DCK 146) is deactivated and the sense activation signal (e.g., sense activation signal SAE 144) serves as the clock source of the data flip-flop for bistable toggling.

[0165] Figure 10 For operating according to some embodiments of the present disclosure Figure 1 and Figure 2 Flowchart of an example method 1000 for operating the memory device 100 in. The method 1000 can be used to operate the memory device 100. For example, for the memory device 100, at least a part of the operations described in the method 1000 can be performed during the test mode. It should be noted that the method 1000 is only an example and is not intended to limit the present disclosure. Therefore, it should be understood that additional operations can be provided before, during, and after Figure 10 the method 1000, and other operations may only be briefly described herein.

[0166] The method 1000 starts with operation 1002, in which the memory circuit 100 can directly receive the data signal 132 and indirectly receive the write enable signal 134 to generate a bypass data signal 136. For example, in Figure 2 , the bypass circuit 102 can directly receive the data signal D 132 and indirectly receive the write enable signal BWEB 134. The bypass circuit 102 can generate an XOR output 136 according to the directly received data signal D 132 and the indirectly received write enable signal BWEB 134.

[0167] The method 1000 then proceeds to operation 1004, in which the memory circuit 100 can transfer the bypass data signal 136 to the first latch (master latch) 104. The first latch 104 is coupled to the memory bit cell via the first data wire 138 and the second data wire 140. Continuing Figure 2 with the foregoing example in, the XOR gate 103 can transfer the bypass data signal SXOR136 to the first latch 104.

[0168] Method 1000 then proceeds to operation 1006, in which memory circuit 100 may transfer the logically inverted signal of bypass data signal 262 to the first latch (master latch) 104. The master latch 104 includes a sense amplifier coupled to a first transistor 108 and a second transistor 110. The first transistor 108 is gated by a sense enable signal 144, and the second transistor 110 is gated by a clock signal 146. Continuing Figure 2 from the foregoing example, the inverter 118 of the first latch 104 may generate an inverted bypass data signal XORB 262 based on the bypass data signal SXOR 136 (data signal XOR). The second switch 114 may transfer the inverted bypass data signal XORB 262 from the inverter 220 to the data line DLB 140. The first transistor 108 may be coupled to the first latch 104 and gated by the sense enable signal SAE 144. The second transistor 110 may be coupled to the first latch 104 and gated by the clock signal DCK 146.

[0169] Method 1000 then proceeds to operation 1008, in which memory circuit 100 may generate an output signal Q 142 based on the voltage level present on the second data line 140 and from the second latch (shadow latch) 106. The shadow latch 106 includes a Q latch. The master latch 104 and the shadow latch 106 together and operably serve as a data flip-flop. Operations 1002 to 1008 are performed during a test mode for the memory circuit 100. Continuing Figure 2 from the foregoing example, the second latch 106 may be used to generate the output signal Q 142 based on the voltage level present on the second data line 140. The first latch 104 may utilize the bypass data signal SXOR 136 (data signal XOR) and the inverted bypass data signal XORB 262 as inputs to operate as a DFT D flip-flop.

[0170] This disclosure document relates to removing components from a circuit, such as write latches, shadow latches, 3-to-1 multiplexers, PMISO clamping circuits, and power-saving logic. The removal of the components brings a significant improvement in the utilization of the layout area within each IO. Additionally, eliminating the extra devices, transistors for write and shadow latches, and their associated logic schemes helps significantly reduce leakage current. The absence of these extra circuits minimizes power consumption because there is no extra signal bi-state toggling activity. Even when these components are removed, the functions of read, write, and DFT operations can still continue to function effectively. The Q latch can hold the last read data even during the write mode, thus ensuring that the performance is not affected. The memory design provides good results for problems related to DFT. Additionally, it can be expected that the layout will benefit from the improved IO area saving ratio in the implementation. This method provides improved layout area utilization, reduced leakage current, lower power consumption, and maintains the inherent operating functions without reducing performance.

[0171] This disclosure document provides an input / output circuit, including a bypass circuit, a first latch, a second latch, a first transistor, and a second transistor. The bypass circuit is used to directly receive a data signal and indirectly receive a write enable signal. The first latch is coupled between a first data wire and a second data wire, and includes a first switch and a second switch, where the first switch is coupled between the first data wire and the output of the bypass circuit, and where the second switch is coupled between the second data wire and the output of the bypass circuit. The second latch is coupled to the first latch and is used to generate a data output signal based on the voltage level present on the second data wire. The first transistor is coupled to the first latch and is gated by a sense enable signal. The second transistor is coupled to the first latch and is gated by a clock signal. The first transistor and the second transistor are alternately enabled in each of multiple operating modes of the input / output circuit.

[0172] In some embodiments of the input / output circuit, in at least one of the multiple operating modes, the first latch and the second latch operate together as a data flip-flop, the clock signal is deactivated, and the sense enable signal toggles as the clock source of the data flip-flop.

[0173] In some embodiments of the input / output circuit, the bypass circuit includes an exclusive-OR (XOR) gate, and one of the multiple inputs of the XOR gate is used to receive the write enable signal at least via an inverter and a NOR gate.

[0174] In some embodiments of the input / output circuit, a NOR gate causes one of a plurality of inputs of the NOR gate to receive a control signal, and wherein when the control signal is in a first logic state, the input / output circuit is set to a non-test mode, and when the control signal is in a second logic state, the input / output circuit is set to a test mode.

[0175] In some embodiments of the input / output circuit, the first switch and the second switch each include a transmission gate.

[0176] In some embodiments of the input / output circuit, the first switch and the second switch each include a transistor.

[0177] In some embodiments of the input / output circuit, when the input / output circuit is in a read mode, the second transistor, the first switch, and the second switch are deactivated, and the first transistor is activated.

[0178] In some embodiments of the input / output circuit, when the input / output circuit is in a write mode, the first transistor is deactivated, and the second transistor, the first switch, and the second switch are activated.

[0179] In some embodiments of the input / output circuit, when the input / output circuit is in a test mode, the first transistor, the first switch, and the second switch are activated, and the second transistor is deactivated.

[0180] In some embodiments of the input / output circuit, the first latch is coupled to the memory array via a first data wire and a second data wire.

[0181] The present disclosure provides a memory circuit including a memory array and an input / output circuit. The memory array includes memory bit cells coupled between a first data wire and a second data wire. The input / output circuit is coupled to the memory array and includes a bypass circuit, a first latch, and a second latch. The bypass circuit is configured to receive a data signal and a write enable signal to generate a bypass data signal. The first latch is coupled to the first data wire and the second data wire and includes a first switch and a second switch, wherein the first switch is configured to selectively couple the bypass data signal to the first data wire, and the second switch is configured to selectively couple an inverted signal of the bypass data signal to the second data wire. The second latch is coupled to the first latch and is configured to generate a data output signal based on a voltage level present on the second data wire.

[0182] In some embodiments of the memory circuit, the input / output circuit further includes a first transistor and a second transistor. The first transistor is coupled to a first latch and is gated by a sense enable signal. The second transistor is coupled to the first latch and is gated by a clock signal. The first transistor and the second transistor are alternately enabled in each of a plurality of operating modes of the input / output circuit.

[0183] In some embodiments of the memory circuit, when the input / output circuit is set to be in a design for testability mode of the memory array, the first latch and the second latch jointly operate as a data flip-flop, wherein the clock signal is deactivated and the sense enable signal serves as a clock source of the data flip-flop for bistable toggling.

[0184] In some embodiments of the memory circuit, the first switch and the second switch each include a transmission gate.

[0185] In some embodiments of the memory circuit, the first switch and the second switch each include a transistor.

[0186] In some embodiments of the memory circuit, the bypass circuit includes an exclusive-OR gate that enables one of a plurality of inputs of the exclusive-OR gate to receive a write enable signal at least via an inverter and a NOR gate.

[0187] In some embodiments of the memory circuit, the NOR gate enables one of a plurality of inputs of the NOR gate to receive a control signal, and wherein when the control signal is in a first logic state, the input / output circuit is set to a non-test mode, and when the control signal is in a second logic state, the input / output circuit is set to a test mode.

[0188] The present disclosure provides a method of operating a memory circuit, including the steps of: directly receiving a data signal and indirectly receiving a write enable signal to generate a bypass data signal; transmitting the bypass data signal to a master latch, wherein the first latch is coupled to a memory bit cell via a first data connection and a second data connection; transmitting a logical inverse signal of the bypass data signal to the master latch; and generating a data output signal from a shadow latch based on a voltage level present on the second data connection.

[0189] In some embodiments of the method of operating the memory circuit, the following steps are performed in a test mode of the memory circuit: directly receiving a data signal and indirectly receiving a write enable signal to generate a bypass data signal; transmitting the bypass data signal to the master latch; transmitting a logical inverse signal of the bypass data signal to the master latch; and generating a data output signal from a shadow latch based on a voltage level present on the second data connection.

[0190] In some embodiments of a method of operating a memory circuit, a master latch includes a sense amplifier coupled to a first transistor and a second transistor, and a shadow latch includes a Q latch, the first transistor being gated by a sense enable signal and the second transistor being gated by a clock signal, and wherein the master latch and the shadow latch are used together as a data flip-flop.

[0191] The present disclosure also provides another memory circuit, including a memory array and an input / output circuit. The memory array includes memory cell units coupled between a first data line and a second data line. The input / output circuit is coupled to the memory array and includes a bypass circuit, a first latch, and a second latch. The bypass circuit is configured to receive a data signal and a write enable signal to generate a bypass data signal. The first latch is coupled to the first data line and the second data line and includes a first switch and a second switch, wherein the first switch is configured to selectively couple the bypass data signal to the first data line, and the second switch is configured to selectively couple an inverted signal of the bypass data signal to the second data line. The second latch is coupled to the first latch.

[0192] As used herein, the terms “about” and “approximately” generally indicate plus or minus 10% of the stated value. For example, about 0.5 would include 0.45 to 0.55, about 10 would include 9 to 11, and about 1000 would include 900 to 1100.

[0193] The foregoing outlines the features of several embodiments such that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for the same purposes and / or achieving the same advantages as those introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that such equivalent constructions may be made herein in various changes, substitutions, and alterations without departing from the spirit and scope of the present disclosure.

Claims

1. An input / output circuit, characterized in that: Include: a bypass circuit for directly receiving a data signal and indirectly receiving a write enable signal; a first latch coupled between a first data connection and a second data connection, and comprising a first switch and a second switch, wherein the first switch is coupled between the first data connection and an output terminal of the bypass circuit, and wherein the second switch is coupled between the second data connection and the output terminal of the bypass circuit; a second latch coupled to the first latch and configured to generate a data output signal based on a voltage level present on the second data line; a first transistor coupled to the first latch and gated by a sensing start signal; and a second transistor coupled to the first latch and gated by a clock signal, The first transistor and the second transistor are alternately activated in each of a plurality of operation modes of the input / output circuit.

2. The input / output circuit according to claim 1, wherein: In at least one of the plurality of operation modes, the first latch and the second latch are operated together as a data flip-flop, the clock signal is disabled, and the sensing start signal is used as a clock source of the data flip-flop to perform a two-state flip-flop.

3. The input / output circuit according to claim 1, wherein: The bypass circuit includes an XOR gate, which enables one of the multiple inputs of the XOR gate to receive the write-initiating signal via at least an inverter and a NOR gate.

4. The input / output circuit according to claim 3, characterized in that The NOR gate enables one of its multiple inputs to receive a control signal, and when the control signal is in a first logic state, the input / output circuit is set in a non-test mode, and when the control signal is in a second logic state, the input / output circuit is set in a test mode.

5. The input / output circuit according to claim 1, wherein: When the input / output circuit is in a read mode, the second transistor, the first switch and the second switch are disabled, and the first transistor is enabled.

6. The input / output circuit according to claim 1, wherein: When the input / output circuit is in a write mode, the first transistor is disabled, and the second transistor, the first switch and the second switch are enabled.

7. The input / output circuit according to claim 1, wherein: When the input / output circuit is in a test mode, the first transistor, the first switch and the second switch are activated, and the second transistor is disabled.

8. The input / output circuit according to claim 1, wherein: The first latch is coupled to a memory array via the first data connection and the second data connection.

9. A memory circuit, characterized in that: Include: A memory array includes a memory bit cell coupled between a first data connection and a second data connection; and An input / output circuit coupled to the memory array and comprising: A bypass circuit, for receiving a data signal and a write enable signal to generate a bypass data signal; a first latch coupled to the first data connection and the second data connection, and comprising a first switch and a second switch, wherein the first switch is used to selectively couple the bypass data signal to the first data connection, and the second switch is used to selectively couple an inverted signal of the bypass data signal to the second data connection; as well as A second latch is coupled to the first latch and is used to generate a data output signal based on a voltage level present on the second data line.

10. A memory circuit, characterized in that: Include: A memory array includes a memory bit cell coupled between a first data connection and a second data connection; and An input / output circuit coupled to the memory array and comprising: A bypass circuit, for receiving a data signal and a write enable signal to generate a bypass data signal; a first latch coupled to the first data connection and the second data connection, and comprising a first switch and a second switch, wherein the first switch is used to selectively couple the bypass data signal to the first data connection, and the second switch is used to selectively couple an inverted signal of the bypass data signal to the second data connection; as well as A second latch is coupled to the first latch.

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