Circuit for optimizing current sampling precision
By designing a sampling circuit that can be switched according to the current size in the circuit, the impact of traditional current sampling methods on the subsequent circuit at large current and the insufficient sampling accuracy of small current is solved, and accurate current sampling within different current ranges is achieved.
Patent Information
- Application Number
- CN202421559468.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-03
- Publication Date
- 2025-06-03
- Estimated Expiration
- 2034-07-03
AI Technical Summary
Traditional current sampling methods may have adverse effects on the subsequent circuit when sampling large currents, and it is difficult to accurately measure when sampling small currents, affecting accuracy.
A circuit including a first sampling circuit and a second sampling circuit is designed, and the state of the MOS tube is controlled by the control chip according to the input current magnitude, and an appropriate sampling resistance value is selected to achieve accurate sampling in different current ranges.
When sampling large current, select the second sampling circuit with a smaller resistance value to reduce the voltage drop across the resistor to ensure the normal operation of the subsequent circuit; when sampling small current, select the first sampling circuit with a larger resistance value to increase the voltage difference between the resistor, ensure accurate measurement of the ADC, and improve sampling accuracy.
Smart Images
Figure CN222939179U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of sampling circuits, and particularly relates to a circuit for optimizing current sampling accuracy. Background Art
[0002] Traditional current sampling methods usually involve connecting a milliohm-level resistor in series in the power supply path, measuring the voltage difference across the resistor, and performing appropriate amplification processing to indirectly calculate the magnitude of the current. However, this method faces some challenges and limitations in practical applications.
[0003] On the one hand, when sampling large currents above several tens of milliamperes, using a milliohm-level resistor as the sampling resistor is a feasible option. Since the resistance value is small, the voltage drop across the resistor is relatively small, and the impact on the subsequent circuit is small, thus ensuring the accuracy of current sampling. However, when sampling small currents of a few milliamperes, due to the unchanged resistance value of the sampling resistor, the voltage drop across the resistor is too small, making it difficult for the ADC to accurately measure, thereby affecting the accuracy of current sampling.
[0004] On the other hand, if an ohm-level resistor is used as the sampling resistor to improve the accuracy of small current sampling, although the accuracy of small current sampling can be ensured, when sampling large currents, due to the large resistance value, the voltage drop across the resistor will increase significantly, which may have an adverse impact on the normal operation of the subsequent circuit, such as reducing the power supply voltage and increasing power consumption. Summary of the Utility Model
[0005] The purpose of the utility model is to overcome the deficiencies of the prior art and provide a circuit for optimizing current sampling accuracy to solve the drawbacks of the prior art.
[0006] To achieve the above purpose, the utility model adopts the following technical solutions:
[0007] An embodiment of the utility model provides a circuit for optimizing current sampling accuracy, which includes: a control chip, a first sampling circuit, a second sampling circuit, and a load output port. The first end of the first sampling circuit is connected to the first GPIO port of the control chip, the second end of the first sampling circuit is connected to the first ADC port of the control chip and the load output port, the first end of the second sampling circuit is connected to the second GPIO port of the control chip, and the second end of the second sampling circuit is connected to the second ADC port of the control chip and the load output port;
[0008] The first sampling circuit includes: a first power input port, a first MOS transistor, and a first sampling resistor. The first power input port is respectively connected to the source electrode of the first MOS transistor and grounded. The gate electrode of the first MOS transistor is connected to the first GPIO port. The drain electrode of the first MOS transistor is connected to the first end of the first sampling resistor. The second end of the first sampling resistor is respectively connected to the first ADC port and the load output port;
[0009] The second sampling circuit includes: a second power input port, a second MOS transistor, and a second sampling resistor. The second power input port is respectively connected to the source electrode of the second MOS transistor and grounded. The gate electrode of the second MOS transistor is connected to the second GPIO port. The drain electrode of the second MOS transistor is connected to the first end of the second sampling resistor. The second end of the second sampling resistor is respectively connected to the second ADC port and the load output port;
[0010] Wherein, the control chip is used to control the first MOS transistor and the second MOS transistor to be in a conducting state or a cut-off state, and the resistance value of the first sampling resistor is greater than that of the second sampling resistor.
[0011] As a preferred technical solution of the present invention, the first sampling circuit further includes a first operational amplifier disposed between the first sampling resistor and the first ADC port. The IN+ port of the first operational amplifier is connected to the first end of the first sampling resistor. The IN- port of the first operational amplifier is connected to the second end of the first sampling resistor. The OUT port of the first operational amplifier is connected to the first ADC port.
[0012] As a preferred technical solution of the present invention, the first sampling circuit further includes a first capacitor, a second capacitor, and a third capacitor. The first end of the first capacitor is connected to the coupling point between the first power input port and the source electrode of the first MOS transistor. The second end of the first capacitor is grounded. The first end of the second capacitor is connected to the second end of the first sampling resistor and the first end of the third capacitor. The second end of the second capacitor is grounded. The first end of the third capacitor is connected to the load output port. The second end of the third capacitor is grounded.
[0013] As a preferred technical solution of the present invention, the first sampling circuit further includes a fourth capacitor and a fifth capacitor. The first end of the fourth capacitor is connected to the V+ port of the first operational amplifier. The second end of the fourth capacitor is grounded. The first end of the fifth capacitor is connected to the OUT port of the first operational amplifier. The second end of the fifth capacitor is grounded.
[0014] As a preferred technical solution of the present utility model, the amplification factor of the first operational amplifier is 100 times.
[0015] As a preferred technical solution of the present utility model, the second sampling circuit further includes a second operational amplifier disposed between the second sampling resistor and the second ADC port. The IN+ port of the second operational amplifier is connected to the first end of the second sampling resistor, the IN- port of the second operational amplifier is connected to the second end of the second sampling resistor, and the OUT port of the second operational amplifier is connected to the second ADC port.
[0016] As a preferred technical solution of the present utility model, the second sampling circuit further includes a sixth capacitor, a seventh capacitor, and an eighth capacitor. The first end of the sixth capacitor is connected to the coupling point of the second power input port and the source electrode of the second MOS transistor, and the second end of the sixth capacitor is grounded; the first end of the seventh capacitor is connected to the second end of the second sampling resistor and the first end of the eighth capacitor, and the second end of the seventh capacitor is grounded; the first end of the eighth capacitor is connected to the load output port, and the second end of the eighth capacitor is grounded.
[0017] As a preferred technical solution of the present utility model, the second sampling circuit further includes a ninth capacitor and a tenth capacitor. The first end of the ninth capacitor is connected to the V+ port of the second operational amplifier, and the second end of the ninth capacitor is grounded; the first end of the tenth capacitor is connected to the OUT port of the second operational amplifier, and the second end of the tenth capacitor is grounded.
[0018] As a preferred technical solution of the present utility model, the amplification factor of the second operational amplifier is 100 times.
[0019] As a preferred technical solution of the present utility model, the resistance value of the first sampling resistor is 10 Ω, and the resistance value of the second sampling resistor is 0.01 Ω.
[0020] Compared with the prior art, the circuit for optimizing the current sampling accuracy of the present utility model controls the first MOS transistor and the second MOS transistor to be in a conducting state or a cut-off state by the control chip according to the input current magnitudes of the first power input port and the second power input port. Further, when sampling a large current, the second sampling circuit where the second sampling resistor with a smaller resistance value is located is selected to work; when sampling a small current, the first sampling circuit where the first sampling resistor with a larger resistance value is located is selected to work, so as to achieve accurate current sampling within different current ranges.
[0021] The above description is only an overview of the technical solution of the present utility model. In order to better understand the technical means of the present utility model, it can be implemented according to the content of the specification. And in order to make the above and other purposes, features and advantages of the present utility model more obvious and understandable, the following preferred embodiments are specifically described in detail as follows. Brief Description of the Drawings
[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings required for the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present utility model. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0023] Figure 1 It is a schematic structural diagram of a circuit for optimizing the current sampling accuracy of the present utility model. Detailed Embodiment
[0024] In order to make the purpose, technical solutions and advantages of the present utility model more clear and understandable, the present utility model will be further described in detail below with reference to the drawings and specific embodiments.
[0025] The technical solutions in the embodiments of the present utility model will be clearly and completely described below with reference to the drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all the embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present utility model.
[0026] In the description of the present utility model, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present utility model.
[0027] In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present utility model, "a plurality" means two or more, unless otherwise specifically defined.
[0028] In the present utility model, unless otherwise clearly defined and limited, terms such as "installation", "connection", "coupling", "fixing", etc. shall be understood in a broad sense. For example, it can be a connection, a detachable connection, or an integral body; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.
[0029] In the present utility model, unless otherwise clearly defined and limited, the first feature being "on" or "under" the second feature may include the direct contact between the first and second features, or may include the situation where the first and second features are not in direct contact but in contact through other features therebetween. Moreover, the first feature being "above", "over" and "on top of" the second feature includes that the first feature is directly above and obliquely above the second feature, or merely indicates that the horizontal height of the first feature is higher than that of the second feature. The first feature being "under", "below" and "beneath" the second feature includes that the first feature is directly below and obliquely below the second feature, or merely indicates that the horizontal height of the first feature is lower than that of the second feature.
[0030] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present utility model. In this specification, the schematic descriptions of the above terms should not be understood as necessarily referring to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification.
[0031] Please refer to Figure 1, an embodiment of the present utility model discloses a circuit for optimizing current sampling accuracy, which includes: a control chip U1, a first sampling circuit 10, a second sampling circuit 20, and a load output port. The first end of the first sampling circuit 10 is connected to the first GPIO port of the control chip U1, and the second end of the first sampling circuit 10 is connected to the first ADC port of the control chip U1 and the load output port. The first end of the second sampling circuit 20 is connected to the second GPIO port of the control chip U1, and the second end of the second sampling circuit 20 is connected to the second ADC port of the control chip U1 and the load output port; The first sampling circuit 10 includes: a first power input port VCC1, a first MOS transistor Q1, and a first sampling resistor R1. The first power input port VCC1 is respectively connected to the source electrode of the first MOS transistor Q1 and grounded. The gate electrode of the first MOS transistor Q1 is connected to the first GPIO port, and the drain electrode of the first MOS transistor Q1 is connected to the first end of the first sampling resistor R1. The second end of the first sampling resistor R1 is respectively connected to the first ADC port and the load output port; The second sampling circuit 20 includes: a second power input port VCC2, a second MOS transistor Q2, and a second sampling resistor R2. The second power input port VCC2 is respectively connected to the source electrode of the second MOS transistor Q2 and grounded. The gate electrode of the second MOS transistor Q2 is connected to the second GPIO port, and the drain electrode of the second MOS transistor Q2 is connected to the first end of the second sampling resistor R2. The second end of the second sampling resistor R2 is respectively connected to the second ADC port and the load output port; Wherein, the control chip U1 is used to control the first MOS transistor Q1 and the second MOS transistor Q2 to be in a conducting state or a cut-off state, and the resistance value of the first sampling resistor R1 is greater than that of the second sampling resistor R2.
[0032] Preferably, both the first MOS transistor Q1 and the second MOS transistor Q2 are P-MOS transistors, and the control chip U1 is an MCU. Specifically, the model of the control chip U1 is STM32F103VCT6-LQFP100, the first GPIO port is the SPI2-NSS / PB13 port it has, the second GPIO port is the PD13 port it has, the first ADC port is the PD10 port it has, and the second ADC port is the PC7 port it has. Optionally, the load output port in this embodiment is connected to an SSD (Solid State Drive) device.
[0033] In this embodiment, after receiving the input current from the first power input port VCC1 and the second power input port VCC2, the control chip U1 determines whether the first MOS transistor Q1 and the second MOS transistor Q2 are in the on state or the off state according to the magnitude of the current. In one embodiment, when the control chip U1 detects that the power supply currents from the first power input port VCC1 and the second power input port VCC2 to the load output port are 10 mA to 3.3 A, the control chip U1 controls the first MOS transistor Q1 to turn off and the second MOS transistor Q2 to turn on through the first GPIO port and the second GPIO port respectively. At this time, the current only supplies power to the load output port through the second sampling circuit 20 where the second MOS transistor Q2 and the second sampling resistor R2 are located. Since the resistance value of R2 is small, it will not affect the power supply voltage of the load output port. Then, the second ADC port collects the voltage difference across the second sampling resistor R2 and gives the collected voltage difference to the control chip U1 for current sampling data analysis. When the control chip U1 detects that the power supply currents from the first power input port VCC1 and the second power input port VCC2 to the load output port are 0.1 mA to 10 mA, with the second MOS transistor Q2 turned on, the control chip U1 controls the first MOS transistor Q1 to also turn on through the first GPIO port. At this time, the first sampling circuit 10 and the second sampling circuit 20 supply power to the load output port simultaneously. After the power supply is stable, the second MOS transistor Q2 is turned off, and the load output port is independently powered by the first sampling circuit 10 where the first MOS transistor Q1 is located. Since the current is very small, only at the milliamp level, the voltage drop caused by the first sampling resistor R1 will not affect the power supply voltage of the subsequent circuit. Moreover, the voltage difference across the first sampling resistor R1 with a larger resistance value is collected by the second ADC port and given to the control chip U1 for current sampling data analysis.
[0034] Specifically, the resistance value of the first sampling resistor R1 is 10 Ω, and the resistance value of the second sampling resistor R2 is 0.01 Ω. It can be understood that by selecting different resistance values of the first sampling resistor R1 or the second sampling resistor R2, the voltage drop across the resistor (V = IR) can be controlled at different current magnitudes. In the case of large current, the second sampling resistor R2 with a smaller resistance value (0.01 Ω) is used to reduce the voltage drop and ensure the normal operation of the subsequent circuit. In the case of small current, the first sampling resistor R1 with a larger resistance value (10 Ω) is used to increase the voltage drop across the resistor, so that the first ADC port can sample more accurately.
[0035] Further, the first sampling circuit 10 further includes a first operational amplifier U2 disposed between the first sampling resistor R1 and the first ADC port. The IN+ port of the first operational amplifier U2 is connected to the first end of the first sampling resistor R1, the IN- port of the first operational amplifier U2 is connected to the second end of the first sampling resistor R1, and the OUT port of the first operational amplifier U2 is connected to the first ADC port. It can be understood that an operational amplifier (Op-Amp) is a circuit unit with a multiple amplification function that can amplify a weak signal to a sufficient amplitude for subsequent circuit processing. In the first sampling circuit 10, the first operational amplifier U2 is used to amplify the voltage difference across the first sampling resistor R1 to match the input voltage range of the first ADC port. It should be explained that the ADC port usually has a specific input voltage range. If the voltage across the sampling resistor is not within this range, the ADC port will not be able to accurately sample. The role of the first operational amplifier U2 is to adjust this voltage to meet the input requirements of the ADC port. Specifically, the IN+ port of the first operational amplifier U2 is connected to the first end (i.e., the current inflow end) of the first sampling resistor R1, and the IN- port is connected to the second end (i.e., the current outflow end) of the first sampling resistor R1. Therefore, the first operational amplifier U2 can measure the voltage difference across the first sampling resistor R1 and amplify it through its internal circuit. The amplified voltage signal is output from the OUT port of the first operational amplifier U2 and connected to the first ADC port. The first ADC port can receive a signal within its input voltage range and perform accurate sampling. Specifically, the amplification factor of the first operational amplifier U2 is 100 times.
[0036] Further, the first sampling circuit 10 further includes a first capacitor C1, a second capacitor C2, and a third capacitor C3. The first end of the first capacitor C1 is connected to the coupling point between the first power input port VCC1 and the source of the first MOS transistor Q1, and the second end of the first capacitor C1 is grounded; the first end of the second capacitor C2 is connected to the second end of the first sampling resistor R1 and the first end of the third capacitor C3, and the second end of the second capacitor C2 is grounded; the first end of the third capacitor C3 is connected to the load output port, and the second end of the third capacitor C3 is grounded.
[0037] Specifically, the first sampling circuit 10 further includes a fourth capacitor C4 and a fifth capacitor C5. The first end of the fourth capacitor C4 is connected to the V+ port of the first operational amplifier U2, and the second end of the fourth capacitor C4 is grounded. The first end of the fifth capacitor C5 is connected to the OUT port of the first operational amplifier U2, and the second end of the fifth capacitor C5 is grounded. In this embodiment, the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, and the fifth capacitor C5 play a filtering and stabilizing role in the first sampling circuit 10. By filtering out high-frequency noise and stabilizing the voltage across the first sampling resistor R1, the signal-to-noise ratio and stability of the sampling signal are improved, thereby improving the sampling accuracy.
[0038] Further, the second sampling circuit 20 further includes a second operational amplifier U3 disposed between the second sampling resistor R2 and the second ADC port. The IN+ port of the second operational amplifier U3 is connected to the first end of the second sampling resistor R2, the IN- port of the second operational amplifier U3 is connected to the second end of the second sampling resistor R2, and the OUT port of the second operational amplifier U3 is connected to the second ADC port. Specifically, the IN+ port of the second operational amplifier U3 is connected to the first end of the second sampling resistor R2 (i.e., the current inflow end), and the IN- port is connected to the second end of the second sampling resistor R2 (i.e., the current outflow end). Therefore, the second operational amplifier U3 can measure the voltage difference across the second sampling resistor R2 and amplify it through its internal circuit. The amplified voltage signal is output from the OUT port of the second operational amplifier U3 and connected to the second ADC port. The second ADC port can receive a signal within its input voltage range and perform accurate sampling. Specifically, the amplification factor of the second operational amplifier U3 is 100 times.
[0039] Further, the second sampling circuit 20 further includes a sixth capacitor C6, a seventh capacitor C7, and an eighth capacitor C8. The first end of the sixth capacitor C6 is connected to the coupling point between the second power input port VCC2 and the source of the second MOS transistor Q2, and the second end of the sixth capacitor C6 is grounded. The first end of the seventh capacitor C7 is connected to the second end of the second sampling resistor R2 and the first end of the eighth capacitor C8, and the second end of the seventh capacitor C7 is grounded. The first end of the eighth capacitor C8 is connected to the load output port, and the second end of the eighth capacitor C8 is grounded.
[0040] Specifically, the second sampling circuit 20 further includes a ninth capacitor C9 and a tenth capacitor C10. The first end of the ninth capacitor C9 is connected to the V+ port of the second operational amplifier U3, and the second end of the ninth capacitor C9 is grounded; the first end of the tenth capacitor C10 is connected to the OUT port of the second operational amplifier U3, and the second end of the tenth capacitor C10 is grounded. In this embodiment, the sixth capacitor C6, the seventh capacitor C7, the eighth capacitor C8, the ninth capacitor C9, and the tenth capacitor C10 play a filtering and stabilizing role in the second sampling circuit 20. By filtering out high-frequency noise and stabilizing the voltage across the second sampling resistor R2, the signal-to-noise ratio and stability of the sampling signal are improved, thereby improving the sampling accuracy.
[0041] Compared with the prior art, the circuit for optimizing the current sampling accuracy of the present invention controls the first MOS transistor and the second MOS transistor to be in an on state or an off state according to the input current magnitudes of the first power input port and the second power input port through a control chip. Thus, when sampling a large current, the second sampling circuit where the second sampling resistor with a smaller resistance value is located is selected to work; when sampling a small current, the first sampling circuit where the first sampling resistor with a larger resistance value is located is selected to work, realizing accurate current sampling within different current ranges.
[0042] As described above, only the specific embodiments of the present invention are provided, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of various equivalent modifications or substitutions, and these modifications or substitutions should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims
1. A circuit for optimizing current sampling accuracy, characterized in that: include: A control chip, a first sampling circuit, a second sampling circuit, and a load output port, wherein a first end of the first sampling circuit is connected to a first GPIO port of the control chip, a second end of the first sampling circuit is connected to a first ADC port of the control chip and the load output port, a first end of the second sampling circuit is connected to a second GPIO port of the control chip, and a second end of the second sampling circuit is connected to a second ADC port of the control chip and the load output port; The first sampling circuit includes: a first power input port, a first MOS transistor, and a first sampling resistor, the first power input port is respectively connected to the source of the first MOS transistor and grounded, the gate of the first MOS transistor is connected to the first GPIO port, the drain of the first MOS transistor is connected to the first end of the first sampling resistor, and the second end of the first sampling resistor is respectively connected to the first ADC port and the load output port; The second sampling circuit includes: a second power input port, a second MOS tube, and a second sampling resistor, the second power input port is respectively connected to the source of the second MOS tube and grounded, the gate of the second MOS tube is connected to the second GPIO port, the drain of the second MOS tube is connected to the first end of the second sampling resistor, and the second end of the second sampling resistor is respectively connected to the second ADC port and the load output port; The control chip is used to control the first MOS tube and the second MOS tube to be in an on state or an off state, and the resistance of the first sampling resistor is greater than that of the second sampling resistor.
2. A circuit for optimizing current sampling accuracy according to claim 1, characterized in that: The first sampling circuit also includes a first operational amplifier arranged between the first sampling resistor and the first ADC port, an IN+ port of the first operational amplifier is connected to the first end of the first sampling resistor, an IN- port of the first operational amplifier is connected to the second end of the first sampling resistor, and an OUT port of the first operational amplifier is connected to the first ADC port.
3. A circuit for optimizing current sampling accuracy according to claim 2, characterized in that: The first sampling circuit also includes a first capacitor, a second capacitor, and a third capacitor. The first end of the first capacitor is connected to the coupling point between the first power input port and the source of the first MOS tube, and the second end of the first capacitor is grounded; the first end of the second capacitor is connected to the second end of the first sampling resistor and the first end of the third capacitor, and the second end of the second capacitor is grounded; the first end of the third capacitor is connected to the load output port, and the second end of the third capacitor is grounded.
4. A circuit for optimizing current sampling accuracy according to claim 3, characterized in that: The first sampling circuit also includes a fourth capacitor and a fifth capacitor, wherein a first end of the fourth capacitor is connected to the V+ port of the first operational amplifier, and a second end of the fourth capacitor is grounded; a first end of the fifth capacitor is connected to the OUT port of the first operational amplifier, and a second end of the fifth capacitor is grounded.
5. A circuit for optimizing current sampling accuracy according to claim 4, characterized in that: The amplification factor of the first operational amplifier is 100 times.
6. The circuit for optimizing current sampling accuracy according to claim 1, characterized in that: The second sampling circuit also includes a second operational amplifier arranged between the second sampling resistor and the second ADC port, an IN+ port of the second operational amplifier is connected to the first end of the second sampling resistor, an IN- port of the second operational amplifier is connected to the second end of the second sampling resistor, and an OUT port of the second operational amplifier is connected to the second ADC port.
7. The circuit for optimizing current sampling accuracy according to claim 6, characterized in that: The second sampling circuit also includes a sixth capacitor, a seventh capacitor, and an eighth capacitor. The first end of the sixth capacitor is connected to the coupling point between the second power input port and the source of the second MOS tube, and the second end of the sixth capacitor is grounded; the first end of the seventh capacitor is connected to the second end of the second sampling resistor and the first end of the eighth capacitor, and the second end of the seventh capacitor is grounded; the first end of the eighth capacitor is connected to the load output port, and the second end of the eighth capacitor is grounded.
8. The circuit for optimizing current sampling accuracy according to claim 7, characterized in that: The second sampling circuit also includes a ninth capacitor and a tenth capacitor, wherein a first end of the ninth capacitor is connected to the V+ port of the second operational amplifier, and a second end of the ninth capacitor is grounded; a first end of the tenth capacitor is connected to the OUT port of the second operational amplifier, and a second end of the tenth capacitor is grounded.
9. The circuit for optimizing current sampling accuracy according to claim 8, characterized in that: The amplification factor of the second operational amplifier is 100 times.
10. The circuit for optimizing current sampling accuracy according to claim 1, characterized in that: The resistance value of the first sampling resistor is 10Ω, and the resistance value of the second sampling resistor is 0.01Ω.