Crystal grain stacking structure and semiconductor structure

Abstract

Semiconductor structures, die stack structures, and fabrication methods are provided. In one example, a semiconductor structure includes a die having a test pad disposed on a front side of the die. The test pad has a probe mark in an upper portion of the test pad. The probe mark has an open end at the top surface of the test pad, a bottom wall, a sidewall connected to the bottom wall, and a space between the open end, the bottom wall, and the sidewall. The semiconductor structure further includes a first capping layer and a second capping layer. The first covering layer is arranged on the front side of the first test pad and the side wall and the bottom wall of the probe mark. The second covering layer is arranged on the first covering layer. The first cover layer and the second cover layer are made of different materials.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to semiconductor packages, and more particularly to semiconductor structures and die stack structures. Background Art

[0002] In recent years, the semiconductor industry has experienced rapid growth due to the increasing integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. This increase in integration density is mainly attributed to the continuous reduction of the minimum feature size, which allows more components to be integrated into a given area.

[0003] These smaller electronic components also require smaller packages that occupy a smaller area than previous packages. Exemplary types of packages for semiconductors include quad flat pack (QFP), pin grid array (PGA), ball grid array (BGA), flip chip (FC), three-dimensional integrated circuit (3DIC), wafer level package (WLP), and package on package (PoP) devices. Some 3DICs are fabricated by placing a die on top of a die on a semiconductor wafer level. 3DICs provide improved integration density and other advantages, such as faster speed and higher bandwidth, because the length of the interconnects between the stacked dies is reduced. However, there are quite a number of challenges in the technologies of die stacking and wafer packaging that need to be addressed. Summary of the Utility Model

[0004] Some embodiments of the present disclosure provide a semiconductor structure, comprising: a die, a first cover layer, and a second cover layer. The die has test pads disposed on a front side of the die, wherein the test pads have probe marks in an upper portion of the test pads, and the probe marks have open ends at a top surface of the test pads, bottom walls, side walls connected to the bottom walls, and spaces between the open ends, the bottom walls, and the side walls. The first cover layer is disposed on the front side of the test pads and in the spaces, and on the side walls and the bottom walls of the probe marks, and the first cover layer comprises a first structure. The second cover layer is disposed on the first cover layer and in the spaces, wherein the second cover layer comprises a second structure different from the first structure.

[0005] Some embodiments of the present disclosure provide a die stack structure, including a first semiconductor structure, a second semiconductor structure, and at least one bonding structure. The first semiconductor structure and the second semiconductor structure are bonded together face-to-face at a bonding interface. The first semiconductor structure includes a first die, a first capping layer, a second capping layer, and a third capping layer. The first die has a first metal pad disposed on a front side of the first die, wherein the first metal pad is a first test pad and has a first probe mark in an upper portion of the first test pad. The first probe mark has an open end at a top surface of the first test pad, a bottom wall, sidewalls connected to the bottom wall, and a space between the open end, the bottom wall, and the sidewalls. The first capping layer is disposed on the front side of the first test pad and in the space, and on the sidewalls and the bottom wall of the probe mark, and the first capping layer includes a first structure. The second capping layer is disposed on the first capping layer and in the space, wherein the second capping layer includes a second structure different from the first structure. The third capping layer is disposed on the second capping layer. The second semiconductor structure includes a second die and at least one capping layer. The second die has a second metal pad disposed on a front side of the second die. The at least one capping layer is disposed on the second metal pad. The at least one bonding structure connects the first metal pad and the second metal pad, wherein the at least one bonding structure vertically extends through the first, second, and third capping layers of the first semiconductor structure, the bonding interface, the third capping layer, and the at least one capping layer of the second semiconductor structure, and the at least one bonding structure is adjacent to the first probe mark.

[0006] Some embodiments of the present disclosure provide a semiconductor structure, including: a die, a first capping layer, and a second capping layer. The die has a test pad disposed on a front side of the die, wherein the test pad has a probe mark in an upper portion of the test pad. The first capping layer is disposed on the front side of the test pad and in the space, and on the sidewalls and the bottom wall of the probe mark, and the first capping layer includes a first structure. The second capping layer is disposed on the first capping layer and in the space, wherein the second capping layer includes a second structure different from the first structure, the first capping layer has a first thickness, and the second capping layer has a second thickness greater than the first thickness. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figures 1A to 1F A schematic diagram of a cross-sectional view showing an intermediate stage of forming an exemplary semiconductor structure according to some embodiments;

[0009] Figures 2A to 2CSchematic cross-sectional view illustrating an example method of forming a die stack structure according to some embodiments;

[0010] Figure 3 Flowchart of an example method for forming a semiconductor structure and a die stack structure according to some embodiments.

[0011]

Reference Signs

[0012] 10: First semiconductor structure

[0013] 10A, 10B, 10C, 10D, 10E, 10F: Semiconductor structures

[0014] 20: Second semiconductor structure

[0015] 100: First die

[0016] 100a: Front side

[0017] 102: Substrate / First semiconductor substrate

[0018] 103: First device region

[0019] 104: First interconnect structure

[0020] 106, 206: First insulating material

[0021] 108, 208: First metal feature

[0022] 108a, 108b: Top metal feature

[0023] 110: First passivation layer

[0024] 112, 112a, 112b: First test pad

[0025] 113: Top surface

[0026] 114: Region

[0027] 117: Opening

[0028] 117a: Opening / First opening

[0029] 117b: Opening / Second opening

[0030] 121: Overlay / First overlay

[0031] 121a: Front surface

[0032] 122: Overlay / Second overlay

[0033] 122a: Front surface

[0034] 123: Overlayer / Third Overlayer

[0035] 123a: Front Surface

[0036] 124: Bonding Layer

[0037] 128: Insulating Encapsulation

[0038] 130: First Through-Substrate Via / TSV

[0039] 132: Through-Dielectric Via / TDV

[0040] 140: Redistribution Circuit Structure

[0041] 140a: Dielectric Layer

[0042] 140b: Redistribution Conductive Layer

[0043] 140b1: Bonding Pad

[0044] 140b2: Test Pad

[0045] 150: Passivation Layer

[0046] 160: Probe Mark / First Probe Mark

[0047] 160a: Internal Portion

[0048] 160b: External Portion

[0049] 161: Open End

[0050] 162: Side Wall

[0051] 163: Bottom Wall

[0052] 164: Corner Portion

[0053] 165: Protruding Structure

[0054] 166: First End

[0055] 167: Second End

[0056] 181: Connector

[0057] 181a, 181b, 181c, 181d, 181e: Connector

[0058] 182: Bonding Interface

[0059] 185: Bonding Structure

[0060] 185a, 185b, 185c, 185d, 185e: Bonding Structure

[0061] 190: Bonding Region

[0062] 200: Second semiconductor / Second die

[0063] 200A, 200B, 200C: Die stack structure

[0064] 202: Second semiconductor substrate

[0065] 203: Second device area

[0066] 204: Second interconnect structure

[0067] 210: Second passivation layer

[0068] 212: Second test pad

[0069] 212a: Second test pad

[0070] 221: Capping layer / First capping layer

[0071] 222: Capping layer / Second capping layer

[0072] 223: Capping layer / Third capping layer

[0073] 224: Bonding layer

[0074] 260: Probe mark / Second probe mark

[0075] 281, 281a, 281b, 281c, 281d, 281e, 281f: Connector

[0076] 300: Method

[0077] 302, 304, 306, 308, 310, 312, 314: Operations

[0078] F: Front side

[0079] F': Front side

[0080] H: Height

[0081] T 1 : First thickness

[0082] T 2 : Second thickness

[0083] T 3 : Third thickness

[0084] T 4 : Thickness

[0085] T 5 : Thickness

[0086] W O : Width

[0087] W P : Bottom width

[0088] X: X-axis

[0089] Y: Y-axis

[0090] Z: Z-axis

[0091] α: Angle Detailed implementation manners

[0092] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and in itself does not indicate the relationship between the various embodiments and / or configurations discussed.

[0093] In addition, for ease of description, spatially relative terms such as "below", "beneath", "lower", "above", "upper", and the like may be used herein to describe the relationship of one element or feature shown in the figures to another (or other) element or feature. The spatially relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0094] In addition, the source / drain region may refer to the source or the drain, individually or jointly depending on the context. For example, a device may include a first source / drain region and a second source / drain region, as well as other components. The first source / drain region may be the source region, while the second source / drain region may be the drain region, and vice versa. Those of ordinary skill in the art will recognize many variations, modifications, and alternatives.

[0095] Other features and processes may also be included. For example, test structures may be included to assist in the verification testing of 3D packages or 3DIC devices. The test structures may include, for example, test pads formed in the redistribution layer or on the substrate, which allow for the testing of 3D packages or 3DICs, using probes and / or probe cards, and the like. The verification testing may be performed either on the intermediate structure or on the final structure. Additionally, the structures and methods disclosed herein may be used in combination with testing methods that incorporate intermediate verification of known good die to increase yield and reduce costs.

[0096] Some embodiments of the present disclosure are described. Additional operations may be provided before, during, and / or after the stages described in these embodiments. For different embodiments, some of the described stages may be replaced or eliminated. Some of the features described below may be replaced or eliminated, and additional features may be added for different embodiments. Although some embodiments are discussed as operations performed in a specific order, these operations may also be performed in another logical order.

[0097] Overview

[0098] When testing a semiconductor wafer or die, probes are used to contact metal pads (i.e., test metal pads or test pads) on the die, and these probes may leave marks, dents, or scratches on the pads. These probe marks may affect the functionality of the die or cause problems during subsequent wafer integration, die stacking, or packaging processes. In particular, the shape and size of some probe marks may be too deep (e.g., having a high aspect ratio), or the number may be large, and if not treated properly, they may lead to reliability issues or failures of the device. For example, a capping layer is formed on the test pads prior to the die stacking process. The probe marks are filled with the material of the capping layer. The capping layer is typically a high-stress material used to protect the die. However, due to its high stress, the capping layer may cause incompatibility between the capping layer and the test pads, and the probe marks may induce or initiate voids and cracks in the high-stress capping layer during the die stacking process. For example, when openings are formed in the area around or adjacent to the probe marks, cracks in the capping layer or delamination of the capping layer from the test pads may be induced by the probe marks. Therefore, in the die stacking process, the area around the probe marks is typically restricted. For example, other components such as interconnects or bonding elements are not placed in close proximity to the probe marks.

[0099] Some embodiments of the present disclosure provide techniques that address the above challenges and / or mitigate design limitations caused by probe marking. An insight provided in some embodiments of the present disclosure is regarding a novel semiconductor structure (sometimes also referred to as a die structure) having a multi-layer protection structure, the multi-layer protection structure having a plurality of overcoat layers that cover test pads and fill in probe marks of the test pads. According to some embodiments, at least two overcoat layers are sequentially formed to cover the test pads. A first overcoat layer is formed on a front surface of the semiconductor structure to cover the test pads. The first overcoat layer may include a low-stress oxide that at least partially fills a portion of the probe marks. A second overcoat layer is then formed on the first overcoat layer. According to some embodiments, the probe marks may be completely or substantially filled with the first overcoat layer. According to some embodiments, an inner portion of the probe marks is filled with the first overcoat layer, and an outer portion of the probe marks is filled with the second overcoat layer. Thus, the probe marks may be filled with both a low-stress oxide and a high-stress oxide. The second overcoat layer may include a high-stress oxide that protects the die and provides mechanical strength to the semiconductor structure. The second overcoat layer also provides good step coverage for the probe marks, particularly for probe marks having a relatively high aspect ratio. The first overcoat layer may serve as both a buffer layer and a bonding layer to increase the compatibility and bonding strength between the test pads and the second overcoat layer. Thus, the combination of multiple overcoat layers (e.g., the first and second overcoat layers) may reduce the risk of voids, cracks, seams, damage, and delamination induced, initiated, or propagated by the probe marks and improve the overall compatibility and mechanical durability of the semiconductor structure during the die stacking process.

[0100] According to some embodiments, a third overcoat layer may be formed on the second overcoat layer. The third overcoat layer may serve as an additional protection layer and a bonding attachment layer for subsequent die stacking processes.

[0101] Another insight provided in some embodiments of the present disclosure is regarding a die stack structure formed by a first semiconductor structure and a second semiconductor structure joined via one or more connectors. According to some embodiments, at least one connector (i.e., a bonding structure) interconnects a test pad of the first semiconductor structure and a metal component of the second semiconductor structure. At least one connector is proximate to a first probe mark. Because of multiple cover layers that cover the test pads and fill the probe marks, the overall mechanical durability and performance of the die stack structure can be improved. According to some embodiments, at least one connector interconnects a first test pad of the first semiconductor structure and a second test pad of the second semiconductor structure. The connector is proximate to a first probe mark of the first test pad and a second probe mark of the second test pad that is substantially aligned with the first probe mark in a vertical direction. Because there are multiple cover layers on both the first semiconductor structure and the second semiconductor structure, the overall mechanical durability of the semiconductor structures can be improved regardless of the proximity of the two probe marks and the proximity of the connector to the two probe marks. Therefore, in a die stacking process, design limitations caused by probe marks can be alleviated, and the overall yield and quality of the stacked die package can be improved.

[0102] Example semiconductor structures, die stack structures, and methods

[0103] Figures 1A to 1F FIG. is a schematic diagram showing a cross-sectional view of an intermediate stage of forming an example semiconductor structure 10F according to some embodiments. Figures 1A to 1F The operations shown in are also Figure 3 schematically illustrated in method 300 of. In the following discussion, reference is also made to Figure 3 the operations in to discuss Figures 1A to 1F the operations shown in.

[0104] As shown in the example of semiconductor structure 10A of Figure 1A a first die 100 is provided. The first die 100 serves as a substrate for the semiconductor structure 10A. For example, the first die 100 can be an application-specific integrated circuit (ASIC) wafer, an analog wafer, a sensor wafer, a wireless and radio frequency wafer, a voltage regulator wafer, or a memory wafer. The first die 100 includes a first semiconductor substrate 102, a first device region 103, a first interconnect structure 104, a first passivation layer 110, and a first test pad 112, among other components.

[0105] In some embodiments, the first semiconductor substrate 102 may comprise silicon or other semiconductor materials. Additionally or alternatively, the first semiconductor substrate 102 may comprise other elemental semiconductor materials such as germanium. In some embodiments, the first semiconductor substrate 102 is made of compound semiconductors such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, the first semiconductor substrate 102 is made of alloy semiconductors such as silicon germanium, silicon germanium carbide, gallium phosphoarsenide, or gallium indium phosphide. In some embodiments, the first semiconductor substrate 102 includes an epitaxial layer. For example, the first semiconductor substrate 102 has an epitaxial layer overlying a body semiconductor.

[0106] In some embodiments, the first device region 103 is formed on the first semiconductor substrate 102 in a front-end-of-line (FEOL) process. The first device region 103 includes a wide variety of devices. In some embodiments, the devices include active components, passive components, or combinations thereof. In some embodiments, the devices may include integrated circuit devices. These devices are, for example, transistors, capacitors, resistors, diodes, photodiodes, fuse devices, or other similar devices. In some embodiments, the first device region 103 includes gate structures, source / drain regions, and isolation structures such as shallow trench isolation (STI) structures (not shown). Figure 1A The first device region 103 shown is only an example, and other structures may be formed in the first device region 103. In the first device region 103, various N-type metal-oxide semiconductor (NMOS) and / or P-type metal-oxide semiconductor (PMOS) devices such as transistors or memories and the like may be formed and interconnected to perform one or more functions. Other devices such as capacitors, resistors, diodes, photodiodes, fuses, and the like may also be formed on the first semiconductor substrate 102. The functions of the devices may include memory, processor, sensor, amplifier, power distribution, input / output circuitry, or the like.

[0107] As Figure 1AAs shown, a first interconnect structure 104 is formed over a first semiconductor substrate 102. The first interconnect structure 104 includes a first insulating material 106 and a plurality of first metal features 108. The first metal features 108 are formed in the first insulating material 106 and are electrically connected to each other. A portion of the first metal features 108, such as top metal features 108a and 108b, is exposed by the first insulating material 106. In some embodiments, the first insulating material 106 includes an inner-layer dielectric (ILD) layer on the first semiconductor substrate 102, and at least one inter-metal dielectric (IMD) layer above the inner-layer dielectric layer. In some embodiments, the first insulating material 106 includes silicon oxide, silicon oxynitride, silicon nitride, a low dielectric constant (low-k) material, or a combination thereof. In some embodiments, the first insulating material 106 may be a single layer or multiple layers. In some embodiments, the first metal features 108 include sockets and metal lines. The sockets may include contacts formed in the ILD layer and vias formed in the inter-metal dielectric layer. The contacts are formed between the substrate 102 and the bottom metal line and are connected to both. The vias are formed between two metal lines and are connected to both. The first metal features 108 may be made of tungsten (W), copper (Cu), copper alloy, aluminum (Al), aluminum alloy, or a combination thereof. In some alternative embodiments, a barrier layer (not shown) may be formed between the first metal features 108 and the first insulating material 106 to prevent the material of the first metal features 108 from migrating to the first device region 103. The material of the barrier layer includes, for example, tantalum, tantalum nitride, titanium, titanium nitride, cobalt tungsten (CoW), or a combination thereof.

[0108] As Figure 1A As shown, a first passivation layer 110 is formed over the first interconnect structure 104. The first passivation layer 110 covers the first insulating material 106 and the top metal feature 108a. In addition, a portion of the top metal feature 108b is covered by the first passivation layer 110, and another portion of the top metal feature 108b is exposed by the first passivation layer 110, such that the other portion of the top metal feature 108b can be electrically connected to one or more first test pads 112 (e.g., first test pads 112a and 112b) to be formed. In some embodiments, the first passivation layer 110 includes silicon oxide, silicon nitride, benzocyclobutene (BCB) polymer, polyimide (PI), polybenzoxazole (PBO), or a combination thereof, and is formed by a suitable process such as spin coating, CVD, or the like.

[0109] As Figure 1AAs shown, a first test pad 112 is formed over the first passivation layer 110 and extends to cover the top metal feature 108b. The first test pad 112 has a top surface 113. In some embodiments, the material of the first test pad 112 is different from the material of the first metal feature 108. In some embodiments, the material of the first test pad 112 is softer than the material of the first metal feature 108. In some embodiments, the first test pad 112 comprises a metallic material such as aluminum, copper, nickel, gold, silver, tungsten, or a combination thereof. The first test pad 112 can be formed by depositing a layer of metallic material via a suitable process such as electroless plating, CVD, atomic layer deposition (ALD), physical vapor deposition (PVD), or the like, and then patterning the metallic material layer. In some embodiments, the first test pad 112 is in the form of an aluminum pad.

[0110] It should be noted that the first die 100 is a known good die (KGD). That is, the first test pad 112 of the first die 100 is subjected to die performance testing to identify or select known good dies. In some embodiments, the die performance testing is performed by using a die performance probe (not shown) inserted into at least one of the first test pads 112. As shown in region 114, after performing the die performance testing, a first probe mark 160 is formed at an upper portion of the first test pad 112a. In some embodiments, the first probe mark 160 can be formed over the first passivation layer 110, the top metal feature 108b, or a combination thereof.

[0111] The first probe mark 160 can have various shapes and cross-sectional geometries, including but not limited to triangular, square, rectangular, trapezoidal, etc. In Figure 1A an example, the first probe mark 160 has a concave profile and extends in the Z direction from an open end 161 that is located at and aligned with the top surface 113 of the first test pad 112a to a bottom wall 163. The probe mark 160 includes sidewalls 162 that are circumferentially connected to the bottom wall 163. In some embodiments, the angle α formed between the sidewalls 162 and the top surface 113 is 90 degrees to 120 degrees. In some embodiments, the bottom wall 163 has a minimum width or tapers to a point in the X direction such that the probe mark 160 has a triangular cross-sectional shape. The probe mark 160 can also be regarded as a space surrounded by the open end 161, the sidewalls 162, and the bottom wall 163. For convenience, in some embodiments of the present disclosure, the probe mark and the space of the probe mark can be used interchangeably.

[0112] The sidewall 162 and the top surface 113 may form a corner portion 164 that circumferentially surrounds the open end 161 of the first probe mark 160. In some embodiments, the corner portion 164 protrudes upward and is in an elevated position relative to the top surface 113. In some embodiments, a protruding portion (not shown) of the corner portion 164 may be formed due to the material displacement of the first test pad 112 during the formation of the probe mark 160. The protruding portion may have a shape of an elevated protrusion or an annular configuration surrounding the open end 161 of the probe mark 160.

[0113] The probe mark 160 has an opening width (W O ) in the X direction and a height (H) in the Z direction. The height (H) is characterized as the distance between the top surface 113 and the bottom wall 163. In some embodiments, the width (W O ) is from 10 micrometers (μm) to 20 micrometers, from 12 micrometers to 18 micrometers, from 14 micrometers to 16 micrometers, or from 12.5 micrometers to 15.5 micrometers. In some embodiments, the height (H) is from 0.2 micrometers to 1 micrometer, from 0.4 micrometers to 0.8 micrometer, or from 0.5 micrometers to 0.7 micrometer. In at least one embodiment, H is about 0.6 micrometers. The probe mark 160 may have various aspect ratios, characterized as the ratio of H to W O , depending on the probe used and the process for the performance test using the probe. In some embodiments, the probe mark 160 has an aspect ratio (H / W O ) of 0.001 to 1000, 0.05 to 500, 0.01 to 100, or 0.1 to 10.

[0114] As Figure 1BAs shown in the example of the semiconductor structure 10B, a first capping layer 121 is formed on the first test pad 112. In some embodiments, after the first die 100 is identified as a known good die, the first capping layer 121 is disposed over the top surface 113 of the first test pad 112 and the front side 100a of the first die 100 (i.e., the front side of the first passivation layer 110). The first capping layer 121 covers and contacts the first test pad 112 and the first passivation layer 110. The first capping layer 121 can be formed by a deposition technique such as CVD, ALD, physical vapor deposition (PVD). In some embodiments, the first capping layer 121 includes a dielectric material such as silicon oxide, silicon nitride, a polymer, or a combination thereof. In some embodiments, the first capping layer is a tetraethoxysilane (TEOS) oxide layer formed from tetraethoxysilane (TEOS). For example, TEOS can be deposited onto the top surface 113 of the first test pad 112 and the front side of the first die 100 using a CVD process. During the process, TEOS is mixed with oxygen and heated to an elevated temperature to react and form a layer of silicon dioxide on the top surface 113 of the first test pad 112 and the front side of the first die 100. The TEOS oxide layer can be used as a bonding layer between the first die 100 and additional layers to be formed on the first capping layer 121. The TEOS oxide layer can also be used as an insulator between the first die in the package structure and other dies to be stacked. The TEOS oxide layer can also be used as a protective layer to protect the first die 100.

[0115] The material of the first capping layer 121 can also partially fill the interior portion of the probe mark 160 in the first test pad 112a. As Figure 1A and Figure 1B shown in the enlarged view of the region 114, the first capping layer 121 is deposited on the top surface 113 of the first test pad 112a and the sidewall 162 and bottom wall 163 of the probe mark 160. The first capping layer 121 can fill the interior portion 160a (i.e., the first portion) of the probe mark 160 in the first test pad 112a. The interior portion 160a is directly connected to the sidewall 162 and bottom wall 163 of the probe mark 160. The interior portion 160a can be occupied by the first capping layer 121 formed on the sidewall 162 and bottom wall 163 of the probe mark 160.

[0116] In some embodiments, the first capping layer 121 can have a first thickness (T 1 ) on the top surface 113 of the first test pad 112a, a second thickness (T 2 ) on the bottom wall 163 of the probe mark 160, and a third thickness (T 3)。In some embodiments, the deposition rate of the first capping layer 121 on the top surface 113, sidewalls 162, and bottom wall 163 in the deposition process is the same or substantially the same. Thus, the first thickness T 1 , the second thickness T 2 , and the third thickness T 3 are the same or substantially the same. In some embodiments, the deposition rate of the first capping layer 121 on the sidewalls 162 and bottom wall 163 of the probe mark 160 in the deposition process is the same or substantially the same. As a result, the second thickness T 2 and the third thickness T 3 are the same or substantially the same. In some embodiments, the first thickness T 1 may be greater than the second thickness T 2 and the third thickness T 3 . In some embodiments, the second thickness T 2 and the third thickness T 3 are less than or substantially less than the height (H) of the probe mark 160. In some embodiments, the first thickness T 1 , the second thickness T 2 , and the third thickness T 3 are 0.1 micrometer to 1 micrometer, 0.2 micrometer to 0.8 micrometer, or 0.4 micrometer to 0.6 micrometer. In at least one embodiment, the second thickness T 2 and the third thickness T 3 are about 0.5 micrometer.

[0117] After the first capping layer 121 is formed, at least a portion of the probe mark 160 remains unfilled, and the remaining unfilled portion of the probe mark 160 is labeled as the outer portion 160b (i.e., the second portion) of the probe mark 160. The inner portion 160a and the outer portion 160b may be complementary. The outer portion 160b is spaced apart from the sidewalls 162 and bottom wall 163 of the probe mark 160 by the inner portion 160a. In some embodiments, the inner portion 160a filled with the first capping layer 121 has a total volume of at least 25%, at least 35%, at least 50%, at least 75%, or at least 95% based on the total volume of the probe mark 160. In some embodiments, the unfilled outer portion 160b has a volume of about 80% or less, about 65% or less, about 50% or less, about 35% or less, about 15% or less, or about 5% or less based on the total volume of the probe mark 160. In at least one embodiment, based on the total volume of the probe mark 160, the inner portion 160a has at least 35% of the volume, while the outer portion 160b has 65% or less of the volume. The volume ratio of the inner portion 160a to the outer portion 160b is at least 35 / 65. In at least one embodiment, the entire probe mark 160 is filled with the first capping layer 121.

[0118] In some embodiments, the material of the first capping layer 121 is a low-stress oxide film containing low-stress oxide (LSO). The low-stress oxide may have a stress level of 100 megapascals (MPa) to 200 MPa, 120 MPa to 180 MPa, or 135 MPa to 160 MPa. In at least one embodiment, the low-stress oxide may have a stress level of about 150 MPa. It should be noted that the stress level of the first capping layer 121 can be controlled, for example, by adjusting the film thickness, selecting an appropriate deposition method, tuning the deposition parameters, and / or performing post-treatment.

[0119] As Figure 1C shown in the example of the semiconductor structure 10C of 4 , a second capping layer 122 is formed on the first capping layer 121. The second capping layer 122 is deposited on the front surface 121a of the first capping layer 121 and fills the outer portion 160b of the probe mark 160. The second capping layer 122 can be formed by deposition techniques such as CVD (chemical vapor deposition, CVD), ALD, plasma-enhanced CVD (PECVD), and PVD. In some embodiments, the second capping layer 122 includes a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, a polymer, or a combination thereof. In some embodiments, the second capping layer 122 is a liner oxide layer. The liner oxide layer can be formed by depositing silicon dioxide on the first capping layer 121 using a CVD process. The second capping layer 122 may have a front surface 122a and a thickness (T 4 ), and the thickness is measured by the distance in the Z direction from the front surface 121a of the first capping layer 121 to the front surface 122a of the second capping layer 122. In some embodiments, the thickness T 4 is 0.1 micrometer to 5 micrometers, 0.2 micrometer to 4 micrometers, 0.4 micrometer to 3 micrometers, or 0.5 micrometer to 2 micrometers. In some embodiments, the thickness T 4 is greater than the first thickness T 1 . In some embodiments, the ratio of the thickness T 4 to the first thickness T 1 (T 4 / T 1 ) is at least 2, at least 3, or at least 4. In at least one embodiment, the thickness T 4 / the first thickness T 1 is at least 2.4.

[0120] After filling the outer portion 160b of the probe mark 160 with the second capping layer 122, a protruding structure 165 may be formed. The protruding structure 165 protrudes vertically from a first end 166 horizontally aligned with the front surface 121a to a second end 167 in the probe mark 160. The second end 167 is aligned with the surface of the first capping layer 121 filled in the inner portion 160a of the probe mark 160. The protruding structure 165 has a bottom width (W P ). In some embodiments, W P is less than W O , and is 12 microns to 18 microns, 13 microns to 17 microns, 13.5 microns to 15.5 microns, or 14 microns to 15 microns. A portion of the protruding structure 165 (e.g., from the top surface 113 of the first test pad 112a to the second end 167) is filled in the outer portion 160b of the probe mark 160. The protruding structure 165 may have a profile substantially similar to the profile of the probe mark 160. For example, if the probe mark 160 has a triangular cross-sectional shape, the protruding structure 165 may similarly have a triangular cross-sectional shape. The protruding structure 165 is made of the same material as the second capping layer 122. In some embodiments, if the probe mark 160 is completely or substantially filled with the first capping layer 121, the protruding structure 165 may not extend into the probe mark 160.

[0121] In some embodiments, the second capping layer 122 is a high-stress oxide film and includes high-stress oxide (HSO) material. In at least one embodiment, the second capping layer 122 has a greater stress level compared to the first capping layer 121. The high-stress oxide material may have a stress level of at least 150 MPa, at least 175 MPa, or at least 200 MPa. In some embodiments, the high-stress oxide material may have a stress level of 150 MPa to 400 MPa, 175 MPa to 300 MPa, or 180 MPa to 220 MPa. In at least some embodiments, the first capping layer 121 has a first stress level, the second capping layer 122 has a second stress level, and the second stress level is at least 15 MPa, at least 35 MPa, at least 50 MPa, or at least 70 MPa higher than the first stress level.

[0122] After the second cover layer 122 is formed, the probe mark 160 is filled with a first structure (i.e., a low stress material) from the first cover layer 121 in the inner portion 160a and a second structure (i.e., a high stress material) from the second cover layer 122 in the outer portion 160b. In some embodiments, the inner portion 160a filled with the first structure has a total volume of at least 25%, at least 35%, at least 50%, at least 75%, or at least 95% based on the total volume of the probe mark 160. In some embodiments, the outer portion 160b filled with the second structure has a volume of about 80% or less, about 65% or less, about 50% or less, about 35% or less, about 15% or less, or about 5% or less based on the total volume of the probe mark 160. In at least one embodiment, based on the total volume of the probe mark 160, the inner portion 160a filled with the first structure has a volume of at least 35%, and the outer portion 160b filled with the second structure has a volume of 65% or less. The first cover layer 121 can be used as both a bonding layer and a buffer layer between the first test pad 112a and the second cover layer 122 due to its relatively low stress level, thereby improving the compatibility and bonding strength between the first cover layer 121 and the second cover layer 122, reducing voids, cracks, and damage formed near the probe mark 160 and / or caused by the probe mark 160 in the first cover layer 121 and the second cover layer 122, reducing the risk of seams or delamination between the first cover layer 121 and the second cover layer 122, and improving the overall mechanical durability of the first die 100 in the die stack to be formed.

[0123] As Figure 1D shown in an example of the semiconductor structure 10D of, a third cover layer 123 is formed on the second cover layer 122. The third cover layer 123 is deposited on the front surface 122a of the second cover layer 122. The third cover layer 122 can be formed by deposition techniques such as spin coating, CVD, ALD, or PVD, followed by a planarization process on the third cover layer 123. In some embodiments, the planarization process includes a chemical-mechanical polishing (CMP) process, an etch-back process, or a combination thereof. In some embodiments, the third cover layer 123 includes a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, a polymer, or a combination thereof. In some embodiments, the third cover layer 123 includes a low stress material such as LSO. In some embodiments, the third cover layer 123 includes the same or substantially the same material as the material of the first cover layer 121. The third cover layer 123 can be used as a bonding layer with another die in subsequent die stack processes. The third cover layer 123 can also be used as a barrier layer that evenly covers the second cover layer 122 and further protects the first die 100.

[0124] The third cover layer 123 may have a front surface 123a and a thickness (T 5 ), and the thickness is measured by the distance between the front surface 122a of the first cover layer 122 and the front surface 123a of the third cover layer 123 in the Z direction. In some embodiments, the thickness T 5 is from 0.1 micrometer to 1 micrometer, from 0.2 micrometer to 0.8 micrometer, or from 0.4 micrometer to 0.6 micrometer. In at least one embodiment, the second thickness T 2 and the third thickness T 3 are about 0.5 micrometer. In some embodiments, the thickness T 5 is the same as or substantially the same as the first thickness T 1 . In some embodiments, the thickness T 4 is greater than the thickness T 5 . In some embodiments, the ratio of the thickness T 4 to the thickness T 5 (T 4 / T 5 ) is at least 2, at least 3, or at least 4. In at least one embodiment, T 4 / T 5 is at least 2.4.

[0125] As shown in the example of the semiconductor structure 10E of Figure 1E , one or more openings 117 (e.g., a first opening 117a and a second opening 117b) are formed. Each of the openings 117 is used to receive and accommodate a conductive element for connecting to another die in a subsequent die stacking process. In some embodiments, one or more bonding layers 124 may be formed on the third cover layer 123 before forming the openings 117. The additional bonding layers 124 can be used to facilitate or enhance the bonding and adhesion strength between the first die 100 and another die 100 to be bonded to the first die. It should be noted that the bonding layer 124 is optional. In some embodiments, no additional bonding layer is formed on the third cover layer 123 before die bonding or stacking. In some embodiments, the openings 117a and 117b may extend from the front surface of the bonding layer 124 to the first test pads 112a and 112b, respectively. The openings 117 can be formed by a patterning and etching process, and the position, shape, and dimensions of the openings can be controlled by adjusting parameters according to design requirements. For example, the opening 117a may be located above the probe mark 160 (i.e., aligned or substantially aligned with the probe mark 160).

[0126] In some embodiments, at least one opening 117 (e.g., opening 117a) is adjacent to the probe mark 160 of the first test pad 112a. As described above, the multiple overlay layers 121 and 122 having a combination of low-stress oxide and high-stress oxide filled in the probe mark 160 of the first test pad 112a can effectively reduce the risk of voids, cracks, damage, seams, and delamination of the overlay layer caused by the probe mark 160. In other words, when selecting the location of the opening for the connector in the die bonding and stacking process, the probe mark may not be restricted by the design.

[0127] As Figure 1F shown in the example of the semiconductor structure 10F of, one or more connectors 181 are formed. The connectors 181 (e.g., connectors 181a and 181b) may be composed of conductive elements, for example, C4 bumps or micro-bumps. In some embodiments, the connector 181 may include a conductive component connecting to a metal bonding pad of a metal contact. The metal bonding pad may be connected to the metal bonding pad of another die to be stacked on the first die via a metal-to-metal bonding, a fusion bonding, or a hybrid bonding. The metal contact may interconnect the metal pad of the conductive component to the first test pad 112a of the first die 100. Within the scope of some embodiments of the present disclosure, other types of conductive elements are also possible. The semiconductor structure 10F can be used to bond the first die 100 to another die in a die stacking process to form a die stack structure (e.g., Figure 2B the die stack structure 200B).

[0128] Figures 2A to 2C is a cross-sectional view of a method for forming a die stack structure according to some embodiments. Figures 2A to 2C The operations shown in are also schematically illustrated in Figure 3 the method 300 of. In the following discussion, reference is also made to Figure 3 the operations in to discuss Figures 2A to 2C the operations shown in.

[0129] As Figure 2A shown in the example of the die stack structure 200A to be formed of, a first semiconductor structure 10 and a second semiconductor structure 20 are provided. The first semiconductor structure 10 is based on and includes a first die 100, and the second semiconductor structure 20 is based on and includes a second die 200. The first semiconductor structure 10 is similar to Figures 1A to 1FThe exemplary semiconductor structure shown. For example, the second die 200 may be an application-specific integrated circuit (ASIC) wafer, an analog wafer, a sensor wafer, a wireless and radio frequency wafer, a voltage regulator wafer, or a memory wafer. The second die 200 and the first die 100 may be the same type of die or different types of dies. In some embodiments, the second die 200 may be an active component or a passive component.

[0130] In some embodiments, the second semiconductor structure 20 is similar to the first semiconductor structure 10. That is, the second semiconductor 200 includes a second semiconductor substrate 202, a second device region 203, a second interconnect structure 204 (including a first insulating material 206 and a plurality of first metal features 208), a second passivation layer 210, and one or more second test pads 212. Similar to the first die 100, at least one of the second test pads 212 (e.g., the second test pad 212a) includes a probe mark 260 in its upper portion. The configuration, materials, and formation method of the second die 200 are similar to those of the first die 100. Therefore, the details thereof are omitted herein. The difference therebetween is that the size of the second die 200 is larger than the size of the first die 100. Here, the term "size" refers to length, width, or area. For example, as Figure 2A shown, the length of the second die 200 is greater than the length of the first die 100. For convenience, the probe mark 160 of the first semiconductor structure 10 is labeled as the first probe mark, and the probe mark 260 of the second semiconductor structure 20 is labeled as the second probe mark.

[0131] Similar to the first semiconductor structure 10, the second semiconductor structure 20 may be formed by sequentially forming a plurality of overlying layers 221, 222, and 223 on the front side of the second die 200. Thus, the second probe mark 260 is similarly filled with a first structure derived from the first overlying layer 221 in the inner portion and a second structure derived from the second overlying layer 222 in the outer portion. Similar to the first die 100, the first structure filled in the inner portion of the second probe mark 260 may be a low-stress oxide, and the second structure filled in the outer portion of the second probe mark 260 may be a high-stress oxide.

[0132] It should be noted that the bonding layer 124 of the first semiconductor structure 10 and the bonding layer 224 of the second semiconductor structure 20 are optional. In some embodiments, no additional bonding layer is formed on the third overlying layer 123 of the first semiconductor structure 10 and the third overlying layer 223 of the second semiconductor structure 20. The third overlying layers 123 and 223 may be directly used as bonding layers to bond the first die 100 and the second die 200 together in a die stacking process.

[0133] In Figure 2A the example of, the first semiconductor structure 10 further includes a plurality of connectors 181 (e.g., connectors 181a, 181b, 181c, 181d, and 181e), which are disposed on the front side (F) of the first semiconductor structure 10. As described above, the connectors can be formed by forming corresponding openings on the front side, depositing conductive elements in the openings, and then performing a polarization process to polarize the surface. At least one connector 181 (e.g., connectors 181a, 181b, and 181c) is proximate to the first probe mark 160, and at least one connector 181 (e.g., connector 181c) extends through the bonding layer 124 and the plurality of overlying layers 121, 122, and 123 and contacts the first test pad 112a. Similarly, the second semiconductor structure 20 further includes a plurality of connectors 281 (e.g., connectors 281a, 281b, 281c, 281d, 281e, and 281f) disposed on the front side (F') of the second semiconductor structure 20. At least one connector 281 (e.g., connector 281c) is proximate to the second probe mark 260, extends through the bonding layer 224 and the plurality of overlying layers 221, 222, and 223, and contacts the second test pad 212a. The connectors 281a, 281b, 281c, 281d, 281e of the second semiconductor structure 20 respectively correspond to the connectors 181a, 181b, 181c, 181d, and 181e of the first semiconductor structure 10. It should be noted that Figure 2A the example shown in is not intended to be restrictive, and the number, size, shape, and position of the connectors may vary according to design requirements.

[0134] As Figures 2A to 2BAs shown, the first semiconductor structure 10 and the second semiconductor structure 20 are joined face-to-face to form a die stack structure 200B. For example, the first semiconductor structure 10 is inverted and mounted on the second semiconductor structure 20. Specifically, the front side (F) of the first semiconductor structure 10 and the front side (F') of the second semiconductor structure 20 are joined together at the bonding interface 182, and a bonding region 190 is formed across the bonding interface 182. The bonding interface 182 can be formed by the attachment and combination of the bonding layer 124 of the first semiconductor structure 10 and the bonding layer 224 of the second semiconductor structure 20. In some embodiments, if the first semiconductor structure 10 and the second semiconductor structure 20 do not include the bonding layers 124 and 224, the bonding interface 182 is formed by the attachment and combination of a part of each of the third cover layers 123 and 223. In some embodiments, at least a part of the respective cover layers of the first semiconductor structure and the second semiconductor structure (i.e., at least a part of the first cover layers 121 and 221, at least a part of the second cover layers 122 and 222, and / or at least a part of the third cover layers 123 and 223) is included in the bonding region 190 and contributes to the bonding between the first semiconductor structure 10 and the second semiconductor structure 20.

[0135] In some embodiments, before the first semiconductor structure 10 is bonded to the second semiconductor structure 20, a plurality of connectors 181 and 281 are aligned in the Z direction such that a plurality of pairs of connectors (e.g., connector 181a and 281a, connector 181b and 281b, connector 181c and 281c, connector 181d and 281d, and connector 181e and 281e) are formed face-to-face. In some embodiments, the alignment of the plurality of connectors 181 and 281 can be achieved by using an optical sensing method. After the alignment is achieved, the first semiconductor structure 10 and the second semiconductor structure 20 are bonded together. As a result, a plurality of bonding structures 185 (e.g., bonding structures 185a, 185b, 185c, 185d, and 185e) are formed corresponding to the coupling of the connector pair 181a and 281a, the coupling of the connector pair 181b and 281b, the coupling of the connector pair 181c and 281c, the coupling of the connector pair 181d and 281d, and the coupling of the connector pair 181e and 281e. It should be noted that at least one bonding structure 185 (e.g., bonding structure 185c) extends vertically through the bonding region 190 and interconnects the first test pad 112a of the first die 100 and the second test pad 212a of the second die 200.

[0136] In some embodiments, the bond between the first semiconductor structure 10 and the second semiconductor structure 20 of the die stack structure 200B is formed by a hybrid bond that applies a combination of pressure and heat. It should be noted that a hybrid bond involves at least two types of bonds, including metal-to-metal bonding and non-metal-to-non-metal bonding, such as dielectric-to-dielectric bonding or fusion bonding. As Figures 2A to 2B shown in the example, the bonding structure 185 is formed by metal-to-metal bonding, and the bonding layer 124 of the first semiconductor structure 10 and the bonding layer 224 of the second semiconductor structure 20 are bonded by non-metal-to-non-metal bonding.

[0137] It should be noted that the first probe mark 160 and the second probe mark 260 can be vertically aligned and close to each other, and the bonding structure 185c is close to the first probe mark 160 and the second probe mark 260. Regardless of the proximity, due at least in part to the multiple overlayers filled in both the first probe mark 160 and the second probe mark 260, the risk of voids and cracks caused by the probe marks 160 and 260 is significantly reduced. As a result, the mechanical durability, reliability, and performance of the die stack structure 200B can be correspondingly improved.

[0138] As Figure 2C shown, an insulating package 128 is formed beside the first die 100. In some embodiments, the material of the insulating package 128 includes a molding compound. The molding compound may include a resin and a filler. In some alternative embodiments, the material of the insulating package 128 includes an oxide or a nitride, such as silicon oxide, silicon nitride, or a combination thereof. The insulating package 128 can be formed by spin coating, lamination, deposition, or the like. For example, the insulating package 128 can be formed by first forming a packaging material (not shown) over the first die 100 and covering the first die 100. Thereafter, the sealant material over the first die 100 is removed by a planarization process such as a CMP process. In some embodiments, a portion of the packaging material is removed such that the back side of the first die 100 is exposed after the planarization process. Thus, the back side of the first die 100 and the top surface of the insulating package 128 are substantially planar.

[0139] After forming the insulating package 128, at least one first through-substrate via (TSV) 130 is formed. The TSV 130 penetrates the first semiconductor substrate 102 and is electrically connected to the first metal feature 108 of the first interconnect structure 104. The TSV 130 is used to provide an electrical connection between the first die 100 and the redistribution circuit structure 140 to be formed. In some embodiments, the TSV 130 includes a conductive via. The conductive via is made of copper, copper alloy, aluminum, aluminum alloy, or a combination thereof. In some other embodiments, the TSV 130 further includes a diffusion barrier layer (not shown) surrounding the conductive via. The diffusion barrier layer is made of Ta, TaN, Ti, TiN, CoW, or a combination thereof and can be formed by a suitable process such as an electroless plating process, CVD, ALD, PVD, or the like.

[0140] At least one through dielectric via (TDV) 132 is formed in the insulating package 128 to be electrically connected to the second interconnect structure 204 and the redistribution circuit structure 140 to be formed. In some embodiments, the TDV 132 includes a conductive via. The conductive via is made of copper, copper alloy, aluminum, aluminum alloy, or a combination thereof. In some other embodiments, the TDV 132 further includes a diffusion barrier layer (not shown) surrounding the conductive via. The diffusion barrier layer is made of Ta, TaN, Ti, TiN, CoW, or a combination thereof and can be formed by a suitable process such as an electroless plating process, CVD, ALD, PVD, or the like.

[0141] After forming the TSV 130 and the TDV 132, a redistribution circuit structure 140 is formed over the rear side of the first die 100 and above the insulating package 128. The redistribution circuit structure 140 includes a plurality of dielectric layers 140a and a plurality of redistribution conductive layers 140b stacked alternately. A part of the redistribution conductive layer 140b is electrically connected to the TSV 130. Another part of the redistribution conductive layer 140b is electrically connected to the TDV 132. In addition, the topmost redistribution conductive layer 140b includes at least one pad. In some embodiments, the above-mentioned pads include a plurality of bonding pads 140b1 for mounting bumps of conductive connectors (e.g., metal pillars, micro-bumps, or a combination thereof), and / or at least one test pad 140b2 for performing backside die performance testing. The number of the bonding pads 140b1 and the test pads 140b2 is not limited in some embodiments of the present disclosure. The material of the bonding pads 140b1 includes metal or metal alloy. The bonding pads 140b1 are, for example, aluminum, copper, nickel, or an alloy thereof. The material of the test pads 140b2 may be the same as or different from the materials of the first test pad 112 and the second test pad 212. In some embodiments, the test pads 140b2 include a metal material, such as aluminum, copper, nickel, gold, silver, tungsten, or a combination thereof.

[0142] After forming a passivation layer 150 over the redistribution circuit structure 140 and partially covering the bonding pads 140b1 and the test pads 140b2, the die stack structure 200C is achieved. The passivation layer 150 includes silicon oxide, silicon nitride, benzocyclobutene (BCB) polymer, polyimide (PI), polybenzoxazole (PBO), or a combination thereof, and is formed by a suitable process such as spin coating, CVD, or the like.

[0143] The die stack structure 200C can be further processed to form a package. For example, a singulation process can be performed to cut the die stack structure into individual wafers. The individual wafers can be mounted onto a substrate, which serves as the basis for the finished package. The substrate can be made of a variety of materials such as ceramic or plastic, depending on the specific requirements of the device. Once the wafers are attached to the substrate, the individual wafers are connected together using wires or other interconnects and are connected via wire bonding to other components of the substrate. The entire package can be enclosed in a protective material such as epoxy resin or plastic to protect the delicate components from damage and environmental factors (such as moisture or dust). The finished package can be tested to ensure that all components are working correctly and that the package meets the required specifications.

[0144] Figure 3 FIG. is a flowchart illustrating an example method 300 for manufacturing a semiconductor structure and a die stack structure according to some embodiments. Cross-sectional views of the semiconductor structure and the die stack structure at various manufacturing stages are as Figures 1A to 1F AndFigures 2A to 2C The details of the semiconductor structure and the die stacking structure formed at various manufacturing stages have been described above and will not be repeated unless otherwise specified.

[0145] exist Figure 3 In the illustrated example of , method 300 includes operations 302, 304, 306, 308, 310, 312, and 314. Additional operations may be performed. In addition, it should be understood that the above reference Figure 3 The sequences of various operations discussed are provided for illustrative purposes, and therefore, other embodiments may utilize different sequences. These different sequences of operations will be included within the scope of the embodiments.

[0146] At 302, a first cover layer is formed on a first test pad of a first die. The first test pad is disposed on a front side of the first die and has a first probe mark in an upper portion of the first test pad. At least a portion (e.g., an inner portion) of the probe mark is filled with a material of the first cover layer. After forming the first cover layer, at least a portion (i.e., an outer portion) of the probe mark may remain unfilled. The first cover layer may be composed of a low stress material such as a low stress oxide. At 304, a second cover layer is formed on the first cover layer. The second cover layer fills the unfilled portion of the probe mark. The second cover layer may include a high stress material such as a high stress oxide. In at least one embodiment, a volume ratio (V / V) of the first cover layer to the second cover layer in the probe mark is at least 35:65. At 306, a third cover layer is formed on the second cover layer. The third cover layer may include the same material as the first cover layer. The third cover layer may be a bonding layer for forming a bonding interface with another die to be stacked to the first die. One or more additional layers may be formed on the third cover layer. In some embodiments, before the die bonding and stacking process, only three cover layers are formed on the first test pad, and no bonding layer is formed on the third cover layer.

[0147] At 308, a die stacking process is performed to bond the first die to another wafer. In some embodiments, operation 308 further includes operations 310, 312, and 314. At 310, an opening is formed on the top of the first test pad. The opening is adjacent to the first probe mark and extends vertically through the cover layers 123, 122, and 121 to expose the top surface of the first test pad. The opening is used to receive and accommodate a connection element (connector). In some embodiments, a plurality of openings are formed.

[0148] At 312, a connector is disposed in the opening. The connector can be a conductive element of a connector for bonding to another die or wafer. In some embodiments, the connector is a metal pad for forming a metal-to-metal bond with a metal pad of another die or wafer. In some embodiments, the connector is a C4 bump or a micro-bump for bonding to another die or wafer. In some embodiments, a plurality of connectors are respectively disposed in a plurality of openings.

[0149] At 314, a first die is bonded to another die or wafer. In some embodiments, the die or wafer to be bonded to the first die is a second die similar to the first die. In some embodiments, the second die includes a second test pad. The second test pad includes a second probe mark filled with a first structure from a first overcoat formed on the second test pad and a second structure from a second overcoat formed on the first test pad. Similar to the first die, the second die may also have a connector disposed in an opening adjacent to the second probe mark. The connector is formed on the front side of the second die and contacts the second test pad. The first die and the second die can be aligned such that the connectors of the first and second dies are vertically aligned before die stacking. When two connectors from the first die and the second die are bonded via a metal-to-metal bond, a bonding structure is formed, and the bonding structure interconnecting the first test pad and the second test pad is adjacent to both the first and second probe marks. In some embodiments, the first and second dies are bonded together via hybrid bonding.

[0150] Summary

[0151] According to some aspects of the present disclosure, a semiconductor structure is provided. In one example, the semiconductor structure includes a die. The die has a test pad disposed on a front side of the die. The test pad has a probe mark in an upper portion of the test pad, the probe mark having an opening end at a top surface of the test pad, a bottom wall, sidewalls connected to the bottom wall, and a space between the opening end, the bottom wall, and the sidewalls. The semiconductor structure further includes a first overcoat disposed on a front side of the test pad and in the space, and on the sidewalls and the bottom wall of the probe mark. The first overcoat fills a portion of the space and includes a first structure. The semiconductor structure further includes a second overcoat disposed on the first overcoat and in the space. The second overcoat fills a second portion of the space and includes a second structure different from the first structure. In some embodiments, the semiconductor structure further includes a third overcoat disposed on the second overcoat. In some embodiments, the third overcoat includes a third structure having a stress level less than a stress level of the second structure.

[0152] In some embodiments, a first capping layer fills a first portion of the space of the probe mark, a second capping layer fills a second portion of the space of the probe mark, the first portion is connected to the sidewall and the bottom wall of the probe mark, and the second portion is complementary to the first portion.

[0153] In some embodiments, based on the total volume of the space of the probe mark, the first portion has at least 35% of the volume, and the second portion has at most 65% of the volume. In some embodiments, the first portion and the second portion of the space are complementary.

[0154] In some embodiments, a first structure has a first stress level, and a second structure has a second stress level higher than the first stress level. In some embodiments, the first stress level is from 130 MPa to 160 MPa, and the second stress level is from 170 MPa to 230 MPa.

[0155] In some embodiments, based on the total volume of the space of the probe mark, the first portion has at least 35% of the volume, and the second portion has at most 65% of the volume.

[0156] In some embodiments, the probe mark has a width and a height, wherein the width measured by the horizontal dimension at the opening end is from 12 microns to 16 microns, and the height measured by the vertical distance from the opening end to the bottom wall is from 0.5 microns to 0.8 microns.

[0157] In some embodiments, the first capping layer has a first thickness, and the second capping layer has a second thickness greater than the first thickness. In some embodiments, the first thickness is from 0.3 microns to 0.7 microns.

[0158] In some embodiments, the semiconductor structure further includes a bonding layer disposed on the third capping layer, and the bonding layer is used to form a bonding interface with another die to be stacked on the die.

[0159] In some embodiments, the semiconductor structure further includes a connector that contacts the test pad and extends through the first and second capping layers, and the connector is adjacent to the probe mark and is used to connect to another die.

[0160] In some embodiments, the connector is used to connect to another test pad in another die.

[0161] In some embodiments, the connector is a microbump.

[0162] According to some aspects of the present disclosure, a stacked die structure is provided. In one example, the stacked die structure includes a first semiconductor structure and a second semiconductor structure bonded together face-to-face at a bonding interface. The first semiconductor structure includes a first die having a first metal pad disposed on a front side of the first die. The first metal pad is a first test pad having a first probe mark in an upper portion of the first test pad. The first probe mark has an open end, a bottom wall, side walls connected to the bottom wall, and a space between the open end, the bottom wall, and the side walls at a top surface of the first test pad. The first semiconductor structure further includes a first capping layer, a second capping layer, and a third capping layer sequentially formed on the front side of the first test pad in a vertical direction. The first capping layer is disposed on the side walls and the bottom wall of the probe mark. The first capping layer fills a first portion of the space and includes a first structure. The first capping layer is disposed on the front side of the first test pad and in the space. The second capping layer is disposed on the first capping layer and in the space, fills a second portion of the space, and includes a second structure different from the first structure. The third capping layer is disposed on the second capping layer. The second semiconductor structure includes a second die having a second metal pad disposed on a front side of the second die. The second semiconductor structure further includes at least one capping layer disposed on a second test pad. The stacked die structure further includes at least one bonding structure connecting the first metal pad and the second metal pad. The at least one bonding structure extends vertically through the first, second, and third capping layers of the first semiconductor structure, the bonding interface, and the at least one capping layer of the second semiconductor structure. The bonding structure is proximate to the first probe mark.

[0163] In some embodiments, the second metal pad is a second test pad having a second probe mark in an upper portion of the second test pad, wherein the bonding structure is proximate to the second probe mark; and the at least one capping layer of the second semiconductor structure further includes: a fourth capping layer disposed on the front side of the second test pad, wherein the fourth capping layer includes the first structure; a fifth capping layer disposed on the fourth capping layer, wherein the fifth capping layer includes the second structure; and a sixth capping layer disposed on the fifth capping layer, the sixth capping layer being bonded to the third capping layer at the bonding interface.

[0164] In some embodiments, the first capping layer fills a first portion of the space of the first probe mark, the second capping layer fills a second portion of the space of the first probe mark, the first portion is connected to the side walls and the bottom wall of the first probe mark, and the second portion is complementary to the first portion; and the fourth capping layer fills a third portion of the space of the second probe mark, the fifth capping layer fills a fourth portion of the space of the second probe mark, the third portion is connected to the side walls and the bottom wall of the second probe mark, and the fourth portion is complementary to the third portion.

[0165] In some embodiments, the first structure has a low-stress oxide with a first stress level of 130 megapascals to 160 megapascals, and the second structure has a high-stress oxide with a second stress level of 170 megapascals to 230 megapascals.

[0166] According to some aspects of the present disclosure, a method of fabricating a semiconductor structure is provided. In one example, the method includes providing a die. The die has a test pad disposed on a front side, and the test pad has a probe mark in an upper portion of the test pad. The probe mark has an open end at a top surface of the test pad, a bottom wall, sidewalls connected to the bottom wall, and a space between the open end, the bottom wall, and the sidewalls. The method further includes forming a first capping layer on the front side of the first test pad and in the space, and on the sidewalls and the bottom wall of the probe mark, such that the first capping layer fills a first portion of the space and leaves a second portion of the space unfilled. The first capping layer is disposed on the sidewalls and the bottom wall of the probe mark and includes a first structure having a first stress level. The method further includes forming a second capping layer on the first capping layer such that the second capping layer fills the second portion of the space. The second capping layer includes a second structure having a second stress level higher than the first stress level. In some embodiments, the method further includes forming a third capping layer on the second capping layer. The third capping layer is a bonding layer and includes a third structure having a third stress level less than the second stress level.

[0167] According to some aspects of the present disclosure, a semiconductor structure is provided, comprising a die, a first capping layer, and a second capping layer. The die has a test pad disposed on a front side of the die, wherein the test pad has a probe mark in an upper portion of the test pad. The first capping layer is disposed on the front side of the test pad and in the space, and on the sidewalls and the bottom wall of the probe mark, and the first capping layer includes a first structure. The second capping layer is disposed on the first capping layer and in the space, wherein the second capping layer includes a second structure different from the first structure. The first capping layer has a first thickness, and the second capping layer has a second thickness greater than the first thickness.

[0168] The foregoing outlines the features of several embodiments such that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for the same purposes and / or achieving the same advantages as those introduced herein. Those skilled in the art should also recognize that such equivalent constructs do not depart from the spirit and scope of the present disclosure, and that such equivalent constructs may be made herein in various changes, substitutions, and alterations without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: Include: a die having a test pad disposed on a front side of the die, wherein the test pad has a probe mark in an upper portion of the test pad, the probe mark having an open end at a top surface of the test pad, a bottom wall, a side wall connected to the bottom wall, and a space between the open end, the bottom wall, and the side wall; a first covering layer disposed on the front side of the test pad and in the space, and on the side wall and the bottom wall of the probe mark, and the first covering layer includes a first structure; and A second covering layer is disposed on the first covering layer and in the space, wherein the second covering layer includes a second structure different from the first structure.

2. The semiconductor structure according to claim 1, wherein: The first covering layer fills a first part of the space of the probe mark, the second covering layer fills a second part of the space of the probe mark, the first part is connected to the side wall and the bottom wall of the probe mark, and the second part is complementary to the first part.

3. The semiconductor structure according to claim 2, wherein: Wherein, based on a total volume of the space labeled by the probe, the first portion has a volume of at least 35%, and the second portion has a volume of at most 65%.

4. The semiconductor structure according to claim 1, wherein: The probe mark has a width and a height, wherein the width measured by a horizontal dimension of the opening end is 12 microns to 16 microns, and the height measured by a vertical distance from the opening end to the bottom wall is 0.5 microns to 0.8 microns.

5. The semiconductor structure according to claim 1, wherein: The first covering layer has a first thickness, and the second covering layer has a second thickness greater than the first thickness.

6. The semiconductor structure according to claim 1, wherein: The invention further comprises a third covering layer disposed on the second covering layer.

7. A grain stacking structure, characterized in that: Include: A first semiconductor structure and a second semiconductor structure are bonded together in a face-to-face manner at a bonding interface, wherein the first semiconductor structure comprises: a first die having a first metal pad disposed on a front side of the first die, wherein the first metal pad is a first test pad having a first probe mark in an upper portion of the first test pad, the first probe mark having an open end at a top surface of the first test pad, a bottom wall, a side wall connected to the bottom wall, and a space between the open end, the bottom wall, and the side wall; a first covering layer disposed on the front side of the first test pad and in the space, and The probe marks the side wall and the bottom wall, and the first covering layer includes a first structure; a second covering layer disposed on the first covering layer and in the space, wherein the second covering layer comprises a second structure different from the first structure; and a third covering layer, disposed on the second covering layer; The second semiconductor structure comprises: a second die having a second metal pad disposed on a front side of the second die; and At least one covering layer is disposed on the second metal liner; and At least one bonding structure connects the first metal pad and the second metal pad, wherein the at least one bonding structure vertically extends through the first, second, and third covering layers of the first semiconductor structure, the bonding interface, the third covering layer, and the at least one covering layer of the second semiconductor structure, and the at least one bonding structure is close to the first probe mark.

8. The die stacking structure according to claim 7, wherein: in, The second metal pad is a second test pad having a second probe mark in an upper portion of the second test pad, wherein the bonding structure is proximate to the second probe mark; and The at least one capping layer of the second semiconductor structure further comprises: a fourth cover layer disposed on the front side of the second test pad, wherein the fourth cover layer includes the first structure; a fifth covering layer disposed on the fourth covering layer, wherein the fifth covering layer comprises the second structure; and A sixth covering layer is disposed on the fifth covering layer, and the sixth covering layer is bonded to the third covering layer at the bonding interface.

9. The die stacking structure according to claim 8, wherein: in, The first covering layer fills a first portion of the space of the first probe mark, and the second covering layer fills a second portion of the space of the first probe mark, the first portion is connected to the side wall and the bottom wall of the first probe mark, and the second portion is complementary to the first portion; and The fourth covering layer fills a third portion of the space of the second probe mark, and the fifth covering layer fills a fourth portion of the space of the second probe mark. The third portion is connected to a side wall and a bottom wall of the second probe mark, and the fourth portion is complementary to the third portion.

10. A semiconductor structure, characterized in that: Include: a die having a test pad disposed on a front side of the die, wherein the test pad has a probe mark in an upper portion of the test pad; a first covering layer disposed on the front side and in a space of the test pad, and on a side wall and a bottom wall of the probe mark, and the first covering layer includes a first structure; and a second covering layer, disposed on the first covering layer and in the space, wherein the second covering layer comprises a second structure different from the first structure, The first covering layer has a first thickness, and the second covering layer has a second thickness greater than the first thickness.

Images