DDR voltage temperature 4-corner test Vref voltage bias circuit

Abstract

The utility model provides a DDR voltage temperature 4-corner test Vref voltage bias circuit, comprising a first voltage bias module and a second voltage bias module which are connected with a DDRVREFCA circuit module, the first voltage bias module and the second voltage bias module are both connected with a main control chip, the first voltage bias module comprises a first field effect transistor, the second voltage bias module comprises a second field effect transistor, and the first field effect transistor comprises a second field effect transistor. The first voltage bias module comprises a first field effect transistor, the second voltage bias module comprises a second field effect transistor, the first field effect transistor and the second field effect transistor are both controlled by the main control chip, and voltage division adjustment is carried out on the DDRVREFCA circuit module by controlling conduction and non-conduction of the first field effect transistor or the second field effect transistor; compared with the prior art, the DDRVREFCA circuit module has the following beneficial effects that the switch-on and switch-off of the first field effect transistor or the second field effect transistor are controlled through an instruction sent by the main control chip so as to realize the adjustment of the voltage of the DDRVREFCA circuit module, so that a machine table is prevented from being disassembled for multiple times in a running test, and the test efficiency is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of voltage biasing circuits, in particular to a DDR voltage temperature 4-corner test Vref voltage biasing circuit. Background Art

[0002] The DDR voltage and temperature 4-corner test tests the performance changes of DDR on the board under various environments (including temperature, voltage, and load) by pulling the bias of V12_DDR and DDR_VREFCA. There are two specific pulling methods: 1) V12_DDR and DDR_VREFCA are pulled biased at the same time. The simultaneous pulling method ensures that V12_DDR and DDR_VREFCA change synchronously. The main purpose is to simulate the actual operation of the designed and developed machine motherboard system. On this platform, the impact of motherboard voltage changes on memory operation can be verified; 2) V12_DDR and DDR_VREFCA are pulled biased independently. The independent pulling method mainly examines the impact of noise tolerance on DDR operation on the machine motherboard.

[0003] However, the ordinary DDR_VREFCA voltage requires not only complicated operation when performing a 4-corner test on the machine, but also requires the machine to be disassembled to modify the resistance before testing. Therefore, stopping the temperature chamber, dismantling the machine, and re-setting up the test environment not only increases the labor intensity of the staff, but also wastes the staff's time, while also making the test efficiency low. Utility Model Content

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a DDR voltage temperature 4-corner test Vref voltage deviation circuit to solve the problem of low test efficiency in the prior art.

[0005] In order to achieve the above purpose and other related purposes, the utility model provides the following technical solutions:

[0006] A DDR voltage temperature 4-corner test Vref voltage biasing circuit comprises: a first voltage biasing module and a second voltage biasing module connected to a DDR_VREFCA circuit module, the first voltage biasing module and the second voltage biasing module are connected to each other, and the first voltage biasing module and the second voltage biasing module are both connected to a main control chip, wherein the first voltage biasing module comprises a first field effect transistor, the second voltage biasing module comprises a second field effect transistor, the first field effect transistor and the second field effect transistor are both controlled by the main control chip, and the voltage division of the DDR_VREFCA circuit module is adjusted by controlling the conduction and non-conduction of the first field effect transistor or the second field effect transistor.

[0007] In one embodiment of the utility model, the first voltage pull-bias module also includes a first resistor and a third resistor, the gate of the first field effect transistor is the DDR_VREFCA_CTU0 terminal and is connected to the output end of the main control chip, the gate of the first field effect transistor is also grounded through the first resistor, the drain of the first field effect transistor is the V12_DDR terminal and is connected to the DDR_VREFCA circuit module, and the source of the first field effect transistor is respectively connected to the second voltage pull-bias module and the DDR_VREFCA circuit module through the third resistor.

[0008] In one embodiment of the utility model, the second voltage biasing module also includes a second resistor and a fourth resistor, the gate of the second field effect transistor is the DDR_VREFCA_CTL0 terminal and is connected to the output terminal of the main control chip, the gate of the second field effect transistor is also connected to the source of the second field effect transistor and the DDR_VREFCA circuit module through the second resistor and is grounded, and the drain of the second field effect transistor is respectively connected to the first voltage biasing module and the DDR_VREFCA circuit module through the fourth resistor.

[0009] In one embodiment of the utility model, the DDR_VREFCA circuit module includes a first DDR_VREFCA circuit sub-module and a second DDR_VREFCA circuit sub-module connected to each other, the first DDR_VREFCA circuit sub-module is also connected to the first voltage pull-bias module and the second voltage pull-bias module respectively, and the second DDR_VREFCA circuit sub-module is also connected to the first voltage pull-bias module and the second voltage pull-bias module respectively.

[0010] In one embodiment of the utility model, the first DDR_VREFCA circuit submodule includes a first capacitor, a fifth resistor and a sixth resistor, the positive electrode of the first capacitor is connected to the first voltage pull-bias module, the positive electrode of the first capacitor is also connected to the negative electrode of the first capacitor through the fifth resistor and the sixth resistor, the negative electrode of the first capacitor is the DDR_VREFCA end and is respectively connected to the second DDR_VREFCA circuit submodule, the first voltage pull-bias module and the second voltage pull-bias module.

[0011] In one embodiment of the utility model, the second DDR_VREFCA circuit submodule includes a second capacitor, a seventh resistor and an eighth resistor, the positive electrode of the second capacitor is also the DDR_VREFCA end and is respectively connected to the first DDR_VREFCA circuit submodule, the first voltage pull-bias module and the second voltage pull-bias module, the positive electrode of the second capacitor is also connected to the negative electrode of the second capacitor through the seventh resistor and the eighth resistor, and the negative electrode of the second capacitor is also connected to the second voltage pull-bias module and grounded.

[0012] As described above, a DDR voltage temperature 4-corner test Vref voltage deviation circuit of the utility model has the following beneficial effects: the utility model adjusts the voltage of the DDR_VREFCA circuit module by controlling the conduction and non-conduction of the first field effect tube or the second field effect tube through the instruction issued by the main control chip. Therefore, when developing the motherboard, the utility model switches the voltage of V12_DDR and DDR_VREFCA by controlling the opening and closing of the first field effect tube or the second field effect tube, avoiding multiple disassembly of the machine when running the test, which not only improves the test efficiency, but also reduces the labor intensity of the staff and saves the staff's time. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 Shown is the existing common DDR_VREFCA circuit schematic diagram;

[0014] Figure 2 It shows the overall structure schematic diagram of the DDR voltage temperature 4-corner test Vref voltage deviation circuit disclosed in the embodiment of the utility model;

[0015] Figure 3 Shown is the overall circuit schematic diagram of the DDR voltage temperature 4-corner test Vref voltage biasing circuit disclosed in the embodiment of the utility model;

[0016] Figure 4 It shows an equivalent circuit principle diagram in which the first field effect tube is turned on and the second field effect tube is not turned on in the DDR voltage temperature 4-corner test Vref voltage deviation circuit disclosed in the embodiment of the utility model;

[0017] Figure 5 It shows an equivalent circuit principle diagram in which the first field effect tube is not turned on and the second field effect tube is turned on in the DDR voltage temperature 4-corner test Vref voltage deviation circuit disclosed in an embodiment of the utility model. DETAILED DESCRIPTION

[0018] The following describes the implementation of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0019] See also Figure 2The utility model provides a DDR voltage temperature 4-corner test Vref voltage biasing circuit, including: a first voltage biasing module and a second voltage biasing module connected to a DDR_VREFCA circuit module. Specifically, the DDR_VREFCA circuit module includes a first DDR_VREFCA circuit sub-module and a second DDR_VREFCA circuit sub-module connected to each other.

[0020] See also Figure 1 and Figure 3 , the first DDR_VREFCA circuit submodule includes a first capacitor C1, a fifth resistor R5 and a sixth resistor R6, and the second DDR_VREFCA circuit submodule includes a second capacitor C2, a seventh resistor R7 and an eighth resistor R8. In this embodiment, the first capacitor C1 and the second capacitor C2 are selected as examples for description;

[0021] The positive electrode of the first capacitor C1 is connected to the first voltage deviation module, and the positive electrode of the first capacitor C1 is also connected to the negative electrode of the first capacitor C1 through the fifth resistor R5 and the sixth resistor R6. The negative electrode of the first capacitor C1 is the DDR_VREFCA end and is respectively connected to the second DDR_VREFCA circuit submodule, the first voltage deviation module and the second voltage deviation module; the positive electrode of the second capacitor C2 is also the DDR_VREFCA end and is respectively connected to the first DDR_VREFCA circuit submodule, the first voltage deviation module and the second voltage deviation module, the positive electrode of the second capacitor C2 is also connected to the negative electrode of the second capacitor C2 through the seventh resistor R7 and the eighth resistor R8, and the negative electrode of the second capacitor C2 is also connected to the second voltage deviation module and grounded;

[0022] Among them, the DDR_VREFCA circuit module is Figure 1 The ordinary DDR_VREFCA circuit shown uses V12_DDR (1.2V) to divide the voltage to obtain a DDR reference level DDR_VREFCA of 0.6V. The first capacitor C1 and the second capacitor C2 play a role in voltage stabilization. The role of the fifth resistor R5 to the eighth resistor R8 is to provide voltage division under normal working conditions, thereby ensuring that the voltage of DDR_VREFCA is 0.6V required for normal operation. In the utility model, in order to improve the test efficiency, two field effect transistors are added to the DDR_VREFCA circuit module for voltage division adjustment control, namely the first field effect transistor Q9 and the second field effect transistor Q10 mentioned below.

[0023] See also Figure 3The first voltage pull-bias module includes a first field effect transistor Q9, a first resistor R1 and a third resistor R3, and the second voltage pull-bias module includes a second field effect transistor Q10, a second resistor R2 and a fourth resistor R4. In this embodiment, the first field effect transistor Q9 and the second field effect transistor Q10 are both DMG1012T. The first field effect transistor Q9 and the second field effect transistor Q10 are taken as examples for description below;

[0024] The gate of the first field effect transistor Q9 is the DDR_VREFCA_CTU0 terminal and is connected to the output terminal of the main control chip. The gate of the first field effect transistor Q9 is also grounded through the first resistor R1. The drain of the first field effect transistor Q9 is the V12_DDR terminal and is connected to the DDR_VREFCA circuit module. The source of the first field effect transistor Q9 is respectively connected to the second voltage biasing module and the DDR_VREFCA circuit module through the third resistor R3.

[0025] The gate of the second field effect transistor Q10 is the DDR_VREFCA_CTL0 terminal and is connected to the output terminal of the main control chip. The gate of the second field effect transistor Q10 is also connected to the source of the second field effect transistor Q10 and the DDR_VREFCA circuit module through the second resistor R2 and is grounded. The drain of the second field effect transistor Q10 is connected to the first voltage biasing module and the DDR_VREFCA circuit module through the fourth resistor R4, wherein the first resistor R1 and the second resistor R2 have two functions, one is to provide a bias voltage, and the other is to act as a discharge resistor. The third resistor R3 and the fourth resistor R4 participate in voltage division and provide a bias voltage when the first field effect transistor Q9 and the second field effect transistor Q10 are turned on.

[0026] Specifically, the DDR_VREFCA_CTU0 end and the DDR_VREFCA_CTL0 end are respectively connected to the GPIO (output end) pins of the main control chip on the board, and the corresponding pins of the main control chip are pulled up or down through instructions to control the opening and closing of the first field effect transistor Q9 or the second field effect transistor Q10 to adjust the voltage of the DDR_VREFCA circuit module; and the DDR_VREFCA_CTU0 end and the DDR_VREFCA_CTL0 end are initialized to be non-conductive (or both conductive) after the board is powered on normally, and the voltage of DDR_VREFCA is a normal 0.6V. Only when DDR_VREFCA needs to be pulled biased, it will be controlled to be conductive or non-conductive (not conductive at the same time);

[0027] More specifically, pull DDR_VREFCA_CTU0 high and pull DDR_VREFCA_CTL0 low, the first field effect transistor Q9 is turned on, and the second field effect transistor Q10 is not turned on. The equivalent circuit is as follows Figure 4At this time, the voltage of DDR_VREFCA is calculated to be 0.7V, and the calculation formula is: DDR_VREFCA voltage = (1 / (1+(1 / R7+1 / R8) / (1 / R3+1 / R5+1 / R6)))*1.2; pull DDR_VREFCA_CTU0 low and pull DDR_VREFCA_CTL0 high, the first field effect tube Q9 is not turned on, and the second field effect tube Q10 is turned on. The equivalent circuit is as follows Figure 5 , at this time, the DDR_VREFCA voltage calculation formula is: DDR_VREFCA voltage = (1 / (1+(1 / R4+1 / R7+1 / R8) / (1 / R5+1 / R6)))*1.2. After calculation, the DDR_VREFCA level is 0.5V at this time. Therefore, the above operation can be used to independently pull the DDR_VREFCA to examine the impact of noise tolerance on the DDR operation on the machine motherboard;

[0028] Furthermore, the first field effect transistor Q9, the second field effect transistor Q10, the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4 can be removed from the BOM before mass production of the machine, without affecting the cost of the whole machine; therefore, compared with the ordinary DDR_VREFCA circuit, when performing a 4-corner test, the utility model does not require complicated operations (preparing multiple prototypes of various voltages (occupying the already tight R&D prototypes) or disassembling the machine, rebuilding the environment, etc., and the voltage is pulled by command operation, thereby making the test simpler.

[0029] In summary, the utility model adjusts the voltage of the DDR_VREFCA circuit module by controlling the conduction and non-conduction of the first field effect tube or the second field effect tube through the instructions issued by the main control chip. Therefore, when developing the motherboard, the utility model switches the voltage of V12_DDR and DDR_VREFCA by controlling the opening and closing of the first field effect tube or the second field effect tube, avoiding multiple disassembly of the machine when running the test, which not only improves the test efficiency, but also reduces the labor intensity of the staff and saves the staff's time.

[0030] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. All equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention shall still be covered by the claims of the present invention.

Claims

1. A DDR voltage temperature 4-corner test Vref voltage deviation circuit, characterized in that: include: A first voltage pull-bias module and a second voltage pull-bias module are connected to the DDR_VREFCA circuit module, the first voltage pull-bias module and the second voltage pull-bias module are connected to each other, and the first voltage pull-bias module and the second voltage pull-bias module are both connected to the main control chip, wherein the first voltage pull-bias module includes a first field effect transistor, the second voltage pull-bias module includes a second field effect transistor, the first field effect transistor and the second field effect transistor are both controlled by the main control chip, and the voltage division of the DDR_VREFCA circuit module is adjusted by controlling the conduction and non-conduction of the first field effect transistor or the second field effect transistor.

2. A DDR voltage temperature 4-corner test Vref voltage deviation circuit according to claim 1, characterized in that: The first voltage biasing module also includes a first resistor and a third resistor. The gate of the first field effect transistor is the DDR_VREFCA_CTU0 terminal and is connected to the output terminal of the main control chip. The gate of the first field effect transistor is also grounded through the first resistor. The drain of the first field effect transistor is the V12_DDR terminal and is connected to the DDR_VREFCA circuit module. The source of the first field effect transistor is respectively connected to the second voltage biasing module and the DDR_VREFCA circuit module through the third resistor.

3. A DDR voltage temperature 4-corner test Vref voltage deviation circuit according to claim 1, characterized in that: The second voltage pull-bias module also includes a second resistor and a fourth resistor. The gate of the second field effect transistor is the DDR_VREFCA_CTL0 terminal and is connected to the output terminal of the main control chip. The gate of the second field effect transistor is also connected to the source of the second field effect transistor and the DDR_VREFCA circuit module through the second resistor and is grounded. The drain of the second field effect transistor is respectively connected to the first voltage pull-bias module and the DDR_VREFCA circuit module through the fourth resistor.

4. A DDR voltage temperature 4-corner test Vref voltage deviation circuit according to claim 1, characterized in that: The DDR_VREFCA circuit module includes a first DDR_VREFCA circuit submodule and a second DDR_VREFCA circuit submodule connected to each other, the first DDR_VREFCA circuit submodule is also connected to the first voltage pull-bias module and the second voltage pull-bias module respectively, and the second DDR_VREFCA circuit submodule is also connected to the first voltage pull-bias module and the second voltage pull-bias module respectively.

5. A DDR voltage temperature 4-corner test Vref voltage deviation circuit according to claim 4, characterized in that: The first DDR_VREFCA circuit submodule includes a first capacitor, a fifth resistor and a sixth resistor. The positive electrode of the first capacitor is connected to the first voltage pull-bias module. The positive electrode of the first capacitor is also connected to the negative electrode of the first capacitor through the fifth resistor and the sixth resistor. The negative electrode of the first capacitor is the DDR_VREFCA end and is respectively connected to the second DDR_VREFCA circuit submodule, the first voltage pull-bias module and the second voltage pull-bias module.

6. A DDR voltage temperature 4-corner test Vref voltage deviation circuit according to claim 4, characterized in that: The second DDR_VREFCA circuit submodule includes a second capacitor, a seventh resistor and an eighth resistor. The positive electrode of the second capacitor is also the DDR_VREFCA end and is respectively connected to the first DDR_VREFCA circuit submodule, the first voltage pull-bias module and the second voltage pull-bias module. The positive electrode of the second capacitor is also connected to the negative electrode of the second capacitor through the seventh resistor and the eighth resistor. The negative electrode of the second capacitor is also connected to the second voltage pull-bias module and grounded.

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