Package

Abstract

The utility model provides a packaging piece which comprises a first packaging assembly and a second packaging assembly. The first package assembly includes a first semiconductor substrate, a first dielectric layer over the first semiconductor substrate, and a first plurality of metal pads in the first dielectric layer. The second package component includes a second semiconductor substrate and a second dielectric layer under the second semiconductor substrate. The second dielectric layer is bonded to the first dielectric layer, and wherein an entire top surface of the first metal pad of the first plurality of metal pads contacts the second dielectric layer.

Description

Technical Field

[0001] The embodiment of the utility model relates to a packaging component. Background Art

[0002] Fusion bonding is a common bonding method for bonding two package components such as wafers and dies. In the bonding process, the package components are first bonded by pre-bonding at a lower temperature, and then the bonding process is performed at a higher temperature to bond the package components together. Utility Model Content

[0003] The present application provides a package including a first package component and a second package component. The first package component includes a first semiconductor substrate, a first dielectric layer on the first semiconductor substrate, and a first plurality of metal pads in the first dielectric layer. The second package component includes a second semiconductor substrate and a second dielectric layer under the second semiconductor substrate, wherein the second dielectric layer is bonded to the first dielectric layer, and wherein the entire top surface of a first metal pad in the first plurality of metal pads contacts the second dielectric layer.

[0004] The present application provides a package including a first device die and a second device die on and bonded to the first device die. The first device die includes a first dielectric layer, a second dielectric layer on the first dielectric layer, wherein the first dielectric layer and the second dielectric layer are formed of different dielectric materials, and a plurality of metal pads in the second dielectric layer, wherein a bottom surface of the plurality of metal pads contacts a first top surface in the first dielectric layer, and wherein a second top surface of the plurality of metal pads is coplanar with a third top surface in the second dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0006] Figure 1-6 A cross-sectional view is shown of an intermediate stage in the construction of a package including a bonding process, in accordance with some embodiments.

[0007] Figure 7 A top view of a wafer, metal pads, and bond wave propagation is shown in accordance with some embodiments.

[0008] Figures 8A to 8E Metal pads in a device die are shown according to some embodiments.

[0009] Fig. 9A , Fig. 9B and Fig. 9C Structures formed by a wafer-on-wafer bonding process, a chip-on-wafer bonding process, and a chip-on-chip bonding process according to some embodiments are respectively shown.

[0010] Fig.10 A process flow for forming a package according to some embodiments is shown. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for implementing the different features of the utility model embodiments. The following describes specific examples of components and arrangements to simplify the disclosure. Of course, these are only examples and are not intended to be limiting. For example, the following description of forming a first feature on a second feature or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than representing the relationship between the various embodiments and / or configurations discussed.

[0012] Furthermore, for ease of description, spatially relative terms such as "underlying," "below," "lower," "overlying," "upper," and the like may be used herein to describe the relationship of one element or feature to another (other) element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0013] A package and a method for forming a package are provided. According to some embodiments, fusion bonding is used to bond two package components. A metal pad is formed on at least one of the package components. The metal pad can be a dummy pad. The surface of the metal pad has different properties from the dielectric layer, resulting in changes in the propagation of the bonding wave in the pre-bonding. Therefore, tiny non-bonding areas that may occur are avoided. The embodiments discussed herein will provide examples of the subject matter that can be implemented or used, and those skilled in the art will easily understand the modifications that can be made while remaining within the intended scope of different embodiments. In the various views and illustrative embodiments, similar reference numerals are used to refer to similar elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0014] Figures 1 to 6 1 shows a cross-sectional view of an intermediate stage of the construction of a package according to some embodiments, which includes a forming process of the package and a corresponding bonding process. The corresponding process is also schematically reflected in Fig.10 The process flow shown.

[0015] Figure 1 2 shows a cross-sectional view of the construction of the package assembly 20. The corresponding process is illustrated as process 202 in the process flow 200, as shown in FIG. Fig.10 As shown. According to some embodiments, the package component 20 is or includes a device wafer, and the device wafer includes active devices and possible passive devices, which are represented as integrated circuit devices 26. According to alternative embodiments, the package component 20 is a carrier (e.g., a silicon carrier) that does not have active devices and passive devices and is used to provide mechanical support for the thin package component during its formation. According to some other alternative embodiments, the package component 20 is an interposer wafer that does not include active devices and may or may not include passive devices. According to some other alternative embodiments, the package component 20 is or includes a package, such as an integrated fan-out (InFO) package. For example, the package component 20 can be a reconstructed wafer, which includes device dies and / or wafers bonded together and encapsulated in an encapsulation body (e.g., a molding compound). The package component 20 can also be a silicon carrier, which has no metal features and active devices inside.

[0016] When the package component 20 is a wafer, it may include multiple dies 22, and some details of one of the dies 22 are shown. The package component 20 can also be at the die (chip) level instead of the wafer level, and can be a device die, an intermediate die, a discrete package (cut from a reconstructed wafer), or the like. In the subsequent discussion, the device wafer is used as an example of the package component 20, and the package component 20 can also be referred to as a wafer 20. These embodiments can also be applied to intermediate wafers, carriers, reconstructed wafers, discrete packages, discrete device dies, discrete intermediate dies, etc.

[0017] According to some embodiments, wafer 20 includes semiconductor substrate 24 and features formed at a top surface of semiconductor substrate 24. Semiconductor substrate 24 may be formed of or include crystalline silicon, crystalline germanium, crystalline silicon germanium, carbon-doped silicon, III-V compound semiconductors, or the like. Semiconductor substrate 24 may also be a bulk semiconductor substrate or a semiconductor-on-insulator (SOI) substrate.

[0018] According to some embodiments, wafer 20 includes integrated circuit devices 26 formed at a top surface of semiconductor substrate 24. According to some embodiments, integrated circuit devices 26 may include complementary metal oxide semiconductor (CMOS) transistors, resistors, capacitors, diodes, and / or the like. Details of integrated circuit devices 26 are not described herein.

[0019] An interlayer dielectric (ILD) 28 is formed over semiconductor substrate 24 and fills spaces between gate stacks of transistors (not shown) in integrated circuit device 26. According to some embodiments, ILD 28 is formed of phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), silicon oxide, silicon oxynitride, silicon nitride, or the like. ILD 28 may be formed using spin-on coating, fluid chemical vapor deposition (FCVD), chemical vapor deposition (CVD), or the like.

[0020] Contact plug 30 is formed in ILD 28 and is used to electrically connect integrated circuit device 26 to the overlying metal lines and vias. According to some embodiments, contact plug 30 is formed of or includes a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and / or multilayers thereof.

[0021] The interconnect structure 32 is formed on the ILD 28 and the contact plug 30. The interconnect structure 32 may include a metal line 34 and a via 36 formed in a dielectric layer 38 (also referred to as an intermetallic dielectric (IMD)). Hereinafter, metal lines of the same layer are collectively referred to as metal layers. According to some embodiments, the interconnect structure 32 includes a plurality of metal layers interconnected by vias 36. The metal line 34 and the via 36 may be formed of copper, tungsten, copper alloys and / or other metals. According to some embodiments, the dielectric layer 38 is formed of a low-k dielectric material. For example, the dielectric constant (k value) of the low-k dielectric material may be lower than about 3.0, for example, the dielectric layer 38 may include a carbon-containing low-k dielectric material, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ) or the like.

[0022] The interconnect structure 32 may also include a passivation layer on top of the low-k dielectric layer, which may be formed of a non-low-k dielectric material. The passivation layer may be formed of or include undoped silicate glass (USG), silicon nitride, silicon oxide, or the like, or multiple layers thereof. There may also be metal pads (e.g., aluminum copper pads), post-passivation interconnects (PPI), metal pads, or the like, all of which are referred to as conductive features.

[0023] refer to Figure 2 , a dielectric layer 42 is deposited on the interconnect structure 32. The corresponding process is illustrated as process 204 in the process flow 200, as shown in FIG. Fig.10 As shown. The top surface of dielectric layer 42 is planar. According to some embodiments, dielectric layer 42 is a single-layer film formed of a homogeneous material having a uniform composition. Throughout the description, when two features (e.g., two layers) are referred to as having the same composition, it means that the two features have the same type of elements, and the percentages of the corresponding elements in the two features are the same as each other. Conversely, when two features are referred to as having different compositions, it means that one of the two features has at least one element that is not in the other feature, or the two features have the same element, but the percentages of the elements in the two features are different from each other.

[0024] According to some embodiments, dielectric layer 42 may be formed of or include a silicon-based dielectric material, which may include one or more of oxygen, carbon, and nitrogen. The material of dielectric layer 42 may be represented by SiO x N y C z, where x is in a range between about 0 and about 2, y is in a range between about 0 and about 1.33, and z is in a range between about 0 and about 1. The x, y, and z values ​​are not all zero. For example, dielectric layer 42 may be formed of or include SiON, SiN, SiOCN, SiCN, SiOC, SiC, or the like.

[0025] According to some alternative embodiments, dielectric layer 42 is a composite layer including two, three or more sub-layers. Each dielectric layer in dielectric layer 42 can be represented as SiO2 as discussed above. x N y C z For example, in the example shown, dielectric layer 42 includes dielectric (sub)layers 42A, 42B, and 42C. Dielectric layer 42B has a different composition than dielectric layers 42A and 42C, for example, at least one or more of the values ​​x, y, and z in each of dielectric layers 42A, 42B, and 42C is different from the values ​​of the dielectric layers adjacent thereto. Each of dielectric layers 42A, 42B, and 42C may be formed of a homogeneous material.

[0026] According to some embodiments, alignment mark 41A is formed in a dielectric layer (e.g., dielectric layer 42B) below a top dielectric layer (e.g., dielectric layer 42C). Alignment mark 41A may be formed by a damascene process, which includes forming an opening in dielectric layer 42B by etching, filling a metal material such as copper in the opening, and performing a planarization process. According to an alternative embodiment, alignment mark (e.g., alignment mark 41B) is formed in a top dielectric layer (e.g., dielectric layer 42C). According to yet another alternative embodiment, both alignment marks 41A and 41B are formed.

[0027] The metal pad 44 is formed in the top dielectric layer (eg, dielectric layer 42C). The corresponding process is also shown as process 204 in process flow 200, as shown in FIG. Fig.10 As shown. The metal pad 44 can be formed in the same formation process as the alignment mark 41B (if formed) and is therefore formed of the same material. As will be discussed in the subsequent process, since the metal pad 44 does not serve as a bonding pad, other metal materials (in addition to copper) such as tungsten, aluminum, nickel or the like can be used to form the metal pad 44. The metal pad 44 and the alignment mark 41B can also be formed by a damascene process, in which an opening is formed in the dielectric layer 42C, a metal material such as copper is filled in the opening, and a planarization process is performed.

[0028] According to yet another alternative embodiment, instead of forming metal pad 44, non-metallic materials such as dielectrics, semiconductors (such as silicon) or the like may be used to form pads in the top dielectric layer. The formation process may also include a damascene process and may be the same as forming metal pad 44, except that instead of filling the opening with metal, a non-metallic material different from the top dielectric layer 42C is filled. The non-metallic material may also be represented by SiO x N y C z , except that the composition of the non-metallic material is different from that of the top dielectric layer 42C. The non-metallic material may also include a dielectric material that does not contain silicon, such as aluminum oxide, aluminum nitride, or the like.

[0029] According to some embodiments, the metal pads 44 are electrically floating. Each metal pad 44 may be completely surrounded by the dielectric layer 42C, and each metal pad 44 is in full contact with the top surface of the underlying dielectric layer (e.g., dielectric layer 42B). Each metal pad 44 may also be completely surrounded by the dielectric layer 42C. According to some embodiments, one or more of the metal pads 44 may be electrically grounded, while the other metal pads 44 are electrically floating. The electrically grounded metal pad 44 may be a termination pad, wherein the electrical path including the corresponding metal pad terminates at the top surface of the electrically grounded metal pad 44 and does not extend to the upper package component 120 ( Figure 3 ).

[0030] Figure 7 FIG. 2 shows a top view of a wafer 20 according to some embodiments. The wafer 20 includes a plurality of dies 22 separated from each other by scribe lines 50. According to some embodiments, each die 22 includes a plurality of metal pads 44 disposed at the bottom of the wafer 20. Figure 7 , and according to some example embodiments Figures 8A to 8E . The metal pads 44 formed at the wafer level by wafer-on-wafer bonding or chip-on-wafer bonding when bonding may be employed. Thus, the metal pads 44 may extend to a plurality of device dies 22. According to some embodiments, all of the metal pads 44 are formed in the scribe lines 50 but not in the device dies 22. According to an alternative embodiment, all of the metal pads 44 are formed in the device dies 22 but not in the scribe lines 50. According to yet another alternative embodiment, the metal pads 44 are formed in both the device dies 22 and the scribe lines 50.

[0031] The metal pads 44 may be formed as concentric rings whose centers are aligned with the center 20C of the wafer 20, as shown in FIG. Figure 7. The corresponding metal pads 44 may be evenly spaced to reduce the pattern-loading effect of the metal pads 44 and the top surface of the dielectric layer 42C during planarization. The metal pads 44 may have any other shape, such as a ring, including but not limited to a rectangle, a circle, a hexagon, an octagon, a triangle, or the like, wherein there may or may not be breaks in the pattern of the metal pads 44. In addition, if the ring-shaped metal pads 44 include breaks (such as break 45), the break 45 in the outer ring and its corresponding break in the adjacent inner ring may be misaligned from the same radius.

[0032] Fig. 8A , 8B 8C, 8D, and 8E show some example device dies 22 and metal pads 44 according to some embodiments. When forming the scribe line 50, the metal pad 44 may have a similar Fig. 8A , 8B , 8C, 8D and 8E. It should be understood that the metal pads 44 can have any suitable pattern to provide that when the bonding wave propagates, the metal pads 44 are in the way of the bonding wave and will be able to change the propagation behavior of the bonding wave as discussed later. Moreover, the metal pads 44 can be evenly distributed (with uniform pattern density) throughout the corresponding die 22 and / or wafer 20.

[0033] like Fig. 8A , 8B As shown in FIG. 8C , the metal pad 44 forms a plurality of discrete patterns that are isolated from each other by the dielectric layer 42C. The plurality of discrete patterns may have a rectangular top view shape (eg, Fig. 8A ), an elongated top view shape (as shown in Figure 8B and 8C ), a hexagonal top view shape, an elliptical top view shape, an octagonal top view shape, or the like. According to some embodiments, the metal pads 44 are arranged in a repeating pattern, such as an array, a honeycomb (hexagonal) pattern, or the like.

[0034] Figure 8B The metal pads 44 are shown to be elongated and have length directions parallel to each other. Figure 8C The metal pads 44 are shown to be elongated and include a first plurality of metal pads 44 and a second plurality of metal pads 44. The first plurality of metal pads 44 have length directions parallel to each other. The second plurality of metal pads 44 have length directions parallel to each other and perpendicular to the length directions of the first plurality of metal pads 44. Fig.8D In the embodiment, metal pads 44 form a plurality of circular patterns, wherein outer circular patterns surround corresponding inner circular patterns. The centers of the circular patterns may be aligned with the centers of device die 22. Cracks 45 may be formed in the circular patterns. Fig. 8E The metal pads 44 are shown to form a plurality of rectangular (eg, square) patterns, wherein outer rectangles surround corresponding inner rectangles. Cracks 45 may be formed in the rectangular patterns.

[0035] See also Figure 3 , forming a package component 120, and aligning it with the device die 22 in the wafer 20 and placing it on the device die 22. According to some embodiments, the package component 120 is a device die, an interposer die, a package, or the like. Therefore, the corresponding bonding scheme is called chip-on-wafer bonding. Alternatively, the package component 120 can be a device wafer, an interposer wafer, a reconstructed wafer including a bonded device die, or the like. Therefore, the corresponding bonding scheme is called wafer-on-wafer bonding. Figure 3 The illustration takes a device die as an example.

[0036] In some example embodiments, the package component 120 has a similar structure to the package component 20. The structure and materials of the features in the package component 120 can refer to the similar features in the wafer 20, wherein the similar features in the package component 120 are indicated by adding the number "1" before the reference number of the corresponding features in the wafer 20. For example, the substrate in the wafer 20 is indicated as 24, and accordingly, the substrate in the package component 120 is indicated as 124. The package component 120 may include an integrated circuit device 126, an ILD 128, a contact plug 130, an interconnect structure 132, a dielectric layer 138, a metal line 134, and a through hole 136. The details of these features may be similar to the corresponding features in the wafer 20, and are not repeated here.

[0037] Package component 120 also includes a dielectric layer 142 on the surface. Dielectric layer 142 can be a single layer formed of a homogeneous dielectric material, or can be a composite layer including multiple dielectric layers (e.g., 142A, 142B, and 142C) formed of different dielectric materials with different compositions. The material and structure of dielectric layer 142 can be selected from the same candidate materials and structures used to form dielectric layer 42 (and dielectric layers 42A, 42B, and 42C).

[0038] According to some embodiments, no metal pad is formed in the surface dielectric layer (e.g., dielectric layer 142C) of dielectric layer 142. In other words, there is no other material in dielectric layer 142C. According to alternative embodiments, metal (or other material) pad 144 is also formed in dielectric layer 142. Therefore, metal pad 144 is shown as a dotted line to indicate that metal pad 144 may or may not be formed. The formation process and material of metal pad 144 may be the same as that of metal pad 44, and the material of metal (or other material) pad 144 may be selected from the same group of candidate materials used to form metal (or other material) pad 44. According to alternative embodiments of forming metal pad 144, metal pad 44 may or may not be formed.

[0039] Figure 3 The corresponding process is shown as process 206 in process flow 200. Fig.10 As shown. The bonding of package components 20 and 120 is through the surface dielectric layer (e.g., 42C and 142C). Therefore, the surface dielectric layers 42C and 142C are optionally referred to as bonding films. According to some embodiments, during the pre-bonding process, the package component 120 is brought into contact with the wafer 20 by applying pressure to press the package components 20 and 120 toward each other. The pre-bonding can be performed at room temperature (between about 20° C. and about 25° C.), or higher temperatures can be used.

[0040] Pre-bonding may begin by contacting the center of package assembly 120 to wafer 20. The contact propagates from the contact point to the edge of package assembly 20 and 120, which generates a bonding wave propagating from the contact point to the edge. Figure 7 , 8A Arrows 43 in 8B, 8C, 8D and 8E show some example directions of bonding wave propagation. As the bonding wave propagates from the contact point to the edge, the air between the packaging components 20 and 120 is gradually squeezed out, so no bubbles or moisture are trapped between the packaging components 20 and 120.

[0041] During the propagation of the bonding wave, the Joule-Thomson effect may occur, in which the temperature of certain parts of the package components 20 and 120 may drop, and moisture may condense on the low temperature surface. This will cause some tiny non-bonding areas to appear. If the bonding surfaces of the bonding films 42 and 142 are isotropic, the Joule-Thomson effect tends to occur. When at least one of the bonding films 42 and 142 includes corresponding metal pads 44 and 144, which have different compositions and different properties from the bonding films 42C and 142C, the bonding wave travels through the metal pads 44 (and / or 144) and the dielectric layers 42C and 142C at different speeds. Therefore, when encountering the metal pads 44 and / or 144, the bonding wave propagation will be disrupted and discontinuous. The bonding wave propagation behavior in different directions is different. The Joule-Thomson effect is reduced, and the tiny non-bonding areas are at least reduced or even possibly eliminated.

[0042] According to some embodiments, in order to effectively break the bonding wave, the size and spacing of the metal pads 44 are selected such that the breaking of the bonding wave is effective. Fig. 8AThe width and pitch of metal pads 44 according to some embodiments are shown. The length L1 and width W1 of metal pads 44 may be the same or different from each other, and may be in a range between about 1 μm (micrometer) to about 20 μm. The pitch P1 of metal pads 44 may also be the same or different from each other, and may be in a range between about 1 μm to about 100 μm. The total area of ​​metal pads 44 may be less than about 15% of the total area of ​​the corresponding chip or wafer, and may be in a range between about 5% and about 10%.

[0043] A plurality of package components 120 may be pre-bonded to the wafer 20, such as Figure 3 After the pre-bonding, an annealing process is performed, for example, to form Si-O-Si bonds between the bonding films 42 and 142, so that the bonding films 42 and 142 are bonded to each other by fusion bonding. The corresponding process is illustrated as process 208 in the process flow 200, as shown in FIG. Fig.10 According to some embodiments, the annealing process is performed at a temperature in a range between about 250° C. and about 300° C. According to some embodiments, the annealing duration may be in a range between about 5 minutes and about 30 minutes.

[0044] After annealing, when metal pads 144 are formed, metal pads 44 (if formed) may be in physical contact with dielectric layer 142C but not bonded (not bonded) to dielectric layer 142C. Similarly, when metal pads 44 are formed, metal pads 144 (if formed) may be in physical contact with dielectric layer 42C but not bonded (not bonded) to dielectric layer 42C. When both metal pads 44 and 144 are formed, metal pads 44 may or may not be bonded to metal pads 144. For example, the size and spacing of metal pads 44 may be equal to or different from the size and spacing of metal pads 144. Each metal pad 44 may not be aligned with all metal pads 144. According to some embodiments, any of the metal pads 44 may be bonded to one of the metal pads 144, or not bonded to any of the metal pads 144. Each metal pad 144 may be bonded to one of the metal pads 44, or not bonded to any of the metal pads 144, depending on their positions. According to some embodiments, none of the metal pads 144 is bonded to any of the metal pads 44, and even if metal pads 44 and 144 are formed, the corresponding bonding is fusion bonding. According to alternative embodiments, some metal pads 144 are bonded to some metal pads 44, while some other metal pads 44 and 144 are not bonded to any of the metal pads 144 and 44.

[0045] According to some embodiments, some or all of metal pads 44 are completely encapsulated in dielectric material (including, for example, dielectric layers 42B, 42C, and 42C). According to an alternative embodiment in which both metal pads 44 and 144 are formed, some metal pads 44 are bonded to corresponding metal pads 144, and the corresponding metal pads 44 and 144 as a combination are completely encapsulated in dielectric material.

[0046] refer to Figure 4 , the package component 120 is encapsulated in the encapsulation body 54 (dielectric gap filling area). The corresponding process is illustrated as process 210 in the process flow 200, as shown in FIG. Fig.10 As shown. According to some embodiments, encapsulation 54 may include a dielectric liner and a dielectric filling material on the dielectric liner. The dielectric liner may be formed of or include silicon nitride, and the dielectric filling material may include silicon oxide. Alternatively, encapsulation 54 may include a molding compound, an epoxy resin, a resin, and / or the like. A planarization process such as a CMP process is performed to make the top surface of encapsulation 54 flush with the top surface of package component 120.

[0047] According to some embodiments, some of the metal pads 44 may be located in a region that is not bonded to any package component 120 . Thus, the encapsulant 54 may be in physical contact with the top surface of some of the metal pads 44 .

[0048] Figure 5 An example embodiment is shown in which contact plugs 56 are formed to pass through the package component 120 and electrically connect the metal pads 134A in the package component 120 to the metal pads 34A in the wafer 20. The corresponding process is illustrated as process 212 in the process flow 200, as shown in FIG. Fig.10 As shown. The contact plug 56 lands on the metal pad 34A in the wafer 20. The contact plug 56 passes through the bonding films 42C and 142C. The contact plug 56 may pass through and contact one of the metal pads 44 (or 144), or may be away from all the metal pads 44 and / or all the metal pads 144. A dielectric isolation ring 62 may be formed to electrically insulate the contact plug 56 from the semiconductor substrate 124.

[0049] Reference Figure 6 A dielectric layer 58 (also referred to as a passivation layer) may be formed to cover the contact plug 56 and the substrate 124. The corresponding process is illustrated as process 214 in the process flow 200, as shown in FIG. Fig.10 As shown. Thus, a reconstructed wafer 60 is formed. Then, a singulation process may be performed along the dicing street 50 to saw the reconstructed wafer 60 and form a package 60'. The corresponding process is illustrated as process 216 in the process flow 200, as shown in FIG. Fig.10 Each package 60 ′ may include a package component 20 (eg, a device die) bonded to a package component 120 (eg, a device die).

[0050] exist Figure 6 In FIG. 4 , metal pad 44 is also shown as a dotted line to indicate that metal pad 44 may or may not be formed when metal pad 144 is formed. In other words, when chip-on-wafer bonding is performed, metal pads may be formed in the chip or the wafer or both.

[0051] Fig. 9A A package 60 formed by a wafer-on-wafer bonding process is shown. Wafer 20 is bonded to wafer 20'. Wafer 20 may include die 22, and wafer 20' may include die 122. Each of wafers 20 and 20' may be a device wafer, an interposer wafer, a carrier, a reconstructed wafer, or the like. Device die 22 of wafer 20 may or may not include metal pad 44 in bonding film 42C. Device die 122 of wafer 20' may or may not include metal pad 144 in bonding film 142C. At least one of metal pads 44 and 144 is formed.

[0052] Fig. 9B The package 60 is schematically shown formed by the chip-on-wafer bonding process. The details of the package 60 can be found in Figures 1 to 6 The encapsulation body encapsulating the package component 120 is not shown, refer to Figure 6 can be found.

[0053] Fig. 9C A package 60 ′ formed by a chip-on-chip bonding process is shown. The corresponding formation process may include sawing the wafer 20 into device dies 22 and then bonding the device die 122 to one of the device dies 22. Other details of the package 60 ′ can be found in Figures 1 to 6 The discussion will not be repeated here.

[0054] The embodiments of the present disclosure have some advantageous features. By forming a metal pad on the surface of the package component, the bonding wave in the pre-bonding process is broken. The Joule-Thomson effect is reduced, and the minor non-bonding issue is at least alleviated or possibly eliminated.

[0055] According to some embodiments of the present disclosure, a method includes depositing a first dielectric layer as a first surface layer of a first package component; forming a first plurality of metal pads in the first dielectric layer; depositing a second dielectric layer as a second surface layer of a second package component; and bonding the second package component to the first package component, wherein the first dielectric layer is bonded to the second dielectric layer, and wherein after bonding, a first metal pad among the first plurality of metal pads has a top surface in contact with a bottom surface in the second dielectric layer.

[0056] In one embodiment, forming the first plurality of metal pads includes patterning the first dielectric layer to form an opening; filling the metal material into the opening; and performing a planarization process on the metal material and the first dielectric layer. In one embodiment, after bonding, all top surfaces in the first plurality of metal pads are in contact with the bottom surface in the second dielectric layer. In one embodiment, all metal pads in the first dielectric layer are electrically floating. In one embodiment, after bonding, one of the first plurality of metal pads is completely enclosed in the dielectric material. In one embodiment, after bonding, all metal pads in the first dielectric layer are completely enclosed in the dielectric material.

[0057] In one embodiment, the method further includes encapsulating a second package component in an encapsulation, wherein an additional top surface of a second metal pad in the first plurality of metal pads contacts the encapsulation, and the method further includes forming a second plurality of metal pads in a second dielectric layer, wherein after bonding, the entire top surface of at least one of the first plurality of metal pads contacts the second dielectric layer. In one embodiment, after bonding, all metal pads in the first dielectric layer contact the second dielectric layer, and all metal pads in the second dielectric layer contact the first dielectric layer. In one embodiment, each of the first package component and the second package component comprises a wafer. In one embodiment, each of the first package component and the second package component comprises a discrete device die.

[0058] According to some embodiments of the present disclosure, a package includes a first packaging component, the first packaging component including a first semiconductor substrate; a first dielectric layer above the first semiconductor substrate; a first plurality of metal pads in the first dielectric layer; and a second packaging component including a second semiconductor substrate; and a second dielectric layer under the second semiconductor substrate, wherein the second dielectric layer is bonded to the first dielectric layer, and wherein the entire top surface of a first metal pad among the first plurality of metal pads contacts the second dielectric layer.

[0059] In one embodiment, in a top view of the package, the first plurality of metal pads are evenly distributed in the first dielectric layer. In one embodiment, all metal pads in the first dielectric layer are electrically floating. In one embodiment, all metal pads in the first dielectric layer are encapsulated in a dielectric material. In one embodiment, the second package assembly further includes a second plurality of metal pads in the second dielectric layer, wherein the second plurality of metal pads contact the first dielectric layer, and wherein the second plurality of metal pads are electrically floating.

[0060] According to some embodiments of the present disclosure, a package includes a first device die, the first device die including a first dielectric layer; a second dielectric layer on the first dielectric layer, wherein the first dielectric layer and the second dielectric layer are formed of different dielectric materials and a plurality of metal pads in the second dielectric layer, wherein a bottom surface of the plurality of metal pads contacts a first top surface in the first dielectric layer, and wherein a second top surface of the plurality of metal pads is coplanar with a third top surface in the second dielectric layer; and a second device die on and bonded to the first device die. In one embodiment, all metal pads in the second dielectric layer are electrically floating.

[0061] In one embodiment, a first metal pad of the plurality of metal pads is electrically floating, and wherein a second metal pad of the plurality of metal pads is electrically grounded. In one embodiment, the second device die further comprises a third dielectric layer bonded to the second dielectric layer, wherein the third dielectric layer is over and in contact with the plurality of metal pads, and wherein the third dielectric layer is a capping layer having no metal features therein. In one embodiment, the plurality of metal pads are evenly spaced apart.

[0062] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A package, characterized in that: include: | The first packaging component comprises: a first semiconductor substrate; a first dielectric layer over the first semiconductor substrate; and a first plurality of metal pads in the first dielectric layer; and The second packaging component comprises: a second semiconductor substrate; and A second dielectric layer under the second semiconductor substrate, wherein the second dielectric layer is bonded to the first dielectric layer, and wherein an entire top surface of a first metal pad of the first plurality of metal pads contacts the second dielectric layer.

2. The package according to claim 1, wherein: In a top view of the package, the first plurality of metal pads are evenly distributed in the first dielectric layer.

3. The package according to claim 1, wherein: All metal pads in the first dielectric layer are electrically floating.

4. The package according to claim 1, wherein: All metal pads in the first dielectric layer are encapsulated in dielectric material.

5. The package according to claim 1, wherein: The second packaging assembly further comprises: A second plurality of metal pads in the second dielectric layer, wherein the second plurality of metal pads contacts the first dielectric layer, and wherein the second plurality of metal pads are electrically floating.

6. A package, characterized in that: include: The first device die comprises: a first dielectric layer; a second dielectric layer on the first dielectric layer, wherein the first dielectric layer and the second dielectric layer are formed of different dielectric materials; and a plurality of metal pads in the second dielectric layer, wherein bottom surfaces of the plurality of metal pads contact a first top surface in the first dielectric layer, and wherein a second top surface of the plurality of metal pads is coplanar with a third top surface in the second dielectric layer; and A second device die is on and bonded to the first device die.

7. The package according to claim 6, wherein: All of the metal pads in the second dielectric layer are electrically floating.

8. The package according to claim 6, wherein: A first metal pad among the plurality of metal pads is electrically floating, and wherein a second metal pad among the plurality of metal pads is electrically grounded.

9. The package according to claim 8, wherein: The second device die further includes a third dielectric layer bonded to the second dielectric layer, wherein the third dielectric layer is over and in contact with the plurality of metal pads, and wherein the third dielectric layer is a blanket layer having no metal features therein.

10. The package according to claim 6, wherein: The plurality of metal pads are evenly spaced apart.

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