Chip structure for high-power packaging

Abstract

The utility model discloses a chip structure for high-power packaging and a preparation method thereof, relates to the field of power semiconductor devices, and provides a gallium nitride power device structure applied to high-power application, which is provided with a thick metal substrate and a thick metal top weldable metal layer, therefore, good heat dissipation performance and better device reliability are achieved; the utility model also provides a peripheral structure of the gallium nitride power device, which can prevent the chip from cracking during cutting and improve the reliability of the device.

Description

Technical Field

[0001] The utility model relates to the field of power semiconductor devices, in particular to a chip structure used for high-power packaging. Background Art

[0002] Gallium nitride power devices have the advantages of high electron mobility, high voltage resistance, and fast switching speed. Compared with silicon-based power devices, they can achieve large current applications with smaller devices, and are therefore suitable for high-power, high-voltage, and high-frequency applications.

[0003] In high current and high power applications, devices are required to have good heat dissipation performance and reliability. In order to enhance the heat dissipation performance of the device and reduce the package resistance, a metal bonding package is usually required. Figure 1 As shown, the upper end of the power device chip (130) has an upper copper sheet (133), which is connected together by solder (131) and connected to a pin (135), and the lower end of the power device chip (130) is connected to a bottom copper frame (134) by solder (131). When the device is working, a large current passes through the upper copper sheet (133), the power device chip (130) and the bottom copper frame (134), and the upper copper sheet (133) and the bottom copper frame (134) can provide good heat dissipation for the chip. As shown in the figure, since the upper and lower ends of the power device chip need to be bonded to the metal by solder (131), the upper and lower ends of the power device chip (130) need to have a solderable metal layer.

[0004] Figure 1 The solder (131) may contain radioactive lead, tin and other materials and produce radioactive particles. In the gallium nitride device, there are a large number of lattice dislocations and defects between the gallium nitride layers with different energy gaps, gallium nitride layers with different doping, and gallium nitride and other different material layers stacked in the vertical direction. Therefore, the radioactive particles in the vertical direction are easy to generate charge accumulation inside the gallium nitride device, affecting the electrical performance of the device and even affecting the reliability of long-term use.

[0005] Generally, heavy metal materials can effectively block radioactive particles, so thicker metal layers can block radioactive particles and help improve device reliability. Common GaN device substrates include silicon substrates, sapphire substrates, silicon carbide substrates, and GaN substrates. GaN and SiC substrates have better performance but are expensive; silicon substrates are cheap but have a lower lattice match with GaN materials; and sapphire substrates are generally cheaper, but because they are insulating materials, they are not suitable for vertical devices and have poor heat dissipation performance.

[0006] In addition, in the common GaN device wafer cutting process, due to the high hardness of the wafer and the high interlayer stress, it is easy to cause chip cracking at the edge of the chip, which leads to a reduction in chip yield and affects production costs. In addition, chip defects caused by chip edge cracking are prone to the invasion of contaminant ions, affecting reliability during long-term use. Utility Model Content

[0007] In order to solve the above-mentioned problems, the utility model provides a chip structure for high-power packaging, wherein the chip structure includes a top metal layer arranged above the semiconductor device area and a top solderable metal layer arranged above the top metal layer, a barrier metal layer and a solderable thick metal base layer with a thickness of 5um-160um arranged below the barrier metal layer are arranged below the semiconductor device area; the barrier metal layer is used to enhance the bonding strength of the thick metal base layer and prevent impurities from penetrating into the semiconductor device area, and the solderable thick metal base layer is used to provide a solderable metal interface, improve heat dissipation and block radioactive particles from below the device.

[0008] Furthermore, a semiconductor buffer layer is provided between the semiconductor device region and the barrier metal layer.

[0009] Furthermore, the semiconductor buffer layer is a semiconductor composite layer containing nitrogen, aluminum, indium, gallium, carbon and / or magnesium elements.

[0010] Furthermore, the top solderable metal layer is made of copper, nickel, gold, silver, platinum, titanium and / or aluminum; or

[0011] The barrier metal layer is made of titanium, antimony, tungsten, aluminum, copper, nickel, platinum, silver and / or gold, or the thick metal substrate layer is made of copper, nickel, gold and / or silver.

[0012] Furthermore, the top metal layer is also provided with a supporting layer made of a low resistance material, the supporting layer completely covers the top metal layer, and the top weldable metal layer completely covers the supporting layer; or

[0013] The top metal layer is further provided with a supporting layer made of insulating material, the supporting layer covers part of the top metal layer, and the top metal layer and the top solderable metal layer are at least partially connected; and / or

[0014] A supporting layer made of insulating material is also provided above the chip and at the cutting positions between the chips.

[0015] Furthermore, the thickness of the top metal layer is 1um-5um, or the thickness of the weldable metal layer is 5um-50um.

[0016] The beneficial effect of the utility model is that a gallium nitride power device structure for high-power applications is proposed, and the device structure has a thick metal substrate and a top solderable metal layer of the thick metal, so it has good heat dissipation performance and better device reliability; the utility model also proposes a peripheral structure of a gallium nitride power device, which can prevent cracking caused by chip cutting and improve the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of the cross-sectional structure of an existing high-power device.

[0018] Figure 2 The figure is a cross-sectional schematic diagram of a device structure according to an embodiment of the utility model.

[0019] Figure 3 The figure is a cross-sectional schematic diagram of a method for forming a device embodiment of the present invention.

[0020] Figure 4 It is a cross-sectional schematic diagram of a method for forming another variant of a device embodiment of the present invention.

[0021] Figure 5 The present invention is a schematic cross-sectional view of a method for forming a chip peripheral structure according to a device embodiment of the present invention.

[0022] Figure 6 This is a cross-sectional view of the chip peripheral structure of a device embodiment of the utility model after chip cutting. DETAILED DESCRIPTION

[0023] The present invention is described in detail below in conjunction with the accompanying drawings and embodiments.

[0024] It should be noted that the corresponding position words described in this document, such as "upper", "lower", "left", "right", "front", "rear", "vertical", "horizontal", and "vertical", correspond to the relative positions of the reference diagrams. In the specific implementation, there is no restriction on fixed directions. It should be noted that the devices in the drawings are not necessarily drawn to a specific scale. The straight lines shown as the boundaries of the doped regions and trenches in the drawings, and the sharp angles formed by the boundaries, are generally not straight lines and precise angles in actual applications.

[0025] Figure 2 The cross-sectional schematic diagram of a device structure of an embodiment of the utility model comprises:

[0026] A semiconductor device region located at the top, which in this embodiment is a gallium nitride device region (102);

[0027] A gallium nitride drift region (101) located below the gallium nitride device region (102);

[0028] A barrier metal layer (210) located below the gallium nitride drift region (101);

[0029] a solderable thick metal substrate layer (201) located below the barrier metal layer (210);

[0030] a top metal layer (110) located above the gallium nitride device region (102);

[0031] A top solderable metal layer (120) is located above the top metal layer (110), and solder (131) is located above the top solderable metal layer (120).

[0032] Preferably, the top metal layer (110) may also be provided with a supporting layer (211);

[0033] When the supporting layer (211) completely covers the top metal layer (110), and the top solderable metal layer (120) completely covers the supporting layer (211), a structure as shown in 4A is formed. In this figure, the supporting layer (211) may be a low-resistance material, which is retained on the entire chip to provide physical protection for the chip periphery.

[0034] When the supporting layer (211) only covers part of the top metal layer (110), and the top solderable metal layer (120) covers both the supporting layer (211) and the top metal layer (110) not covered by the supporting layer (211), the top metal layer (110) and the top solderable metal layer (120) are at least partially connected, and the resulting structure is shown in 4B; when the supporting layer (211) only covers part of the top metal layer (110), and the top solderable metal layer (120) is thinner than the remaining supporting layer (211) and only covers the top metal layer (110) located between multiple sections of the remaining supporting layer (211), the top metal layer (110) and the top solderable metal layer (120) are at least partially connected, and the resulting structure is shown in 4C. The supporting layer (211) can also extend downward at the cutting position between the chips, and only exists on the periphery of the chip, and is not retained inside, as shown in FIG. Figure 6 In these embodiments, the support layer (211) may be an insulating material, and the support layer (211) is finally only retained at the periphery of the chip to provide physical protection for the periphery of the chip and to act as a passivation layer to prevent ions from entering.

[0035] The gallium nitride device region (102) is a power device structure, which may be a JFET, HEMT, MISFET, CAVET, diode, triode, etc., and is composed of gallium nitride material, doped semiconductor material, insulating material and metal material. The gallium nitride device region (102) has the function of generating a conduction current when the device is forward or forward biased. The gallium nitride device region (102) is not limited to the power device structure shown in the figure or mentioned above, and may include semiconductor channels, 2DEG and other structures. Personnel in the art can combine existing power device structures to form more embodiment structures.

[0036] In one embodiment, a gallium nitride device region (102) has horizontal periodic contact holes, and a top metal layer (110) is connected to the gallium nitride through the periodic contact holes. The period of the periodic grooves is between 0.3-4 um.

[0037] The gallium nitride drift region (101) located below the gallium nitride device region (102) is used to withstand the reverse bias voltage when the device is reversed or reverse biased. Its thickness is proportional to the device withstand voltage, and its doping concentration is inversely proportional to the device withstand voltage. In an embodiment where the reverse bias voltage is 650V, the thickness of the gallium nitride drift region is between 10-50um.

[0038] In one embodiment, a buffer layer containing compound materials such as nitrogen and gallium may be further included between the gallium nitride drift region (101) and the barrier metal layer (210), and its functions are to: reduce lattice defects of the gallium nitride material in the gallium nitride drift region; reduce impurities invading the gallium nitride drift region; and reduce wafer stress.

[0039] The barrier metal layer (210) may be formed of alloys such as gold, silver, titanium, antimony, tungsten, aluminum, copper, nickel, platinum, etc., or metal compounds thereof. The barrier metal layer (210) serves to enhance the bonding force with the underlying solderable thick metal base layer (201), and to prevent the metal material and impurity elements (such as copper, gold, oxygen, carbon, etc.) of the underlying solderable thick metal base layer (201) from penetrating into the upper semiconductor.

[0040] In one embodiment, the barrier metal layer (210) is titanium-nickel-silver with thicknesses of 500A-3kA, 1kA-5kA, and 5kA-40kA, respectively.

[0041] In one embodiment, the barrier metal layer (210) is titanium-nickel-gold with thicknesses of 500A-3kA, 1kA-5kA, and 5kA-10kA, respectively.

[0042] In one embodiment, the barrier metal layer (210) is nickel-gold with thicknesses of 1 kA-2 um and 5 kA-10 kA respectively.

[0043] In one embodiment, the barrier metal layer (210) is titanium-nickel-copper with thicknesses of 500A-3kA, 1kA-5kA, and 5kA-40kA, respectively.

[0044] In one embodiment, the barrier metal layer (210) is nickel-copper with thicknesses of 500A-5AkA and 5kA-40kA respectively.

[0045] The solderable thick metal base layer (201) has the following functions: providing a solderable metal interface and bonding with the copper sheet below the high-power package; providing good heat dissipation for the semiconductor chip; and blocking radioactive particles from the solder (131) below the device.

[0046] The weldable thick metal base layer (201) is usually composed of metal or alloy, because high-density metal and thick metal thickness are both conducive to blocking radioactive particles. The thick metal base layer (201) is usually composed of metal with a density greater than 3g / cm3, such as copper, nickel, gold, silver, etc., or alloys of the above metals, such as aluminum-copper alloy. The thickness of the thick metal base layer (201) is usually between 5um and 160um, and the preferred thickness is 10-30um.

[0047] In one embodiment, the solderable thick metal base layer (201) is composed of copper and has a thickness between 10um and 60um.

[0048] In one embodiment, the solderable thick metal base layer (201) is composed of platinum-copper, and its thickness is 500A-2um, 5um-60um.

[0049] The top metal layer (110) located above the gallium nitride device region (102) is usually composed of alloys such as titanium, tungsten, platinum, nickel, aluminum, etc., and has a thickness of 1um-5um.

[0050] The top solderable metal layer (120) located above the top metal layer (110) has the following functions: providing a solderable metal interface and bonding with the upper copper sheet of the high-power package; providing good heat dissipation for the semiconductor chip; and blocking radioactive particles from the solder (131) above the device from entering the gallium nitride device area.

[0051] The top solderable metal layer (120) is usually composed of metal or alloy, such as copper, nickel, gold, silver, platinum, etc., or alloys of the above metals, such as titanium-nickel, aluminum-copper, titanium-nickel-silver. The thickness of the top solderable metal layer (120) is usually between 2um-60um.

[0052] In one embodiment, the top solderable metal layer (120) is a titanium-nickel-silver-copper composite layer, and its thickness is 500A-3kA, 1kA-5kA, 5kA-40kA, 5um-50um respectively.

[0053] In one embodiment, the top solderable metal layer (120) is a titanium-copper composite layer with thicknesses of 500A-3kA and 5um-50um, respectively.

[0054] In one embodiment, the top solderable metal layer (120) is a nickel-copper composite layer, and its thickness is 500A-2um, 5um-50um respectively.

[0055] In one embodiment, the top solderable metal layer (120) is a nickel-gold-copper composite layer, and its thickness is 500A-2um, 500A-5kA, 5um-50um respectively.

[0056] In one embodiment, the top solderable metal layer (120) is composed of pure copper with a thickness between 10um and 60um.

[0057] In one embodiment, the top solderable metal layer (120) and the thick metal base layer (201) are composed of the same material layer and have a uniform thickness.

[0058] Compared with the prior art, the present embodiment removes the semiconductor base layer (100) and replaces it with a solderable thick metal base layer (201). The solderable thick metal base layer (201) is made of high-density metal. The thick thickness can block radioactive particles. Since the solderable thick metal base layer (201) is made of metal material, the heat dissipation performance is better than that of insulating materials. At the same time, a barrier metal layer (210) is arranged between the solderable thick metal base layer (201) and the gallium nitride device region (102). In addition to enhancing the bonding force between the solderable thick metal base layer (201) and the gallium nitride device region (102), the barrier metal layer (210) can also prevent the metal material and impurity elements of the solderable thick metal base layer (201) below from penetrating into the gallium nitride device region (102).

[0059] In addition, a buffer layer is provided between the gallium nitride drift region (101) and the barrier metal layer (210) to reduce lattice defects of the gallium nitride material in the gallium nitride drift region, reduce impurities invading the gallium nitride drift region, and reduce wafer stress.

[0060] A method for forming a device embodiment of the utility model is as follows Figure 3 As shown:

[0061] In the first step, a semiconductor buffer layer (105) is formed on the semiconductor substrate layer (100), and then a gallium nitride drift region (101) is formed on the semiconductor buffer layer (105), as shown in 3A.

[0062] In one embodiment, the semiconductor substrate layer (100) may be made of sapphire. A semiconductor substrate layer made of sapphire material is beneficial for reducing production costs.

[0063] In another embodiment, the semiconductor base layer (100) may be made of gallium nitride.

[0064] In another embodiment, the semiconductor substrate layer (100) may be made of silicon carbide.

[0065] The semiconductor buffer layer (105) is used to: reduce the lattice defects of the gallium nitride material in the gallium nitride drift region; reduce the invasion of impurities into the gallium nitride drift region; and reduce the stress between the semiconductor and the substrate layer.

[0066] The semiconductor buffer layer (105) may be a semiconductor composite layer composed of nitrogen, aluminum, indium, gallium, carbon, magnesium and other elements. The composite layer may include a layer of aluminum nitride, and the composite layer may include multiple gallium nitride layers containing different carbon impurity contents. The composite layer may also include a P-type gallium nitride layer.

[0067] In one embodiment, the semiconductor buffer layer (105) is a semiconductor combination layer and includes a layer of indium gallium nitride. In one embodiment, the semiconductor buffer layer (105) is a multi-layer semiconductor layer, and each semiconductor layer has a different energy band gap ratio.

[0068] The gallium nitride drift region (101) is N-type doped and has a thickness between 3 and 50 um.

[0069] The method of forming the semiconductor buffer layer (105) and the gallium nitride drift region (101) may be organic metal chemical vapor deposition, epitaxial growth, or other appropriate deposition steps.

[0070] In the second step, a gallium nitride device region (102) is formed on the gallium nitride drift region (101), and a top metal layer (110) is formed, as shown in 3B.

[0071] The top metal layer (110) may be formed by metal deposition. In some embodiments, before the top metal layer (110) is formed, an anti-diffusion metal compound may be first formed on the semiconductor to prevent metal and impurities from diffusing into the semiconductor and to increase the adhesion between the metal and the semiconductor.

[0072] In the third step, a top supporting layer (211) is formed on the top metal layer (110), as shown in 3C.

[0073] The supporting layer (211) may be made of metal compounds, semiconductor compounds, organic compounds, etc. Generally, the supporting layer (211) needs to form good adhesion with the top metal layer (110) and ensure that the wafer does not generate excessive thermal stress in subsequent processes to cause damage to the underlying structure.

[0074] In one embodiment, the support layer (211) is made of a macromolecular organic polymer with a thickness of 1 um-50 um, and may be formed by processes such as spin coating and drying.

[0075] In one embodiment, the supporting layer (211) is made of a material comprising a silicide layer, and the thickness of the silicide layer is 1 um-10 um.

[0076] In the fourth step, a laser pulse process is performed to peel off the semiconductor from the semiconductor base layer (100), as shown in 3D.

[0077] Typically, the laser pulse process is performed below the semiconductor substrate layer (100). However, in some embodiments of wafer structures with a transparent upper surface, the laser pulse process may also be performed from above.

[0078] In one embodiment, a gallium nitride sacrificial layer may be pre-set in the buffer layer (105), and the energy depth is adjusted to the gallium nitride sacrificial layer during the laser pulse process, so that the gallium nitride stripping occurs in the sacrificial layer.

[0079] In the fifth step, a barrier metal layer (210) is formed under the semiconductor stripped from the substrate, as shown in 3E.

[0080] The barrier metal layer (210) is usually a metal composite layer and forms an ohmic contact with the upper semiconductor. The bonding barrier metal layer (210) may be formed by evaporation or sputtering.

[0081] In one embodiment, the barrier metal layer (210) is a titanium-nickel-silver composite layer, and its thickness is 500A-3kA, 1kA-5kA, 5kA-40kA respectively.

[0082] In one embodiment, the barrier metal layer (210) is a nickel-copper composite layer, and the thicknesses thereof are 500A-2um and 500A-5um respectively.

[0083] In one embodiment, the barrier metal layer (210) is a nickel-gold composite layer, and its thickness is 500A-2um and 500A-5kA respectively.

[0084] Before forming the barrier metal layer (210), the semiconductor may be firstly subjected to chemical cleaning and / or wet etching and / or plasma cleaning to remove impurities generated after the laser pulse process and provide a good semiconductor-metal bonding interface.

[0085] In the sixth step, a solderable thick metal base layer (201) is formed below the barrier metal layer (210), and the supporting layer (211) is removed, as shown in FIG3F.

[0086] In one embodiment, the solderable thick metal base layer (201) is mainly composed of copper, and its formation method is: firstly, a copper seed layer is formed by a deposition method, and then a copper main layer is formed by an electroplating method. Generally, the thickness of the copper seed layer is between 500 kA and 5 um, and the thickness of the copper main layer is between 5 um and 100 um. In some variant embodiments, the copper seed layer may contain impurities such as aluminum, magnesium, boron, calcium, nitrogen, etc. to improve the interlayer bonding strength.

[0087] In some alternative embodiments, the copper seed layer may contain impurities such as tin, titanium, nitrogen, indium, etc. to improve the ability to resist electromigration.

[0088] The seventh step is to form a top solderable metal layer (120), as shown in FIG3G.

[0089] In one embodiment, the top solderable metal layer (120) is a nickel-copper composite layer, which is first formed by evaporation, sputtering or chemical vapor deposition to form a 500A-2um nickel layer and a 500kA to 5um copper seed layer, and then formed by electroplating to form a 500A-5um copper main layer.

[0090] In the above-mentioned embodiment process, the solderable thick metal base layer (201) and the top solderable metal layer (120) are formed by different steps, which is conducive to adjusting the metal thickness separately. However, in some embodiments, the top solderable metal layer (120) may be formed by the same step, which is conducive to saving process difficulty and manufacturing cost, and is conducive to reducing wafer warpage.

[0091] In a variant embodiment, the support layer (211) is removed after the semiconductor base layer (100) is stripped in the fourth step. In the sixth step, a solderable thick metal base layer (201) and a top solderable metal layer (120) are simultaneously formed on the exposed top metal layer (110) and the barrier metal layer (210).

[0092] In another variant embodiment, the support layer (211) is removed after the barrier metal layer (210) is formed in the fifth step. In the sixth step, a solderable thick metal base layer (201) and a top solderable metal layer (120) are simultaneously formed on the exposed top metal layer (110) and the barrier metal layer (210).

[0093] In another variant embodiment, the supporting layer (211) is composed of a low-resistance material such as a semiconductor layer, an alloy material layer, etc. In the sixth step, a solderable thick metal base layer (201) and a top solderable metal layer (120) are simultaneously formed on the exposed supporting layer (211) and the barrier metal layer (210). The final device structure formed by this embodiment is shown in 4A.

[0094] In another variant embodiment, after the semiconductor base layer (100) is stripped in the fourth step, or after the barrier metal layer (210) is formed in the fifth step, the support layer (211) is patterned and photolithographically processed to remove part of the support layer (211). In the sixth step, a solderable thick metal base layer (201) and a top solderable metal layer (120) are simultaneously formed on the exposed top metal layer (110) and the barrier metal layer (210). After the thick metal base layer (201) and the top solderable metal layer (120) are formed, the structure of the embodiment is as shown in the schematic diagrams in 4B and 4C. Among them, the remaining support layer (211) may have multiple segments or be in an island shape and be evenly distributed on the wafer. The top solderable metal layer (120) may be thicker than the remaining support layer (211) and cover part of the remaining support layer (211), as shown in 4B; the top solderable metal layer (120) may be thinner than the remaining support layer (211) and be located between multiple sections of the remaining support layer (211), as shown in 4C. In some variant embodiments, the remaining support layer (211) may be composed of a low-resistance material such as a semiconductor layer or an alloy material layer.

[0095] The above method for simultaneously forming a solderable thick metal base layer (201) and a top solderable metal layer (120) may include an electroplating process and simultaneously forming a 5um-60um metal layer in the electroplating process.

[0096] Based on the method of forming a gallium nitride power device mentioned in the above embodiment, a compatible method of forming a peripheral structure of a gallium nitride power device chip is as follows:

[0097] In the first step, a semiconductor buffer layer (105) is formed on the semiconductor substrate layer (100), and then a gallium nitride drift region (101) is formed on the semiconductor buffer layer (105), as shown in 3A.

[0098] In the second step, a patterned passivation layer (207) is formed on the semiconductor, and has a passivation layer window area (213), as shown in 5A.

[0099] The passivation layer (207) may be an oxide, a nitride, or an organic compound, or a combination thereof, and is usually formed by deposition.

[0100] The method of forming the passivation layer window region (213) may be photolithography. In one embodiment, the width of the passivation layer window region (213) is between 30um and 200um.

[0101] The third step is to remove the semiconductor on the cutting road area (214) located in the middle of the passivation layer window area (213) and form a semiconductor trench, as shown in 5B.

[0102] Generally, the method of removing the semiconductor may be dry etching or wet etching, and the semiconductor trench formed after etching may have an opening shape that is larger at the top and smaller at the bottom. In one embodiment, the width of the semiconductor trench is between 20um and 100um.

[0103] The semiconductor trench usually completely penetrates the gallium nitride drift region (101), but in some embodiments, the semiconductor trench may not completely penetrate the gallium nitride drift region (101), and the trench depth is between 0.5um and 50um.

[0104] In the fourth step, a supporting layer (211) is formed on the wafer, and the supporting layer (211) material completely fills the semiconductor trench, as shown in 5C.

[0105] In the fifth step, a laser pulse process is performed to peel off the semiconductor from the semiconductor base layer (100), as shown in 5D.

[0106] In the sixth step, a barrier metal layer (210) and a solderable thick metal base layer (201) thereunder are formed, as shown in FIG5E.

[0107] As shown in FIG5E , the cutting path region ( 214 ) in the above structure is filled with the support layer ( 211 ) material, so in the subsequent chip cutting process, the semiconductor will not be cracked due to direct cutting.

[0108] In some embodiments, the support layer (211) material may be an organic polymer and remain on the periphery of the chip after the dicing process, as shown in 5F.

[0109] In some embodiments, the support layer (211) is made of a soft organic material that can reduce semiconductor edge stress.

[0110] The remaining support layer (211) material plays a role in protecting the peripheral area of ​​the chip, reducing packaging stress, and preventing the entry of peripheral pollutant ions.

[0111] Those skilled in the art should know that the above-mentioned embodiments of the peripheral structure and manufacturing process of the gallium nitride power device chip can be combined with more variation embodiments of the above-mentioned gallium nitride power device structure and manufacturing process to achieve more variations.

[0112] Those skilled in the art should know that the above manufacturing steps only list key steps and do not show the complete steps of forming a device. Specific detailed manufacturing steps can be obtained based on common manufacturing process steps and common sense knowledge in the field and can be appropriately increased, decreased or changed.

[0113] In addition, those skilled in the art should know that the structural features and process steps mentioned in the above-mentioned embodiments of the present invention can be combined with each other to form more device structures and manufacturing processes of embodiments of the present invention.

Claims

1. A chip structure for high-power packaging, the chip structure comprising a top metal layer disposed above a semiconductor device region and a top solderable metal layer disposed above the top metal layer, characterized in that: A barrier metal layer and a solderable thick metal base layer with a thickness of 5um-160um arranged below the barrier metal layer are provided below the semiconductor device area; the barrier metal layer is used to enhance the bonding strength of the thick metal base layer and prevent impurities from penetrating into the semiconductor device area, and the solderable thick metal base layer is used to provide a solderable metal interface, improve heat dissipation and block radioactive particles from below the device.

2. The chip structure for high-power packaging according to claim 1, characterized in that: A semiconductor buffer layer is also provided between the semiconductor device region and the barrier metal layer.

3. The chip structure for high-power packaging according to claim 2, characterized in that: The semiconductor buffer layer is a semiconductor composite layer containing nitrogen, aluminum, indium, gallium, carbon and / or magnesium elements.

4. The chip structure for high-power packaging according to claim 1, characterized in that: The top metal layer is also provided with a supporting layer made of a low-resistance material, the supporting layer completely covers the top metal layer, and the top weldable metal layer completely covers the supporting layer.

5. The chip structure for high-power packaging according to claim 1, characterized in that: The top metal layer is also provided with a supporting layer made of insulating material, the supporting layer covers part of the top metal layer, and the top metal layer and the top solderable metal layer are at least partially connected.

6. The chip structure for high-power packaging according to claim 1, characterized in that: A supporting layer made of insulating material is also provided above the chip and at the cutting positions between the chips.

7. The chip structure for high-power packaging according to claim 1, characterized in that: The thickness of the top metal layer is 1um-5um, or the thickness of the weldable metal layer is 5um-50um.

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