Conductive bump
By adding a barrier metal layer to the conductive bump and forming interfacial metal co-deposited substances, the poor co-planarity and nickel migration problems caused by probe marks of the solder bumps are solved, and better packaging quality and nickel layer stability are achieved.
Patent Information
- Application Number
- CN202422011250.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Priority Date
- 2023-11-29
- Filing Date
- 2024-08-19
- Publication Date
- 2025-06-10
- Estimated Expiration
- 2034-08-19
AI Technical Summary
The existing solder bumps are poor in coplanarity due to indentation of the test probe, which can easily cause non-wet problems during subsequent crystal-covered packaging. The nickel layer will migrate to the surface of the solder bump when the test is powered on, resulting in the inability to remove nickel.
In the production method of conductive bumps, a barrier metal layer (copper layer) is added and a first interface metal co-deposit and a second interface metal co-deposit are formed after the re-welding process to prevent the migration of metal (nickel).
By blocking metal migration, the co-planarity of the solder bumps is improved, the problem of unwetting is avoided, and the stability of the nickel layer is maintained.
Smart Images
Figure CN222966140U_ABST
Abstract
Description
Technical Field
[0001] This application relates to a conductive bump, particularly a conductive bump formed on a semiconductor substrate. Background Art
[0002] Compared with the wire bond technology, the flip chip package is characterized in that the electrical connection between the semiconductor chip and the package substrate is through solder bumps instead of ordinary gold wires. Using solder bumps as electrical connection components has the advantages of shortening the electrical conduction path, improving performance, providing a heat dissipation path, and reducing the volume of the package, so it has become a trend in packaging.
[0003] Please refer to Figures 1A to 1C , in the existing process of forming solder bumps on a wafer / chip, a copper layer (Cu) 11 / nickel layer (Ni) 12 / tin-silver alloy layer (Sn-Ag) 13 are sequentially formed on the solder pad 10, then a reflow process is performed, and then wafer-level testing (Wafer Sort) is carried out. At this time, the solder bumps have poor coplanarity due to the indentation 130 of the test probe and the melting of the solder, resulting in an easy non-wet problem during the flip chip operation.
[0004] To solve the problem of the indentation of the test probe, the industry then changes the order of the reflow process to after wafer-level testing. However, it is found that when wafer-level testing is first carried out, nickel will migrate to the surface of the solder bump during the test power-on, leaving marks and nickel cannot be removed after the test is completed.
[0005] Therefore, how to overcome the problems of the above-mentioned prior art has actually become an urgent issue to be solved currently. Summary of the Utility Model
[0006] In view of the deficiencies of the above-mentioned prior art, this application provides a conductive bump formed on a solder pad of a semiconductor substrate, which includes: a first metal layer, which is a copper layer, disposed on the solder pad; a second metal layer, which is a nickel layer, disposed on the first metal layer; a barrier metal layer, which is a copper layer, disposed on the second metal layer; and a third metal layer, which is a tin-silver alloy layer, disposed on the barrier metal layer.
[0007] The present application also provides a method for manufacturing conductive bumps: providing a semiconductor substrate having a plurality of pads, and forming a conductive metal layer covering the plurality of pads on the semiconductor substrate; forming a photoresist layer on the conductive metal layer, and making the photoresist layer form a plurality of openings, wherein each of the openings corresponds to the position of each of the pads; electroplating a first metal, a second metal layer, a barrier metal layer, and a third metal layer in sequence on the conductive metal layer in each of the openings, wherein the first metal layer is a copper layer, the second metal layer is a nickel layer, the barrier metal layer is a copper layer, and the third metal layer is a tin-silver alloy layer; removing the photoresist layer and the conductive metal layer covered by it; and performing a reflow process to form conductive bumps on each of the pads.
[0008] In the foregoing conductive bumps and manufacturing method, a fourth metal layer and a fifth metal layer are further sequentially formed between the second metal layer and the barrier metal layer, wherein the fourth metal layer is a tin-silver alloy layer and the fifth metal layer is a nickel layer.
[0009] In the foregoing conductive bumps and manufacturing method, a fourth metal layer is further formed between the second metal layer and the barrier metal layer, wherein the fourth metal layer is a tin-silver alloy layer.
[0010] In the foregoing conductive bumps and manufacturing method, after performing the reflow process, a first interfacial metal compound is formed between the second metal layer and the barrier metal layer, and a second interfacial metal compound is formed between the barrier metal layer and the third metal layer.
[0011] As can be seen from the above, in the conductive bumps and their manufacturing method of the present application, a barrier metal layer (copper layer) is mainly added between the third metal layer (tin-silver alloy layer) and the second metal layer (nickel layer), and after the reflow process, a first interfacial metal compound is formed between the second metal layer and the barrier metal layer, and a second interfacial metal compound is formed between the barrier metal layer and the third metal layer, so as to block the migration of metal (nickel), thereby solving the problems of poor coplanarity caused by probe marks in existing solder bumps, resulting in subsequent defects such as non-wetting. Description of the Drawings
[0012] Figures 1A to 1C It is a schematic cross-sectional view of the manufacturing process of an existing solder bump.
[0013] Figures 2A to 2F It is a schematic cross-sectional view of the manufacturing method of the first embodiment of the conductive bump of the present application.
[0014] Figure 3 It is a schematic cross-sectional view of the second embodiment of the conductive bump of the present application.
[0015] Figure 4 It is a schematic cross-sectional view of the third embodiment of the conductive bump of the present application.
[0016] Description of the Main Component Symbols
[0017] 10 Bonding Pad
[0018] 11 Copper Layer
[0019] 12 Nickel Layer
[0020] 13 Tin-Silver Alloy Layer
[0021] 130 Indentation
[0022] 2, 3, 4 Conductive Bumps
[0023] 20 Conductive Metal Layer
[0024] 21, 31, 41 First Metal Layer
[0025] 22, 32, 42 Second Metal Layer
[0026] 23, 33, 43 Third Metal Layer
[0027] 34, 44 Fourth Metal Layer
[0028] 35 Fifth Metal Layer
[0029] 50 Semiconductor Substrate
[0030] 500 Bonding Pad
[0031] 52 Insulating Layer
[0032] 520 Opening
[0033] 53 Photoresist Layer
[0034] 530 Opening
[0035] B2, B3, B4 Barrier Metal Layer
[0036] I1 First Interface Metal Compound
[0037] I2 Second Interface Metal Compound. Detailed Implementation Manner
[0038] The following illustrates the implementation manners of the present application through specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification.
[0039] It should be noted that the structures, proportions, sizes, etc. shown in the attached drawings of this specification are only used to cooperate with the content disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the implementation conditions of this application. Therefore, they do not have substantial technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size, without affecting the efficacy that this application can produce and the purpose that can be achieved, should still fall within the scope covered by the technical content disclosed in this application. At the same time, terms such as "upper", "first", "second", "one", etc. cited in this specification are only for the sake of clear narration and are not used to limit the scope that this application can implement. The change or adjustment of their relative relationship, without substantial change in the technical content, should also be regarded as the scope that this application can implement.
[0040] Please refer to Figures 2A to 2F , which is a schematic cross-sectional view of the first embodiment of the method for manufacturing the conductive bumps of this application. The conductive bumps are formed on a semiconductor substrate such as a wafer or a chip.
[0041] As Figure 2A shown, a semiconductor substrate 50 having a plurality of pads 500 is provided. Since the same processes are performed on each of the pads 500, only a single pad 500 is shown in the drawing.
[0042] In this embodiment, the semiconductor substrate 50 is a wafer, and in other embodiments, the semiconductor substrate 50 can also be a silicon substrate or a glass substrate. The semiconductor substrate 50 is covered with an insulating layer 52, and the insulating layer 52 has a plurality of openings 520 to expose each of the pads 500 corresponding to the openings 520. Furthermore, the material for forming the pad 500 can be aluminum, and the material for forming the insulating layer 52 can be silicon nitride (SiN) or silicon oxide compound (SiOX) as a passivation layer.
[0043] As Figure 2B shown, then a conductive metal layer 20 is formed on the insulating layer 52 and each of the pads 500. The conductive metal layer 20 serves as the current conduction path required for the subsequent electroplated metal material, and the material for forming the conductive metal layer 20 can be titanium / copper (Ti / Cu) or titanium / tungsten / copper (Ti / W / Cu).
[0044] As Figure 2C shown, a photoresist layer 53 is further formed on the conductive metal layer 20. Then, through the processes of exposure and development, a plurality of openings 530 are formed on the photoresist layer 53, and each of the openings 530 corresponds to the position of the pad, so that the conductive metal layer 20 on each of the pads 500 is exposed to each of the openings 530.
[0045] As Figure 2DAs shown, a first metal 21, a second metal layer 22, a barrier metal layer B2, and a third metal layer 23 are sequentially electroplated on the conductive metal layer 20 in each of the openings 530. In this embodiment, the first metal layer 21 is a copper (Cu) layer, the second metal layer 22 is a nickel (Ni) layer, the barrier metal layer B2 is a copper (Cu) layer, and the third metal layer 23 is a tin-silver alloy (SnAg) layer.
[0046] As Figure 2E shown, the photoresist layer 53 and the conductive metal layer 20 thereunder are removed.
[0047] In this embodiment, the conductive metal layer 20 remaining on the pad 500 can serve as an under bump metallization (UBM).
[0048] As Figure 2F shown, a reflow process is performed to form a first interfacial metal compound (IMC) I1 between the second metal layer 22 (nickel layer) and the barrier metal layer B2 (copper layer), and a second interfacial metal compound I2 between the barrier metal layer B2 (copper layer) and the third metal layer 23 (tin-silver alloy layer), so as to form the conductive bump 2 of the present application.
[0049] Accordingly, the conductive bump 2 of the present application mainly adds a barrier metal layer B2 (copper layer) between the third metal layer 23 (tin-silver alloy layer) and the second metal layer 22 (nickel layer), and forms a first interfacial metal compound I1 and a second interfacial metal compound I2 after the reflow process to block metal (nickel) migration, thereby solving the drawback that the existing solder bumps have poor coplanarity due to probe marks, resulting in subsequent non-wetting.
[0050] Please refer to Figure 3 , which is a cross-sectional schematic view of a second embodiment of the conductive bump 3 of the present application. The main difference between this embodiment and the first embodiment lies in the quantity and position changes of the metal layers and the barrier metal layer, and other related processes are substantially the same, so they will not be elaborated here.
[0051] In addition to including the aforementioned first metal layer (such as a copper layer) 31, second metal layer (such as a nickel layer) 32, barrier metal layer (such as a copper layer) B3, and third metal layer (such as a tin-silver alloy layer) 33, the conductive bump 3 of this embodiment further sequentially forms a fourth metal layer (such as a tin-silver alloy layer) 34 and a fifth metal layer (such as a nickel layer) 35 between the second metal layer (such as a nickel layer) 32 and the barrier metal layer (such as a copper layer) B3.
[0052] Please refer to Figure 4, which is a cross-sectional schematic diagram of the third embodiment of the conductive bump 4 of the present application. The main difference between this embodiment and the first embodiment lies in the number and position changes of the metal layer and the barrier metal layer. Since the other related processes are substantially the same, they will not be elaborated here.
[0053] In addition to the aforementioned first metal layer (such as a copper layer) 41, second metal layer (such as a nickel layer) 42, barrier metal layer (such as a copper layer) B4, and third metal layer (such as a tin-silver alloy layer) 43, the conductive bump 4 of this embodiment further forms a fourth metal layer (such as a tin-silver alloy layer) 44 between the second metal layer (such as a nickel layer) 42 and the barrier metal layer (such as a copper layer) B4.
[0054] In summary, the conductive bump of the present application and its manufacturing method mainly add a barrier metal layer to multiple metal layers and form an interfacial metal intermetallic compound after the reflow soldering process to block metal migration, thereby solving the problems of poor coplanarity caused by probe marks in existing solder bumps and subsequent non-wetting and other defects.
[0055] The above embodiments are only used to exemplarily illustrate the principles and effects of the present application, rather than to limit the present application. Any person skilled in the art can modify the above embodiments without departing from the spirit and scope of the present application. Therefore, the scope of the right protection of the present application shall be as listed in the claims.
Claims
1. A conductive bump formed on a pad of a semiconductor substrate, characterized in that: include: A first metal layer, which is a copper layer, is disposed on the pad; A second metal layer, which is a nickel layer, is disposed on the first metal layer; a barrier metal layer, which is a copper layer, disposed on the second metal layer; as well as The third metal layer, which is a tin-silver alloy layer, is disposed on the barrier metal layer.
2. The conductive bump according to claim 1, wherein: The conductive bump further includes a fourth metal layer and a fifth metal layer sequentially formed between the second metal layer and the barrier metal layer, wherein the fourth metal layer is a tin-silver alloy layer, and the fifth metal layer is a nickel layer.
3. The conductive bump according to claim 1, wherein: The conductive bump also includes a fourth metal layer formed between the second metal layer and the barrier metal layer, wherein the fourth metal layer is a tin-silver alloy layer.
4. The conductive bump according to claim 1, wherein: The conductive bump also includes a first interface metal compound formed between the second metal layer and the barrier metal layer, and a second interface metal compound formed between the barrier metal layer and the third metal layer.