Data transmitter and electronic equipment

Abstract

The embodiment of the utility model discloses a data transmitter and electronic equipment, and the data transmitter comprises an SST circuit which comprises a first slice unit, a second slice unit, a coupling unit and a receiving end; the first slicing unit is connected with the receiving end through the coupling unit, and the second slicing unit is connected with the receiving end through the coupling unit; the first slicing unit is used for sending a forward differential signal to a receiving end through the coupling unit, and the second slicing unit is used for sending a reverse differential signal to the receiving end through the coupling unit; the current injection circuit comprises a first injection circuit and a second injection circuit; the first injection circuit is arranged between the first slice unit and the coupling unit, and the second injection circuit is arranged between the second slice unit and the coupling unit; the current injection circuit is used for controlling injection current so as to increase the output differential amplitude between the forward differential signal output by the first slice unit and the reverse differential signal output by the second slice unit, and the circuit area is saved.

Description

Technical Field

[0001] This application relates to the technical field of data transmitters, and more particularly, to a data transmitter and an electronic device. Background Art

[0002] Currently, when a transceiver performs data transmission, the sending end converts externally input parallel data into serial data and then sends it to the receiving end. Generally speaking, the protocol stipulates that the output differential amplitude of the sending end is adjustable from 0.4V to 1.2V, and in order to resist wire loss during transmission, the serialized data needs to be sent to the receiving end through a data transmitter.

[0003] In related technologies, the main function of the data transmitter is to adjust the output differential amplitude. Common data transmitters include SST (Source-Series-Terminated) structures, CML (Current Model Logic) structures, etc. The SST structure adjusts the amplitude of the output terminal by the resistance values of the pull-up and pull-down resistors, and a switching transistor is introduced in each resistor adjustment module. However, under the protocol regulations, the terminal impedances of the sending end and the receiving end are equal, so the maximum differential amplitude of the sending end can only reach the power supply voltage VDD. In some low-process cases, the power supply voltage is mostly less than 1.2V, but when the protocol requires the output differential amplitude to be greater than 1.2V, it is difficult to meet the protocol requirements only by the SST structure. Summary of the Utility Model

[0004] To solve the above technical problems, embodiments of the present application provide a data transmitter and an electronic device, so as to be able to increase the output differential amplitude of the data transmitter.

[0005] According to one aspect of the embodiments of the present application, a data transmitter is provided, including: an SST circuit, including a first slicing unit, a second slicing unit, a coupling unit, and a receiving end; the first slicing unit is connected to the receiving end through the coupling unit, and the second slicing unit is connected to the receiving end through the coupling unit; the first slicing unit is configured to send a positive differential signal to the receiving end through the coupling unit, and the second slicing unit is configured to send a negative differential signal to the receiving end through the coupling unit;

[0006] A current injection circuit, including a first injection circuit and a second injection circuit; the first injection circuit is disposed between the first slicing unit and the coupling unit, and the second injection circuit is disposed between the second slicing unit and the coupling unit; the current injection circuit is configured to inject current in a controlled manner to increase the output differential amplitude between the positive differential signal output by the first slicing unit and the negative differential signal output by the second slicing unit.

[0007] In some embodiments, the data transmitter further includes a first voltage terminal and a ground terminal. The first slicing unit includes: a first PMOS transistor, a first NMOS transistor, a third resistor, and a fourth resistor;

[0008] The source of the first PMOS transistor is connected to the first voltage terminal. The drain of the first PMOS transistor is connected to one end of the third resistor. The other end of the third resistor is respectively connected to one end of the fourth resistor and the data output terminal of the first slicing unit. The other end of the fourth resistor is connected to the drain of the first NMOS transistor. The source of the first NMOS transistor is connected to the ground terminal. The gates of the first PMOS transistor and the first NMOS transistor are connected to the data input terminal of the first slicing unit.

[0009] In some embodiments, the data transmitter further includes a first voltage terminal and a ground terminal. The second slicing unit includes: a second PMOS transistor, a second NMOS transistor, a fifth resistor, and a sixth resistor. The source of the second PMOS transistor is connected to the first voltage terminal. The drain of the second PMOS transistor is connected to one end of the fifth resistor. The other end of the fifth resistor is respectively connected to one end of the sixth resistor and the data output terminal of the second slicing unit. The other end of the sixth resistor is connected to the drain of the second NMOS transistor. The source of the second NMOS transistor is connected to the ground terminal. The gates of the second PMOS transistor and the second NMOS transistor are connected to the data input terminal of the second slicing unit.

[0010] In some embodiments, the coupling unit includes two first capacitors and a second capacitor connected in parallel. The first slicing unit is connected to the receiving end through the coupling unit, including: the data output terminal of the first slicing unit is connected to the receiving end through the first capacitor;

[0011] The second slicing unit is connected to the receiving end through the coupling unit, including: the data output terminal of the second slicing unit is connected to the receiving end through the second capacitor.

[0012] In some embodiments, the data transmitter further includes a ground terminal. The receiving end includes two first resistors and a second resistor connected in parallel. One end of the first resistor is connected to the first capacitor. The other end of the first resistor is respectively connected to one end of the second resistor and the ground terminal. The other end of the second resistor is connected to the second capacitor. The first resistor and the second resistor are used to match the transmission medium channel impedance.

[0013] In some embodiments, the data transmitter further includes a second voltage terminal. The first injection circuit includes: a first current source. One end of the first current source is connected to the second voltage terminal. The other end of the first current source is respectively connected to the data output terminal of the first slicing unit, the third resistor, and the fourth resistor;

[0014] The second injection circuit includes: a second current source; one end of the second current source is connected to the second voltage terminal, and the other end of the second current source is respectively connected to the data output terminal of the second slicing unit, a fifth resistor, and a sixth resistor.

[0015] In some embodiments, both the first current source and the second current source are cascode current mirrors composed of PMOS transistors. The cascode current mirrors composed of PMOS transistors mirror a reference current to obtain the output currents of the first current source and the second current source.

[0016] In some embodiments, the first slicing unit includes: a first PMOS transistor, a first NMOS transistor, a third resistor, and a fourth resistor; the second slicing unit includes: a second PMOS transistor, a second NMOS transistor, a fifth resistor, and a sixth resistor;

[0017] The first injection circuit includes: a first current source; one end of the first current source is respectively connected to the source electrode of the first NMOS transistor and the ground terminal, and the other end of the first current source is respectively connected to the data output terminal of the first slicing unit, a third resistor, and a fourth resistor;

[0018] The second injection circuit includes: a second current source; one end of the second current source is respectively connected to the source electrode of the second NMOS transistor and the ground terminal, and the other end of the second current source is respectively connected to the data output terminal of the second slicing unit, a fifth resistor, and a sixth resistor.

[0019] In some embodiments, both the first current source and the second current source are cascode current mirrors composed of NMOS transistors. The cascode current mirrors composed of NMOS transistors mirror a reference current to obtain the output currents of the first current source and the second current source.

[0020] According to one aspect of the embodiments of the present application, an electronic device is provided, including the above data transmitter.

[0021] In the technical solution provided by the embodiments of the present application, by setting a current injection circuit before the data output terminal of each slicing unit in the SST circuit and controlling the current injection circuit, the output differential amplitude between the positive differential signal output by the first slicing unit and the negative differential signal output by the second slicing unit is increased, so that the output differential amplitude can exceed the power supply voltage.

[0022] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. Description of the Drawings

[0023] The accompanying drawings here are incorporated into the specification and form a part of this specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts. In the drawings:

[0024] Figure 1 is a circuit structure diagram of a data transmitter shown in an exemplary embodiment of the present application;

[0025] Figure 2 is a circuit structure diagram of a data transmitter without a current injection circuit shown in an exemplary embodiment of the present application;

[0026] Figure 3 is an application schematic diagram of the current flow direction of a data transmitter without a current injection circuit shown in an exemplary embodiment of the present application;

[0027] Figure 4 is an application schematic diagram of the current flow direction of a data transmitter without a current injection circuit shown in another exemplary embodiment of the present application;

[0028] Figure 5 is an application schematic diagram of the current direction of a data transmitter with a second injection circuit shown in an exemplary embodiment of the present application;

[0029] Figure 6 is an application schematic diagram of the current direction of a data transmitter with a first injection circuit shown in another exemplary embodiment of the present application;

[0030] Figure 7 is a circuit structure diagram of a data transmitter shown in another exemplary embodiment of the present application.

[0031] Reference numerals:

[0032] 1: First slicing unit 2: Second slicing unit; 3: Coupling unit; 4: Receiving end; 5: First injection circuit; 6: Second injection circuit. Detailed implementation manners

[0033] Here, the exemplary embodiments will be described in detail, and the examples are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numerals in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners of the present application. On the contrary, they are only examples of the devices and methods that are the same as some aspects of the present application as detailed in the appended claims.

[0034] The block diagrams shown in the drawings are only functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in the form of application programs, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0035] The flowcharts shown in the drawings are only illustrative and do not necessarily include all the content and operations / steps, nor do they have to be executed in the described order. For example, some operations / steps can be decomposed, while some operations / steps can be combined or partially combined, so the actual execution order may change according to the actual situation.

[0036] It should be noted that "a plurality of" mentioned in this application means two or more. "And / or" describes the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the front and rear associated objects.

[0037] The following is an introduction and explanation of the technical terms involved in this application:

[0038] The SST (source-series-terminated) circuit is a signal integrity technology commonly used in high-speed data transmission, mainly used to improve the quality and reliability of signals on the transmission line. The SST circuit matches the characteristic impedance of the transmission line by setting a termination resistor between the sending end and the receiving end, thereby reducing signal reflection and distortion. This technology is applicable to long-distance or high-rate signal transmission scenarios, such as backplane interconnection, inter-chip communication, etc.

[0039] TX transmit (sending end or transmitter), which is an important part of the data communication process. Specifically, TX is responsible for converting the data to be sent into electrical signals or optical signals and sending them out through the transmission medium (such as wires, optical fibers, etc.). In the communication system, TX is responsible for converting the data or information to be sent into a signal form suitable for transmission in the transmission medium, and then sending it to the receiving end (RX, Receiver).

[0040] Please refer to Figure 1 , Figure 1The following is a circuit structure diagram of a data transmitter shown in an exemplary embodiment of the present application. Among them, the data transmitter includes an SST circuit and a current injection circuit; the SST circuit includes a first slicing unit 1, a second slicing unit 2, a coupling unit 3, and a receiving end 4; the first slicing unit 1 is connected to the receiving end 4 through the coupling unit 3, and the second slicing unit 2 is connected to the receiving end 4 through the coupling unit 3; the first slicing unit 1 is used to send a positive differential signal to the receiving end 4 through the coupling unit 3, and the second slicing unit 2 is used to send a negative differential signal to the receiving end 4 through the coupling unit 3. The current injection circuit includes a first injection circuit 5 and a second injection circuit 6; the first injection circuit 5 is arranged between the first slicing unit 1 and the coupling unit 3, and the second injection circuit 6 is arranged between the second slicing unit 2 and the coupling unit 3; the current injection circuit is used to inject current in a controlled manner to increase the output differential amplitude between the positive differential signal output by the first slicing unit 1 and the negative differential signal output by the second slicing unit 2.

[0041] It can be understood that both the first current injection circuit and the second current injection circuit in the embodiment of the present application are arranged on one side of the pull-up resistor in the slicing unit. In this way, by only arranging the current injection circuit on one side, it is not necessary to arrange the current injection circuit on both sides of the pull-up resistor and the pull-down resistor, which can save the circuit area.

[0042] In some embodiments, the data transmitter further includes a first voltage terminal and a ground terminal. The first slicing unit includes: a first PMOS transistor M1, a first NMOS transistor M2, a third resistor R3, and a fourth resistor R4. The source of the first PMOS transistor M1 is connected to the first voltage terminal, the drain of the first PMOS transistor M1 is connected to one end of the third resistor R3, and the other end of the third resistor R3 is respectively connected to one end of the fourth resistor R4 and the data output terminal of the first slicing unit; the other end of the fourth resistor R4 is connected to the drain of the first NMOS transistor M2, and the source of the first NMOS transistor M2 is connected to the ground terminal; the gates of the first PMOS transistor M1 and the first NMOS transistor M2 are connected to the data input terminal of the first slicing unit.

[0043] In the embodiment of the present application, as Figure 1 shown, the first voltage terminal is vptx, vptx is the core voltage of 0.9V, the data input terminal of the first slicing unit is data_p, and the data output terminal of the first slicing unit is tx_m. The input signal is received through the data input terminal data_p of the first slicing unit, and then the positive differential signal is output through the data output terminal tx_m of the first slicing unit and sent to the receiving end through the coupling unit.

[0044] In some embodiments, the data transmitter further includes a first voltage terminal and a ground terminal. The second slicing unit includes: a second PMOS transistor M3, a second NMOS transistor M4, a fifth resistor R5, and a sixth resistor R6. The source of the second PMOS transistor M3 is connected to the first voltage terminal, the drain of the second PMOS transistor M3 is connected to one end of the fifth resistor R5, and the other end of the fifth resistor R5 is respectively connected to one end of the sixth resistor R6 and the data output terminal of the second slicing unit; the other end of the sixth resistor R6 is connected to the drain of the second NMOS transistor M4, and the source of the second NMOS transistor M4 is connected to the ground terminal; the gates of the second PMOS transistor M3 and the second NMOS transistor M4 are connected to the data input terminal of the second slicing unit.

[0045] In the embodiments of the present application, as Figure 1 shown, the data input terminal of the second slicing unit is data_m, and the data output terminal of the first slicing unit is tx_p. The input signal is received through the data input terminal data_m of the second slicing unit, and then the inverted differential signal is output through the data output terminal tx_m of the second slicing unit, and then sent to the receiving end through the coupling unit.

[0046] In some embodiments, the coupling unit 3 includes two first capacitors C1 and C2 connected in parallel; the first slicing unit 1 is connected to the receiving end 4 through the coupling unit 3, including: the data output terminal of the first slicing unit 1 is connected to the receiving end 4 through the first capacitor C1; the second slicing unit 2 is connected to the receiving end 4 through the coupling unit 3, including: the data output terminal of the second slicing unit 2 is connected to the receiving end 4 through the second capacitor C2.

[0047] It can be understood that the coupling unit in the embodiments of the present application is an AC coupling unit, and according to actual requirements, the coupling unit can also be set as a DC coupling unit.

[0048] In some embodiments, the receiving end 4 includes two first resistors R1 and R2 connected in parallel; one end of the first resistor R1 is connected to the first capacitor C1, the other end of the first resistor R1 is respectively connected to one end of the second resistor R2 and the ground terminal, and the other end of the second resistor R2 is connected to the second capacitor C2; the first resistor R1 and the second resistor R2 are used to match the channel impedance of the transmission medium.

[0049] In the embodiments of the present application, in order to reduce signal reflection, by configuring the first resistor R1 and the second resistor R2 at the receiving end, the channel impedance of the transmission medium can be matched, thereby improving the signal transmission quality. In some embodiments, the resistance values of the first resistor R1 and the second resistor R2 are both 50 ohms, and the connection method of the receiving end can be selected according to actual requirements, such as grounding or connecting to the common mode.

[0050] In some embodiments, as Figure 1As shown, the current injection circuit includes a first injection circuit 5 and a second injection circuit 6. Among them, the first injection circuit 5 includes: a first current source iboost1; one end of the first current source iboost1 is connected to the second voltage terminal, and the other end of the first current source iboost1 is respectively connected to the data output terminal of the first slicing unit 1, the third resistor R3, and the fourth resistor R4. The second injection circuit 6 includes: a second current source iboost2; one end of the second current source iboost2 is connected to the second voltage terminal, and the other end of the second current source iboost2 is respectively connected to the data output terminal of the second slicing unit 2, the fifth resistor R5, and the sixth resistor R6.

[0051] It can be understood that the first current injection circuit in the embodiment of the present application is arranged on one side of the pull-up resistor in the first slicing unit, that is, one side of the third resistor R3, and the second current injection circuit is arranged on one side of the pull-up resistor in the second slicing unit, that is, one side of the fifth resistor R5; in this way, by only arranging the current injection circuit on one side, not only can the differential output amplitude be adjusted, but also the circuit area can be saved, and there is no need to arrange current injection circuits on both the pull-up resistor and the pull-down resistor.

[0052] For example, in combination with Figures 2 to 4 shown, Figure 2 is the circuit structure diagram of a data transmitter without a current injection circuit shown in an exemplary embodiment of the present application, Figure 3 is the application schematic diagram of the current flow without a current injection circuit shown in an exemplary embodiment of the present application, Figure 4 is the application schematic diagram of the current flow without a current injection circuit shown in another exemplary embodiment of the present application. Figure 2 In , the data transmitter is an SST circuit, including a first slicing unit 1, a second slicing unit 2, a coupling unit 3, and a receiving end 4. The data input terminal of the first slicing unit 1 is data_p, and the data output terminal is tx_m. The data input terminal of the second slicing unit 2 is data_m, and the data output terminal is tx_p.

[0053] Exemplarily, as Figure 3As shown, when the input signal of the data input terminal data_p of the first slicing unit is high level 1 and the input signal of the data input terminal data_m of the second slicing unit is low level 0, at this time, the first PMOS transistor M1 in the first slicing unit 1 is turned off, and the first NMOS transistor M2 is turned on; the second PMOS transistor of the second slicing unit 2 is turned on, and the second NMOS transistor M4 is turned off. Since the switch is off in the shaded area, no current passes through. At this time, the current in the circuit flows from the first voltage terminal vptx through the second PMOS transistor M3 and the fifth resistor R5, then through the second capacitor C2 and the second resistor R2, flows through the first resistor R1, then through the first capacitor C1 to the fourth resistor R4 in the first slicing unit, and then reaches the ground terminal through the first NMOS transistor M2; at this time, the current direction is from the second resistor R2 to the first resistor R1, the voltage of the data output terminal tx_p of the second slicing unit is 3 / 4×vptx, and the voltage of the data output terminal tx_m of the first slicing unit is 1 / 4×vptx.

[0054] Exemplarily, as Figure 4 shown, when the input signal of the circuit data input terminal data_p of the first slicing unit is low level 0 and the input signal of the data input terminal data_m of the second slicing unit is high level 1, at this time, the first PMOS transistor M1 in the first slicing unit 1 is turned on, and the first NMOS transistor M2 is turned off; the second PMOS transistor of the second slicing unit 2 is turned off, and the second NMOS transistor M4 is turned on. Since the switch is off in the shaded area, no current passes through. At this time, the current in the circuit flows from the first voltage terminal vptx through the first PMOS transistor M1 and the third resistor R3, then through the first capacitor C1 and the first resistor R1, flows through the second resistor R2, then through the second capacitor C2 to the sixth resistor R6 in the second slicing unit, and then reaches the ground terminal through the second NMOS transistor M4; at this time, the current flows from R1 to R2, the voltage of the data output terminal tx_p of the second slicing unit is 1 / 4×vptx, and the voltage of the data output terminal tx_m of the first slicing unit is 3 / 4×vptx. It can be seen that in the data transmitter without the current injection circuit, the total differential output voltage amplitude is at most the voltage of the first voltage terminal, that is, the core voltage vptx 0.9v.

[0055] In the embodiment of the present application, by arranging current injection circuits, namely the first current injection circuit and the second current injection circuit, on one side of the slicing unit in the SST circuit, the output differential amplitude between the positive differential signal output by the first slicing unit 1 and the negative differential signal output by the second slicing unit 2 can be increased.

[0056] Exemplarily, in combination with Figure 5 shown, Figure 5It is an application schematic diagram showing the current direction of the second injection circuit shown in an exemplary embodiment of the present application; when the input signal of the data input terminal data_p of the first slicing unit is high level 1 and the input signal of the data input terminal data_m of the second slicing unit is low level 0, the current direction is from R2 to R1 at this time. In the embodiment of the present application, the resistance value of M3 + R5 is 50 ohms, the resistance value of R4 + M2 is 50 ohms, and the resistance values of R1 and R2 are 50 ohms respectively. At this time, through we can obtain , and through calculation we get that the voltage of the data output terminal tx_p of the second slicing unit is ; where, vptx is the voltage magnitude of the first voltage terminal, which is the core voltage 0.9v, Vtx_p is the voltage magnitude of the data output terminal tx_p of the second slicing unit, and iboost2 is the current magnitude output by the second current source. Then through calculation we get the voltage of the data output terminal tx_m of the first slicing unit, where, Vtx_m is the voltage magnitude of the data output terminal tx_m of the first slicing unit. Then through calculation we get the output differential amplitude when data_p is high level 1 and data_m is low level 0.

[0057] Similarly, in combination with Figure 6 shown, Figure 6 It is an application schematic diagram showing the current direction of the first injection circuit shown in another exemplary embodiment of the present application; when the input signal of the data input terminal data_p of the first slicing unit is low level 0 and the input signal of the data input terminal data_m of the second slicing unit is high level 1, the current flows from R1 to R2. In the embodiment of the present application, the resistance value of M1 + R3 is 50 ohms, the resistance value of R6 + M4 is 50 ohms, and the resistance values of R1 and R2 are 50 ohms respectively. At this time, through we can obtain , and through calculation we get that the voltage of the data output terminal tx_m of the first slicing unit is ; where, vptx is the voltage magnitude of the first voltage terminal, which is the core voltage 0.9v, Vtx_m is the voltage magnitude of the data output terminal tx_m of the first slicing unit, and iboost1 is the current magnitude output by the first current source. Then through calculation we get the voltage of the data output terminal tx_p of the second slicing unit, where, Vtx_p is the voltage magnitude of the data output terminal tx_p of the second slicing unit. Then through calculation we get the output differential amplitude when data_p is low level 0 and data_m is high level 1.

[0058] In the embodiment of the present application, the current magnitude iboost1 of the first current source is the same as the current magnitude iboost2 of the second current source. Therefore, the total output differential amplitude is or . It can be seen from this formula that after the current injection circuit is set, the total output differential amplitude is . Without the current injection circuit, the maximum differential amplitude is the voltage of the first voltage terminal, that is, vptx0.9v. It can be seen that 50iboost is the output amplitude exceeding the power supply voltage. In the embodiment of the present application, the voltage magnitude of the second voltage terminal connected to the current source of the injection circuit is greater than the voltage magnitude of the first voltage terminal. The second voltage terminal is vph, that is, the IO voltage 1.8v. Therefore, on the basis of the SST circuit of the present application, after the current injection circuit is set, the differential output amplitude of the data transmitter can exceed the power supply voltage vptx specified by the protocol, so as to achieve the effect of increasing the output differential amplitude.

[0059] In some embodiments, the second voltage terminal is vph, and vph is the IO voltage 1.8v; both the first current source and the second current source are cascode current mirrors composed of PMOS transistors. By mirroring the reference current through the cascode current mirrors composed of PMOS transistors, the output currents of the first current source and the second current source are obtained.

[0060] For example, when the first voltage terminal vptx is the core voltage 0.9v and the second voltage terminal vph is the IO voltage 1.8v, by setting the structure of the current mirror as the cascode current mirror structure, the current replication can be made more accurate, so as to obtain a more accurate output current.

[0061] In some embodiments, as shown in Figure 7 shown Figure 7It is the circuit structure diagram of the data transmitter shown in another exemplary embodiment of the present application. Among them, the first slicing unit includes: a first PMOS transistor, a first NMOS transistor, a third resistor, and a fourth resistor; the second slicing unit includes: a second PMOS transistor, a second NMOS transistor, a fifth resistor, and a sixth resistor; the current injection circuit includes a first injection circuit 5 and a second injection circuit 6. The first injection circuit 5 includes: a first current source iboost1; one end of the first current source iboost1 is respectively connected to the source electrode of the first NMOS transistor M2 and the ground terminal, and the other end of the first current source iboost1 is respectively connected to the data output terminal of the first slicing unit 1, the third resistor R3, and the fourth resistor R4. The second injection circuit 6 includes: a second current source iboost2; one end of the second current source iboost2 is respectively connected to the source electrode of the second NMOS transistor M4 and the ground terminal, and the other end of the second current source iboost2 is respectively connected to the data output terminal of the second slicing unit 2, the fifth resistor R5, and the sixth resistor R6.

[0062] It can be understood that the first current injection circuit in the embodiment of the present application is arranged on one side of the pull-down resistor in the first slicing unit, that is, one side of the fourth resistor R4, and the second current injection circuit is arranged on one side of the pull-down resistor in the second slicing unit, that is, one side of the sixth resistor R6; in this way, by only arranging the current injection circuit on one side, it is not necessary to arrange the current injection circuit on both sides of the pull-up resistor and the pull-down resistor, which can save the circuit area.

[0063] In some embodiments, both the first current source and the second current source are cascode current mirrors composed of NMOS transistors. The cascode current mirrors composed of NMOS transistors mirror the reference current to obtain the output current of the first current source and the output current of the second current source. In this way, through the above two embodiments, not only can the output current of the current source be obtained by mirroring with P transistors, but also the corresponding output current can be obtained by mirroring with N transistors, both of which can improve the output differential amplitude of the data transmitter, so that the output differential amplitude of the data transmitter can exceed the power supply voltage to meet the output differential amplitude specified by the protocol. Moreover, in the data transmitter of the present application, the current injection circuit is only arranged on one side of each slicing unit in the SST circuit, that is, on the pull-up resistor side or the pull-down resistor side, which can achieve the effect of saving the circuit area.

[0064] The embodiment of the present application also provides an electronic device, including the data transmitter provided in each of the above embodiments.

[0065] The above content is only a preferred exemplary embodiment of the present application and is not intended to limit the implementation of the present application. Those of ordinary skill in the art can easily make corresponding adaptations or modifications according to the main concept and spirit of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope required by the claims.

Claims

1. A data transmitter, characterized in that: include: The SST circuit comprises a first slicing unit, a second slicing unit, a coupling unit and a receiving end; the first slicing unit is connected to the receiving end through the coupling unit, and the second slicing unit is connected to the receiving end through the coupling unit; the first slicing unit is used to send a forward differential signal to the receiving end through the coupling unit, and the second slicing unit is used to send a reverse differential signal to the receiving end through the coupling unit; A current injection circuit comprises a first injection circuit and a second injection circuit; the first injection circuit is arranged between the first slice unit and the coupling unit, and the second injection circuit is arranged between the second slice unit and the coupling unit; the current injection circuit is used for controlled injection of current to increase the output differential amplitude between the forward differential signal output by the first slice unit and the reverse differential signal output by the second slice unit.

2. The data transmitter according to claim 1, characterized in that The data transmitter further includes a first voltage terminal and a ground terminal, and the first slice unit includes: a first PMOS transistor, a first NMOS transistor, a third resistor and a fourth resistor; The source of the first PMOS tube is connected to the first voltage end, the drain of the first PMOS tube is connected to one end of the third resistor, and the other end of the third resistor is respectively connected to one end of the fourth resistor and the data output end of the first slice unit; the other end of the fourth resistor is connected to the drain of the first NMOS tube, and the source of the first NMOS tube is connected to the ground end; the gate of the first PMOS tube and the gate of the first NMOS tube are connected to the data input end of the first slice unit.

3. The data transmitter according to claim 1, characterized in that The data transmitter also includes a first voltage terminal and a ground terminal, and the second slice unit includes: a second PMOS tube, a second NMOS tube, a fifth resistor and a sixth resistor; the source of the second PMOS tube is connected to the first voltage terminal, the drain of the second PMOS tube is connected to one end of the fifth resistor, and the other end of the fifth resistor is respectively connected to one end of the sixth resistor and the data output terminal of the second slice unit; the other end of the sixth resistor is connected to the drain of the second NMOS tube, and the source of the second NMOS tube is connected to the ground terminal; the gate of the second PMOS tube and the gate of the second NMOS tube are connected to the data input terminal of the second slice unit.

4. The data transmitter according to claim 1, characterized in that: The coupling unit includes two first capacitors and a second capacitor connected in parallel; The first slicing unit is connected to the receiving end through the coupling unit, including: a data output end of the first slicing unit is connected to the receiving end through the first capacitor; The second slice unit is connected to the receiving end through the coupling unit, including: a data output end of the second slice unit is connected to the receiving end through the second capacitor.

5. The data transmitter according to claim 4, characterized in that: The data transmitter also includes a ground terminal; the receiving terminal includes two parallel first resistors and a second resistor; one end of the first resistor is connected to the first capacitor, the other end of the first resistor is respectively connected to one end of the second resistor and the ground terminal, and the other end of the second resistor is connected to the second capacitor; the first resistor and the second resistor are used to match the transmission medium channel impedance.

6. The data transmitter according to claim 1, characterized in that: The data transmitter further includes a second voltage terminal, and the first injection circuit includes: a first current source, one end of the first current source is connected to the second voltage terminal, and the other end of the first current source is respectively connected to the data output terminal of the first slice unit, the third resistor and the fourth resistor; The second injection circuit includes: a second current source; one end of the second current source is connected to the second voltage end, and the other end of the second current source is respectively connected to the data output end of the second slice unit, the fifth resistor and the sixth resistor.

7. The data transmitter according to claim 6, characterized in that The first current source and the second current source are both cascode current mirrors formed by PMOS tubes, and the cascode current mirrors formed by the PMOS tubes mirror the reference current to obtain the output current of the first current source and the output current of the second current source.

8. The data transmitter according to claim 1, characterized in that: The first slicing unit includes: a first PMOS tube, a first NMOS tube, a third resistor and a fourth resistor; the second slicing unit includes: a second PMOS tube, a second NMOS tube, a fifth resistor and a sixth resistor; The first injection circuit includes: a first current source; one end of the first current source is respectively connected to the source electrode and the ground end of the first NMOS tube, and the other end of the first current source is respectively connected to the data output end of the first slice unit, the third resistor and the fourth resistor; The second injection circuit includes: a second current source; one end of the second current source is respectively connected to the source and ground of the second NMOS tube, and the other end of the second current source is respectively connected to the data output end, the fifth resistor and the sixth resistor of the second slice unit.

9. The data transmitter according to claim 8, characterized in that: The first current source and the second current source are both cascode current mirrors formed by NMOS tubes, and the cascode current mirrors formed by the NMOS tubes mirror the reference current to obtain the output current of the first current source and the output current of the second current source.

10. An electronic device, characterized in that: Comprising the data transmitter as claimed in any one of claims 1 to 9.

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