SiC MOSFET integrated with hybrid body diode

Abstract

The utility model discloses a SiC MOSFET integrated with a hybrid body diode, and relates to the technical field of semiconductors. According to the utility model, the SBD diode and the PN junction diode are integrated in the trench gate SiC MOSFET device to form a hybrid body diode, so that the improvement of long-term stable use of the device is realized. In the Is follow current process, the SBD body diode is started as a follow current tube in advance, so that a bipolar degradation effect caused by the fact that holes enter the SiC Drift layer is avoided; and when the device passes through Issm large surge current, the PN junction body diode is turned on, so that the large surge current impact bearing capability of the device is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a SiC MOSFETT with an integrated hybrid body diode. Background Technique

[0002] In the current social environment of energy conservation and emission reduction, the conversion and transmission of electric energy are more convenient than traditional fossil energy and more in line with the current social situation. However, as power electronic systems develop towards higher voltages and higher powers, the performance of traditional Si-based power devices has approached the theoretical limit of the material and it is difficult to meet the usage conditions under more stringent working conditions. Compared with traditional Si materials, SiC materials have a series of characteristic advantages such as a large bandgap width, a high critical breakdown electric field, a small intrinsic carrier concentration, a fast saturated drift velocity, a high melting point, and a high thermal conductivity. Therefore, it has great advantages in application fields such as high voltage, high temperature, and high frequency, and has great application prospects in future new energy vehicles, photovoltaic energy storage, charging piles, etc.

[0003] The SiC MOSFET device is the core product of SiC power devices. It has both excellent conduction characteristics and switching characteristics, so it can directly replace Si IGBT devices in high-power fields. And there is usually a parasitic PN junction body diode inside the SiC MOSFET to achieve freewheeling protection for the device. This design reduces the device usage of the diode and lowers the cost compared with the method of additionally anti-parallel connecting a freewheeling diode to the Si IGBT device. However, there are also certain risks in the PN junction body diode inside the SiC MOSFET. During the freewheeling process, the operation of the PN junction body diode will cause holes in the P region to enter the SiC Drift layer, resulting in the recombination of holes and electrons, thereby causing the spread of lattice defects in the SiC Drift layer and deteriorating the device performance. This phenomenon is called the bipolar degradation effect, which has great risks for the long-term use of the device. Therefore, how to improve the bipolar degradation effect of SiC MOSFET has a great impact on the performance stability and long-term use of the device. Content of the Utility Model

[0004] Aiming at the above problems, the utility model provides a SiC MOSFETT with an integrated hybrid body diode that avoids the bipolar degradation effect caused by holes entering the SiC Drift layer during the Is freewheeling process; and improves the ability of the device to withstand large surge current impacts during the Issm large surge current.

[0005] The technical solution of the utility model is:

[0006] The SiC MOSFETT with an integrated hybrid body diode includes a SiC Sub layer, a SiC Drift layer, a CSL layer, a second ohmic contact layer, and a front electrode metal layer arranged from bottom to top;

[0007] The top surface of the CSL layer is provided with:

[0008] A Schottky contact layer, formed at the middle position of the top surface of the CSL layer;

[0009] A P-body layer, deposited on the top surface of the CSL layer;

[0010] A P+ region, formed on the top surface of the CSL layer and connected to the P-body layer and the Schottky contact layer; the P+ region extends to the top surface of the Schottky contact layer;

[0011] An NP layer, deposited on the top surfaces of the P-body layer and the P+ region;

[0012] A first ohmic contact layer, formed on the Schottky contact layer, with its side connected to the NP layer and the P+ region, and its top surface located above the NP layer;

[0013] A P-shield region, arranged below the CSL layer, used for shielding the electric field and protecting the gate oxide layer;

[0014] A gate oxide layer, with a U-shaped cross-section, extending downward from the top surface of the NP layer, sequentially passing through the NP layer, the P-body layer, and the CSL layer, and then connecting to the P-shield region;

[0015] A Poly layer, filled in the gate oxide layer; an isolation dielectric layer, deposited on the Poly layer, used for isolating the gate electrode and the source electrode of the SiCMOSFET, with its bottom surface connected to the NP layer, the gate oxide layer, and the Poly layer respectively.

[0016] Specifically, the distance from the bottom surface of the gate oxide layer to the bottom surface of the CSL layer is 0.3 um - 1.2 um.

[0017] Specifically, the thickness of the gate oxide layer is 30 nm - 80 nm.

[0018] Specifically, the sputtering thickness of the Schottky contact layer is 0.1 um - 0.3 um.

[0019] Specifically, the thickness of the P-body layer is 0.3 um - 1 um.

[0020] Advantages of the present utility model:

[0021] 1. Reduce the bipolar degradation effect of the device and improve the long-term use stability of the device:

[0022] Since the SiC MOSFET device usually parasitically has a PN junction body diode inside, the freewheeling protection of the device is realized. However, during the use of the PN junction body diode, holes in the P region are likely to enter the SiC Drift layer, resulting in the recombination of holes and electrons, causing the lattice defects in the SiC Drift layer to spread and deteriorating the device performance. This phenomenon is called the bipolar degradation effect of SiC MOSFET. The utility model integrates a hybrid body diode, namely an SBD diode and a PN junction diode, inside the trench SiC MOSFET device. During the Is freewheeling process, the SBD diode is turned on as a current discharge path, thus avoiding the occurrence of the bipolar degradation effect and improving the performance stability of the device during long-term use.

[0023] 2. Improve the surge current impact resistance of the device:

[0024] Surge current is usually generated during the switching process of the system circuit. Therefore, power devices need to have a certain ability to withstand surge current impact to ensure that the devices are not damaged. The utility model integrates a hybrid body diode, namely an SBD diode and a PN junction diode, inside the trench SiC MOSFET. Since the PN junction diode has an ohmic contact prepared inside the device, under the impact of the Issm large surge current, the PN junction diode is turned on as a current discharge path, making the current discharge path of the device change from the original single SBD diode to the SBD and PN junction diodes, thus improving the surge current impact resistance of the device. Description of the Drawings

[0025] Figure 1 is a schematic structural diagram of the trench-gate SiC MOSFET of the utility model;

[0026] Figure 2 is a schematic structural diagram of step S100 of the utility model;

[0027] Figure 3 is a schematic structural diagram of step S200 of the utility model;

[0028] Figure 4 is a schematic structural diagram of step S300 of the utility model;

[0029] Figure 5 is a schematic structural diagram of step S400 of the utility model;

[0030] Figure 6 is a schematic structural diagram of step S500 of the utility model;

[0031] Figure 7 is a schematic structural diagram of step S600 of the utility model;

[0032] Figure 8It is a schematic structural diagram of step S700 of the present utility model;

[0033] Figure 9 It is a schematic structural diagram of step S800 of the present utility model;

[0034] Figure 10 It is a schematic structural diagram of step S900 of the present utility model;

[0035] Figure 11 It is a schematic structural diagram of step S1000 of the present utility model;

[0036] Figure 12 It is a schematic structural diagram of step S1100 of the present utility model;

[0037] Figure 13 It is a schematic structural diagram of step S1200 of the present utility model;

[0038] Figure 14 It is a schematic structural diagram of step S1300 of the present utility model;

[0039] Figure 15 It is a schematic structural diagram of step S1400 of the present utility model;

[0040] In the figure, 1 is the SiC Sub layer, 2 is the SiC Drift layer, 3 is the CSL layer, 4 is the Schottky contact layer, 5 is the P-body layer, 6 is the P+ region, 7 is the NP layer, 8 is the first ohmic contact layer, 9 is the P-shield region, 10 is the gate oxide layer, 11 is the Poly layer, 12 is the isolation dielectric layer, 13 is the second ohmic contact layer, and 14 is the front electrode metal layer. Detailed implementation manners

[0041] The present utility model will be described in detail below in combination with specific actual cases. Examples of the embodiments are shown in the drawings. The illustrative embodiments and descriptions thereof of the present utility model are only used to explain the present utility model and shall not be construed as a limitation to the present utility model.

[0042] In the description of the present utility model, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "left", "right", "vertical", "horizontal", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present utility model. In the description of the present utility model, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0043] In the description of the present utility model, it should be noted that unless otherwise clearly specified and defined, the terms "installation", "connection", and "coupling" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.

[0044] A preparation method of an integrated hybrid body diode SiC MOSFETT includes the following steps:

[0045] S100, epitaxially deposit a SiC Drift layer 2 on the top surface of the SiC Sub layer 1. The SiC Sub layer 1 serves as a support, and the SiC Drift layer 2 serves as a protection; as Figure 2 shown;

[0046] The thickness of the SiC Sub layer 1 in step S100 is 100um - 450um, and the doping concentration is 1E19cm -2 , the thickness of the SiC Drift layer 2 is 3um - 15um, and the doping concentration is 1E15 - 5E16cm -2 .

[0047] S200, epitaxially deposit a CSL layer 3 on the top surface of the SiC Drift layer 2 to reduce the device resistance through the CSL layer 3; as Figure 3 shown;

[0048] The thickness of the CSL layer 3 in step S200 is 0.8um - 3um, and the doping concentration is 1E17 - 5E18cm -2 .

[0049] S300, form a Schottky contact layer 4 on the top surface of the CSL layer 3 by Ti metal sputtering or annealing after deposition. The function of the Schottky contact layer 4 is to form an SBD body diode inside the SiC MOSFET; as Figure 4 shown;

[0050] The thickness of the Ti metal sputtering in step S300 is 0.1um - 0.3um.

[0051] S400, epitaxially deposit a P-body layer 5 on the top surfaces of the CSL layer 3 and the Schottky contact layer 4; as Figure 5 shown;

[0052] The thickness of the P-body layer 5 in step S400 is 0.3um - 1um, and the doping concentration is 1E17 - 5E18cm -2 .

[0053] S500, locally form a heavily doped P+ region 6 on the P-body layer 5 by Al ion implantation; as Figure 6 shown;

[0054] The doping concentration of the P+ region 6 in step S500 is 1E18 - 5E19 cm -2 .

[0055] S600, epitaxially deposit a layer of NP layer 7 on the top surface of the P-body layer 5; as Figure 7 shown;

[0056] The thickness of the NP layer 7 in step S600 is 0.3 um - 1 um, and the doping concentration is 1E17 - 5E18 cm -2 .

[0057] S700, form a first ohmic contact layer 8 on the top surface of the Schottky contact layer 4 by Ni metal sputtering or deposition followed by annealing. The function of the first ohmic contact layer 8 is to form a PN body diode inside the SiC MOSFET; as Figure 8 shown;

[0058] The thickness of the Ni metal sputtering in step S700 is 0.8 um - 2 um.

[0059] S800, form trenches on the upper surfaces of the NP layer 7, P-body layer 5, CSL layer 3, and SiC Drift layer 2 by etching. The bottom of the trenches extends into the SiC Drift layer 2; as Figure 9 shown;

[0060] The depth of the bottom surface of the trenches in step S800 from the bottom surface of the CSL layer 3 is 0.3 um - 1.2 um.

[0061] S900, form a heavily doped P-shield region 9 at the bottom of the trenches by Al ion implantation. The function of the P-shield region 9 is to shield the electric field and protect the gate oxide layer; as Figure 10 shown;

[0062] The doping concentration of the P-shield region 9 in step S900 is 1E18 - 5E19 cm -2 ;

[0063] S1000, form a layer of gate oxide layer 10 on the inner wall of the trenches by dry oxidation; as Figure 11 shown;

[0064] The thickness of the gate oxide layer 10 in step S1000 is 30 nm - 80 nm.

[0065] S1100, form Poly layer 11 by polysilicon deposition inside the trench. The function of Poly layer 11 is to be used as the gate electrode of the SiC MOSFET; as Figure 12 shown;

[0066] S1200, form isolation dielectric layer 12 by oxide deposition on the top surfaces of NP layer 7 and Poly layer 11. The function of isolation dielectric layer 12 is to isolate the gate electrode and source electrode of the SiC MOSFET and prevent short - circuit between them; as Figure 13 shown;

[0067] S1300, form the second ohmic contact layer 13 again on the top surfaces of NP layer 7 and the first ohmic contact layer 8 by Ni metal sputtering or annealing after deposition; as Figure 14 shown;

[0068] The thickness of Ni metal sputtering in step S1300 is 0.3um - 1um.

[0069] S1400, form the front - side electrode metal layer 14 on the top of the SiC MOSFET by sputtering Ti and AlCu metals; as Figure 15 shown;

[0070] The thickness of Ti metal in step S1400 is 0.1um - 0.5um, and the thickness of AlCu metal is 2um - 5um.

[0071] The integrated hybrid - type body diode SiC MOSFETT includes an SiC Sub layer 1, an SiC Drift layer 2, a CSL layer 3, a second ohmic contact layer 13, and a front - side electrode metal layer 14 arranged from bottom to top;

[0072] On the top surface of the CSL layer 3 are provided:

[0073] A Schottky contact layer 4, formed at the middle position of the top surface of the CSL layer 3;

[0074] A P - body layer 5, deposited on the top surface of the CSL layer 3;

[0075] A P + region 6, formed on the top surface of the CSL layer 3 and connected to the P - body layer 5 and the Schottky contact layer 4; the P + region 6 extends to the top surface of the Schottky contact layer 4;

[0076] An NP layer 7, deposited on the top surfaces of the P - body layer 5 and the P + region 6;

[0077] A first ohmic contact layer 8, formed on the Schottky contact layer 4, with its side connected to the NP layer 7 and the P + region 6, and its top surface located above the NP layer 7;

[0078] The P-shield region 9 is disposed below the CSL layer 3 and is used to shield the electric field and protect the gate oxide layer.

[0079] The gate oxide layer 10 has a U-shaped cross-section and extends downward from the top surface of the NP layer 7, sequentially passing through the NP layer 7, the P-body layer 5, and the CSL layer 3, and then connecting to the P-shield region 9.

[0080] The Poly layer 11 is filled in the gate oxide layer 10; the top surface of the Poly layer 11 is in the same plane as the top surface of the NP layer 7.

[0081] The isolation dielectric layer 12 is deposited on the Poly layer 11 and is used to isolate the gate electrode and the source electrode of the SiC MOSFET. The bottom surface is respectively connected to the NP layer 7, the gate oxide layer 10, and the Poly layer 11.

[0082] Wherein, the second ohmic contact layer 13 is formed on the top surfaces of the NP layer 7 and the first ohmic contact layer 8.

[0083] The front electrode metal layer 14 is formed on the top surface of the device, and the bottom part is respectively connected to the isolation dielectric layer 12 and the second ohmic contact layer 13.

[0084] The utility model integrates a hybrid body diode, namely an SBD diode and a PN junction diode, inside the trench-gate SiC MOSFET device, achieving an improvement in the long-term stable use of the device. As Figure 1 described, the short dashed-line arrows in the figure represent the current Is flow direction during freewheeling, and the long dashed-line arrows represent the device's flow through the large surge current Issm. During the Is freewheeling process, the SBD body diode is turned on first as a freewheeling diode, avoiding the bipolar degradation effect caused by holes entering the SiC Drift layer. And when the device is subjected to the Issm large surge current, the PN junction body diode is turned on, thereby improving the device's ability to withstand the impact of the large surge current.

Claims

1. SiC MOSFETT with integrated hybrid body diode, characterized in that: It comprises a SiC Sub layer (1), a SiC Drift layer (2), a CSL layer (3), a second ohmic contact layer (13) and a front electrode metal layer (14) arranged from bottom to top; The top surface of the CSL layer (3) is provided with: A Schottky contact layer (4) formed on the top surface of the CSL layer (3); A P-body layer (5) deposited on the top surface of the CSL layer (3); A P+ region (6) formed on the top surface of the CSL layer (3) and connected to the P-body layer (5) and the Schottky contact layer (4); An NP layer (7) deposited on the top surface of the P-body layer (5) and the P+ region (6); A first ohmic contact layer (8) is formed on the Schottky contact layer (4), the side of which is connected to the NP layer (7) and the P+ region (6), and the top surface of which is located above the NP layer (7); A P-shield region (9) is arranged below the CSL layer (3) and is used to shield the electric field and protect the gate oxide layer; A gate oxide layer (10) having a U-shaped cross-section, extending downward from the top surface of the NP layer (7), sequentially passing through the NP layer (7), the P-body layer (5) and the CSL layer (3), and then connected to the P-shield region (9); A Poly layer (11) is filled in the gate oxide layer (10); and an isolation dielectric layer (12) is deposited on the Poly layer (11) and is used to isolate a gate electrode and a source electrode of a SiC MOSFET.

2. The SiC MOSFETT with integrated hybrid body diode according to claim 1, characterized in that: The distance between the bottom surface of the gate oxide layer (10) and the bottom surface of the CSL layer (3) is 0.3 um-1.2 um.

3. The SiC MOSFETT with integrated hybrid body diode according to claim 1, characterized in that: The gate oxide layer (10) has a thickness of 30 nm to 80 nm.

4. The SiC MOSFETT with integrated hybrid body diode according to claim 1, characterized in that: The sputtering thickness of the Schottky contact layer (4) is 0.1 um-0.3 um.

5. The SiC MOSFETT with integrated hybrid body diode according to claim 1, characterized in that: The thickness of the P-body layer (5) is 0.3um-1um.

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