Groove SiC MOSFET device

Abstract

The utility model discloses a groove SiC MOSFET device, and relates to the technical field of semiconductors. A single-side groove structure is realized by forming a P + region on one side of the groove; when the device is used, a space depletion layer formed by the P + region and the SiC Drift layer shields an electric field, protects the gate oxide layer and avoids early failure of the gate oxide layer, the N + region is formed on the other side of the groove, the internal resistance of the device is reduced, Schottky contact is prepared on the top surface, an SBD body diode is integrated in the device, and follow current loss of the device is reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a trench SiC MOSFET device. Background Art

[0002] As a typical representative of the third-generation wide-bandgap semiconductor materials, silicon carbide (SiC) has a high critical breakdown electric field, a low intrinsic carrier concentration, a high electron saturation velocity, and a high thermal conductivity. Therefore, compared with traditional Si-based power devices, the SiC power devices prepared have more excellent physical properties and can achieve a good compromise between static and dynamic performance. Therefore, with the continuous development of the power electronics technology field towards high voltage and high power, SiC power devices have been widely used in new energy vehicles, photovoltaics, charging piles, industrial power supplies and other fields.

[0003] Among SiC power devices, the SiC MOSFET device is the most core product, which can completely replace Si IGBT and exhibit more advantageous performance, achieving higher system efficiency. SiC MOSFET devices are divided into planar gate and trench gate structures. Among them, the trench gate is favored due to its smaller chip size and is also the technical development direction of each manufacturer. However, the bottom corner of the trench in the trench-gate SiC MOSFET is prone to electric field concentration, and coupled with the poor quality of the gate oxide layer, the device is easily broken down and fails at this place. Therefore, the market share of the current trench-gate SiC MOSFET has always been less than that of the planar gate. It can be seen that how to improve the electric field concentration at the bottom corner of the trench of the trench-gate SiC MOSFET device and avoid the premature breakdown failure of the gate oxide layer is a technical problem that urgently needs to be solved in the industry. Summary of the Utility Model

[0004] Aiming at the above problems, the utility model provides a trench SiC MOSFET device that protects the gate oxide layer, avoids the premature failure of the gate oxide layer, reduces the internal resistance of the device, and reduces the freewheeling loss of the device.

[0005] The technical solution of the utility model is as follows:

[0006] A trench SiC MOSFET device includes an N+ Sub layer, an N- Drift layer, an alloy layer, and a front electrode metal layer arranged in sequence from bottom to top;

[0007] On the N- Drift layer are provided:

[0008] A Pwell region located within the N- Drift layer;

[0009] An NP region located on the top surface of the Pwell region;

[0010] The P+ region extends downward from the top surface of the NP region to below the Pwell region, and a first laterally extending portion is provided at the bottom.

[0011] The N+ region extends downward from the bottom surface of the Pwell region, and a second laterally extending portion connected to the first laterally extending portion is provided at the bottom.

[0012] The gate oxide layer has the same top surface level as the top surface of the NP region. After passing through the NP region, the Pwell region, and the N+ region in sequence downward, it extends laterally at the corner of the N+ region to form a third laterally extending portion.

[0013] The Poly layer is located on the side of the gate oxide layer, has the same top surface level as the top surface of the gate oxide layer, and its bottom surface is connected to the bottom of the gate oxide layer.

[0014] The isolation dielectric layer extends laterally from the top surface of the NP region, passes through the gate oxide layer and the Poly layer, and then extends downward to be connected to the third laterally extending portion of the gate oxide layer; the bottom surface of the isolation dielectric layer is respectively connected to the N+ region and the P+ region.

[0015] The alloy layer is provided in the NP region and the isolation dielectric layer; the bottom surface of the alloy layer in the isolation dielectric layer is respectively connected to the N+ region and the P+ region; the alloy layer is located below the Pwell region.

[0016] Specifically, the depth of the bottom surface of the alloy layer ≥ the depth of the bottom surface of the Pwell region by 0.3um - 0.5um.

[0017] Specifically, the thickness of the gate oxide layer is 50nm - 80nm.

[0018] Specifically, the cross-section of the P+ region has an L-shaped structure.

[0019] Specifically, the cross-section of the N+ region is L-shaped.

[0020] Advantages of the present utility model:

[0021] 1. Protect the gate oxide layer of the device and improve the long-term use reliability:

[0022] Due to the curvature effect, the trench gate SiC MOSFET device is prone to electric field concentration at the bottom corner of the trench. Coupled with the poor quality of the gate oxide layer of the SiC MOSFET, the gate oxide layer at the bottom corner of the trench is very likely to experience premature breakdown failure during long-term use. The present utility model forms a P+ region on one side of the trench of the trench gate SiC MOSFET to achieve a single-sided trench structure. When the device is in use, the space depletion layer formed by the P+ region and the SiC Drift layer shields the electric field, protects the gate oxide layer, and avoids the premature failure of the gate oxide layer, thereby improving the long-term use reliability of the device.

[0023] 2. Reduce the freewheeling loss of the device:

[0024] SiC MOSFET usually integrates a PN junction body diode internally to achieve freewheeling protection for the device. However, compared with the PN junction diode, the SBD diode has a smaller freewheeling loss due to its better forward performance. Therefore, in this utility model, an N+ region is formed on the other side of the trench of the trench-gate SiC MOSFET, and a Schottky contact is prepared on the top surface, thus realizing the internal integration of the SBD body diode. Its forward voltage drop VF can be reduced by about 30% compared with the PN junction diode, thereby reducing the freewheeling loss of the device. Description of the Drawings

[0025] Figure 1 is a schematic structural diagram of the trench-gate SiC MOSFET of this utility model;

[0026] Figure 2 is a schematic structural diagram of step S100;

[0027] Figure 3 is a schematic structural diagram of step S200;

[0028] Figure 4 is a schematic structural diagram of step S300;

[0029] Figure 5 is a schematic structural diagram of step S400;

[0030] Figure 6 is a schematic structural diagram of step S500;

[0031] Figure 7 is a schematic structural diagram of step S600;

[0032] Figure 8 is a schematic structural diagram of step S800;

[0033] Figure 9 is a schematic structural diagram of step S900;

[0034] Figure 10 is a schematic structural diagram of step S1000;

[0035] Figure 11 is a schematic structural diagram of step S1100;

[0036] In the figure, 1 is the N+ Sub layer, 2 is the N-Drift layer, 3 is the Pwell region, 4 is the NP region, 5 is the P+ region, 6 is the N+ region, 7 is the gate oxide layer, 8 is the Poly layer, 9 is the isolation dielectric layer, 10 is the alloy layer, and 11 is the front electrode metal layer. Detailed Implementation Manner

[0037] The present utility model will be described in detail below in conjunction with specific actual cases. Examples of the embodiments are shown in the drawings. The illustrative embodiments and descriptions of the present utility model are only used to explain the present utility model and do not constitute a limitation to the present utility model.

[0038] In the description of the present utility model, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "left", "right", "vertical", "horizontal", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present utility model. In the description of the present utility model, unless otherwise specified, the meaning of "plurality" is two or more.

[0039] In the description of the present utility model, it should be noted that unless otherwise clearly specified and defined, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific situations.

[0040] A preparation method for a trench SiC MOSFET device includes the following steps:

[0041] S100, epitaxially grow an N- Drift layer 2 on an N+ Sub layer 1; as Figure 2 shown;

[0042] The doping concentration of the N+ Sub layer 1 in step S100 is 1E19 cm -2 , and the doping concentration of the N- Drift layer 2 is 1E15 - 5E16 cm -2 .

[0043] S200, preliminarily form a Pwell region 3 on the top surface of the N- Drift layer 2 by Al ion implantation; as Figure 3 shown;

[0044] The doping concentration of the Pwell region 3 in step S200 is 1E17 - 3E18 cm -2 .

[0045] S300, preliminarily form an NP region 4 on the top surface of the Pwell region 3 by N ion implantation; as Figure 4 shown;

[0046] The doping concentration of the NP region 4 in step S300 is 1E18 - 1E19 cm-2 。

[0047] S400, form a trench extending below the Pwell region 3 on the upper surface of the N-Drift layer 2 by etching; as Figure 5 shown;

[0048] The bottom depth of the trench in step S400 ≥ the bottom depth of the Pwell region 3 by 0.3um - 0.5um.

[0049] S500, initially form a P+ region 5 on the inner surface of one side of the trench by oblique Al ion implantation. The function of the P+ region 5 is to shield the electric field; as Figure 6 shown, the cross-section of the P+ region 5 is in an L-shaped structure;

[0050] The doping concentration of the P+ region 5 in step S500 is 1E18 - 1E19 cm -2 。

[0051] S600, initially form an N+ region 6 on the inner surface of the other side of the trench by oblique N ion implantation. The function of the N+ region 6 is to reduce the device internal resistance and form an SBD body diode subsequently; as Figure 7 shown, the cross-section of the N+ region 6 is in an L-shaped;

[0052] The doping concentration of the N+ region 6 in step S600 is 5E16 - 5E17 cm -2 。

[0053] S700, activate the Pwell region 3, NP region 4, P+ region 5 and N+ region 6 implantation regions by high-temperature ion activation to form;

[0054] The high-temperature activation annealing temperature in step S700 is 1600℃ - 1900℃.

[0055] S800, grow a gate oxide layer 7 on the inner surface of the trench by dry oxidation. During the process, introduce nitrogen monoxide (NO) gas to reduce the interface states of the gate oxide layer 7; as Figure 8 shown;

[0056] The thickness of the gate oxide layer 7 in step S800 is 50nm - 80nm.

[0057] S900, form a Poly layer 8 on the side of the gate oxide layer 7 by polysilicon deposition. The function of the Poly layer 8 is to serve as the device gate electrode; as Figure 9 shown;

[0058] S1000, form an isolation dielectric layer 9 extending downward to the trench bottom on the top surface of the NP region 4 by oxide deposition. The function of the isolation dielectric layer 9 is to serve as a dielectric to prevent short-circuiting between the device gate electrode and the source electrode; as Figure 10 shown;

[0059] S1100, an alloy layer 10 of ohmic contact and Schottky contact is respectively formed on the top surface of the NP region 4 and the bottom surface of the trench by sputtering Ti or Ni metal followed by thermal annealing; as Figure 11 shown;

[0060] The thickness of the Ti or Ni metal in step S1100 is 0.1 um - 0.3 um.

[0061] S1200, a front electrode metal layer 11 is formed above the device by sputtering Ti and AlCu metals; as Figure 1 shown.

[0062] The thickness of the Ti metal in step S1200 is 0.1 um - 0.5 um, and the thickness of the AlCu metal is 2 um - 5 um.

[0063] A trench SiC MOSFET device includes an N+ Sub layer 1, an N- Drift layer 2, an alloy layer 10, and a front electrode metal layer 11 arranged in sequence from bottom to top;

[0064] On the N- Drift layer 2 are provided:

[0065] A Pwell region 3 located within the N- Drift layer 2;

[0066] An NP region 4 located on the top surface of the Pwell region 3;

[0067] A P+ region 5 extending downward from the top surface of the NP region 4 to below the Pwell region 3, with a first lateral extension at the bottom;

[0068] An N+ region 6 extending downward from the bottom surface of the Pwell region 3, with a second lateral extension at the bottom connected to the first lateral extension;

[0069] A gate oxide layer 7, the top surface of which is flush with the top surface of the NP region 4, and after passing through the NP region 4, the Pwell region 3, and the N+ region 6 in sequence downward, extends laterally at the corner of the N+ region 6 to form a third lateral extension;

[0070] One side of the gate oxide layer 7 is externally connected to the P+ region 5, and the other side is externally connected to the N+ region 6; in this case, the N+ region 6 and the P+ region 5 are respectively provided with arc-shaped corners;

[0071] A Poly layer 8 located on the side of the gate oxide layer 7, the top surface of which is flush with the top surface of the gate oxide layer 7, and the bottom surface of which is connected to the bottom surface of the gate oxide layer 7;

[0072] The isolation dielectric layer 9 extends laterally from the top surface of the NP region 4, passes through the gate oxide layer 7 and the Poly layer 8 and then extends downward to connect with the third laterally extending portion of the gate oxide layer 7; the bottom surface of the isolation dielectric layer 9 is connected to the N+ region 6 and the P+ region 5 respectively;

[0073] The alloy layer 10 is disposed within the NP region 4 and the isolation dielectric layer 9; the bottom surface of the alloy layer 10 within the isolation dielectric layer 9 is connected to the N+ region 6 and the P+ region 5 respectively; the alloy layer 10 is located below the Pwell region 3;

[0074] The top surface of the isolation dielectric layer 9 is higher than the top surface of the alloy layer 10 (the top surface region of the NP region 4);

[0075] The front electrode metal layer 11 is disposed on the alloy layer 10, and the bottom surface is connected to the alloy layer 10 and the isolation dielectric layer 9 respectively.

[0076] The bottom surface of the alloy layer 10 is 0.3um - 0.5um away from the bottom surface of the Pwell region 3.

[0077] In the trench-gate SiC MOSFET device of the present utility model, a single-sided trench structure is realized by forming a P+ region 5 on one side of the trench; during device operation, the space depletion layer formed by the P+ region 5 and the SiC Drift layer shields the electric field, protects the gate oxide layer, and avoids premature failure of the gate oxide layer. And an N+ region 6 is formed on the other side of the trench, reducing the device internal resistance. At the same time, a Schottky contact is prepared on the top surface, integrating an SBD body diode inside the device, thereby reducing the freewheeling loss of the device.

Claims

1. A trench SiC MOSFET device, characterized in that: It includes an N+ Sub layer (1), an N-Drift layer (2), an alloy layer (10) and a front electrode metal layer (11) which are arranged in sequence from bottom to top; The N-Drift layer (2) includes: A Pwell region (3) located in the N-Drift layer (2); An NP region (4), located on the top surface of the Pwell region (3); A P+ region (5) extending downward from the top surface of the NP region (4) to below the Pwell region (3), with a first lateral extension portion being provided at the bottom; An N+ region (6) extending downward from the bottom surface of the Pwell region (3), with a second lateral extension portion connected to the first lateral extension portion being provided at the bottom; A gate oxide layer (7) having a top surface flush with a top surface of the NP region (4), and extending downward in sequence through the NP region (4), the Pwell region (3) and the N+ region (6), and then extending laterally at a corner of the N+ region (6) to form a third lateral extension portion; A Poly layer (8) located on the side of the gate oxide layer (7), with a top surface flush with the top surface of the gate oxide layer (7) and a bottom surface connected to the bottom of the gate oxide layer (7); An isolation dielectric layer (9) extends laterally from the top surface of the NP region (4), passes through the gate oxide layer (7) and the Poly layer (8), and then extends downward to be connected to the third lateral extension portion of the gate oxide layer (7); the bottom surface of the isolation dielectric layer (9) is respectively connected to the N+ region (6) and the P+ region (5); The alloy layer (10) is arranged in the NP region (4) and the isolation dielectric layer (9); the bottom surface of the alloy layer (10) in the isolation dielectric layer (9) is connected to the N+ region (6) and the P+ region (5) respectively; and the alloy layer (10) is located below the Pwell region (3).

2. A trench SiC MOSFET device according to claim 1, characterized in that: The bottom surface depth of the alloy layer (10) is greater than or equal to the bottom surface depth of the Pwell region (3) by 0.3 um to 0.5 um.

3. A trench SiC MOSFET device according to claim 1, characterized in that: The gate oxide layer (7) has a thickness of 50 nm to 80 nm.

4. A trench SiC MOSFET device according to claim 1, characterized in that: The cross section of the P+ region (5) is an L-shaped structure.

5. A trench SiC MOSFET device according to claim 1, characterized in that: The cross section of the N+ region (6) is L-shaped.

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