Chip protection device and chip failure analysis system

Abstract

The utility model relates to a chip protection device and a chip failure analysis system, and relates to the technical field of chips. The chip protection device comprises a resistor module and a current-conducting plate, wherein the resistor module is connected with the current-conducting plate; the conductive plate is used for bearing a to-be-protected chip, and the to-be-protected chip is connected in series with the resistor module through the conductive plate under the condition that the to-be-protected chip is borne by the conductive plate; the resistor module is used for reducing current flowing through the chip to be protected in the failure analysis process of the chip to be protected. By adopting the method and the device, secondary damage to the chip caused by large current in a chip failure analysis process can be avoided, and the accuracy of failure analysis is improved.

Description

Technical Field

[0001] This application relates to the field of chip technology, and particularly to a chip protection device and a chip failure analysis system. Background Art

[0002] With the development of chip technology, chips are increasingly used in various fields. Chip failure analysis plays a guiding role in the improvement of chip design, manufacturing, testing, or application.

[0003] In related technologies, the techniques for chip failure analysis include Optical Beam-Induced Resistance Change (OBIRCH), Emission Microscope (EMMI), etc.

[0004] However, during the process of chip failure analysis, the chip may be damaged secondarily, and even the entire structure of the chip may be burned out, affecting the accuracy of chip failure analysis. Summary of the Utility Model

[0005] Based on this, in view of the above technical problems, it is necessary to provide a chip protection device and a chip failure analysis system that can avoid secondary damage to the chip caused by large current during the chip failure analysis process and improve the accuracy of failure analysis.

[0006] In a first aspect, an embodiment of this application provides a chip protection device, which includes a resistor module and a conductive plate, and the resistor module is connected to the conductive plate;

[0007] The conductive plate is used to carry the chip to be protected. Wherein, when the conductive plate carries the chip to be protected, the chip to be protected is connected in series with the resistor module through the conductive plate;

[0008] The resistor module is used to reduce the current flowing through the chip to be protected during the failure analysis of the chip to be protected.

[0009] In one embodiment, the resistor module includes a variable resistor, and the variable resistor is connected to the conductive plate.

[0010] In one embodiment, the resistor module further includes a first switch, and the variable resistor is connected between the first switch and the conductive plate; alternatively, the first switch is connected between the variable resistor and the conductive plate;

[0011] When the conductive plate carries the chip to be protected and the first switch is in the on state, the chip to be protected is connected in series with the variable resistor through the conductive plate.

[0012] In one embodiment, the resistor module includes a second switch and a plurality of variable resistors connected in parallel, and the resistance value ranges of the variable resistors are different;

[0013] The plurality of variable resistors are respectively connected between the second switch and the conductive plate; alternatively, the second switch is connected between the plurality of variable resistors and the conductive plate respectively;

[0014] When the conductive plate carries the chip to be protected and the second switch conducts the target variable resistor and the conductive plate, the chip to be protected is connected in series with the target variable resistor through the conductive plate, and the target variable resistor is any one of the plurality of variable resistors.

[0015] In one embodiment, the resistor module includes a third switch and a plurality of fixed resistors connected in parallel, and the resistance values of the fixed resistors are different;

[0016] The plurality of fixed resistors are respectively connected between the third switch and the conductive plate; alternatively, the third switch is connected between the plurality of fixed resistors and the conductive plate respectively;

[0017] When the conductive plate carries the chip to be protected and the third switch conducts the target fixed resistor and the conductive plate, the chip to be protected is connected in series with the target fixed resistor through the conductive plate, and the target fixed resistor is any one of the plurality of fixed resistors.

[0018] In one embodiment, the conductive plate includes at least a conductive layer, the conductive layer is connected to the resistor module, and the conductive layer is used to carry the chip to be protected.

[0019] In one embodiment, the surface area of the conductive layer for carrying the chip to be protected is greater than or equal to the surface area of the chip to be protected in contact with the conductive layer.

[0020] In one embodiment, the conductive plate further includes an insulating layer, the insulating layer is located on the side of the conductive layer away from carrying the chip to be protected, and the surface area of the insulating layer in contact with the conductive layer is greater than or equal to the surface area of the conductive layer away from the chip to be protected.

[0021] In one embodiment, the chip protection device is configured with a first conductive terminal and a second conductive terminal, and the first conductive terminal and the second conductive terminal are respectively located at two ends of the series connection path of the chip to be protected and the resistor module.

[0022] Second aspect, an embodiment of the present application provides a chip failure analysis system, including: the aforementioned chip protection device and a failure analysis station, where the chip protection device is connected to the failure analysis station;

[0023] When the conductive plate carries the chip to be protected, the failure analysis station is configured to supply power to the series connection path of the chip to be protected and the resistor module.

[0024] The above-mentioned chip protection device and chip failure analysis system include a resistor module and a conductive plate connected to each other. When the conductive plate carries the chip to be protected, the chip to be protected is in series with the resistor module through the conductive plate. Since the resistor module reduces the current flowing through the chip to be protected during the chip failure analysis process, the problem of possible secondary damage to the chip to be protected caused by a large current is solved. Therefore, the accuracy of chip failure analysis is improved. Compared with the method of directly applying voltage across the chip to be protected for failure analysis, the chip protection device provided by the embodiment of the present application can be connected in series with the chip to be protected through the resistor module to reduce the current flowing through the chip to be protected and play a role in protecting the chip. Description of the Drawings

[0025] Figure 1 It is a schematic structural diagram of a chip protection device provided by an embodiment;

[0026] Figure 2 It is one of the equivalent circuit diagrams of a chip protection device provided by an embodiment;

[0027] Figure 3 It is another equivalent circuit diagram of a chip protection device provided by an embodiment;

[0028] Figure 4 It is a third equivalent circuit diagram of a chip protection device provided by an embodiment;

[0029] Figure 5 It is a fourth equivalent circuit diagram of a chip protection device provided by an embodiment;

[0030] Figure 6 It is a schematic cross-sectional structure diagram of a chip to be protected and a conductive plate provided by an embodiment.

[0031] Explanation of the reference numerals in the drawings:

[0032] 10 - resistor module, 2 - conductive plate, 201 - conductive layer, 202 - insulating layer, 30 - chip to be protected. Detailed Embodiments

[0033] To facilitate the understanding of the present utility model, the present utility model will be described more comprehensively below with reference to the relevant drawings. The preferred embodiments of the present utility model are shown in the drawings. However, the present utility model can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present utility model more thorough and comprehensive.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present utility model belongs. The terms used in the description of the present utility model herein are only for the purpose of describing specific embodiments and are not intended to limit the present utility model. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0035] In the description of the present utility model, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present utility model.

[0036] As used in the background art, chip failure analysis is instructive for the improvement of chip design, manufacturing, testing or application. Failure analysis is an opinion detection scan of failed components. According to different needs, various testing methods and various advanced physical and chemical methods are used for analysis to determine the failure mode, failure mechanism and the cause of failure of the components. A reasonable and comprehensive failure analysis can analyze and determine the cause of failure and take corresponding measures to correct the cause of its generation, thereby improving the overall reliability of the product.

[0037] In the related art, the technologies for chip failure analysis include OBIRCH, EMMI, etc. Taking OBIRCH as an example, the failure analysis mode of OBIRCH can quickly and accurately locate defects such as short circuits, voids in wiring and vias, and silicon deposition in metals in the chip. The working principle of OBIRCH is to use a laser beam to scan the surface of the device under a constant voltage. Part of the energy of the laser beam is converted into heat energy. If there are defects in the metal interconnect line, the temperature at the defect cannot be quickly dissipated through the metal line, which will cause the temperature at the defect to accumulate and increase, and further cause changes in the metal line resistance and current. By corresponding the change area with the laser beam scanning position, the defect position, that is, the hot spot location, can be located. Therefore, it can be detected that the relationship between the current change is ΔI=(ΔR / R)I. After recording the magnitude of the current change as the pixel brightness of the image formed and recording it, the position of the pixel and the position scanned by the laser when the current changes are overlapped to form an image.

[0038] However, during the failure analysis process of a short - circuited chip, for example, during the process of the above - mentioned OBIRCH for hot - spot localization of the chip, generally, the chip is directly powered on. Since a large current will be generated after the chip is short - circuited, the chip will be damaged secondarily, and in severe cases, the entire structure will be burned out, affecting subsequent analysis and resulting in low accuracy of chip failure analysis.

[0039] Regarding the above - mentioned technical problems, the present application provides a chip protection device and a chip failure analysis system, which can reduce the current flowing through the chip to be protected during the chip failure analysis process, avoid secondary damage to the chip caused by large current, and improve the accuracy of chip failure analysis.

[0040] In one embodiment, as Figure 1 and Figure 2 shown, a chip protection device is provided. The chip protection device includes a resistor module 10 and a conductive plate 20. Among them, the resistor module 10 is connected to the conductive plate 20. Exemplarily, the resistor module 10 includes at least one resistor, where the resistor can be a variable resistor or a fixed - value resistor.

[0041] The conductive plate 20 is used to carry the chip 30 to be protected. Among them, the chip 30 to be protected can be a chip to be subjected to failure analysis, for example, including a short - circuited chip. The present application does not make specific limitations on the type, size, etc. of the chip 30 to be protected, and the chip 30 to be protected can be determined according to actual failure analysis requirements.

[0042] When the conductive plate 20 carries the chip 30 to be protected, the chip 30 to be protected is connected in series with the resistor module 10 through the conductive plate 20. In application, the chip 30 to be protected can be placed on the conductive plate 20. For example, the lower surface of the chip 30 to be protected is in contact with the conductive plate 20, where the lower surface of the chip 30 to be protected has conductivity, and the conductive plate 20 plays a role in electrically connecting the chip 30 to be protected and the resistor module 10. Since the conductive plate 20 is connected to the resistor module 10, therefore, the chip 30 to be protected can form an electrical connection with the resistor module 10 through the conductive plate 20, and the chip 30 to be protected is connected in series with the resistor module 10 through the conductive plate 20.

[0043] The resistor module 10 is used to reduce the current flowing through the chip 30 to be protected during the failure analysis process of the chip 30 to be protected. In application, power can be supplied to both ends of the path in which the chip 30 to be protected and the resistor module 10 are connected in series to perform failure analysis on the chip 30 to be protected. Since the resistor module 10 is located on the power - supply path of the chip failure analysis and the resistor module 10 is connected in series with the chip 30 to be protected, therefore, the resistor module 10 can play a role in reducing the current of the series path, thereby reducing the current flowing through the chip 30 to be protected during the failure analysis process of the chip 30 to be protected.

[0044] Exemplarily, during the failure analysis of the chip 30 to be protected, the current flowing through the chip 30 to be protected ranges from 1 microampere to 10 milliamperes. It should be noted that in practical applications, the current range flowing through the chip 30 to be protected can be determined according to factors such as the chip 30 to be protected and the voltage applied to the series circuit. This is only for exemplary illustration and does not constitute a limitation thereto.

[0045] The chip protection device provided in the above embodiment includes a resistor module 10 and a conductive plate 20 connected to each other. When the conductive plate 20 carries the chip 30 to be protected, the chip 30 to be protected is connected in series with the resistor module 10 through the conductive plate 20. Since the resistor module 10 reduces the current flowing through the chip 30 to be protected during the failure analysis of the chip 30 to be protected, the problem that the large current may cause secondary damage to the chip 30 to be protected is solved, thereby improving the accuracy of chip failure analysis. Compared with the method of directly applying voltage across the chip 30 to be protected for failure analysis, the chip protection device provided in the embodiment of the present application can be connected in series with the chip 30 to be protected through the resistor module 10 to reduce the current flowing through the chip 30 to be protected and play a role in protecting the chip.

[0046] In one embodiment, as Figure 3 shown, the resistor module 10 includes a variable resistor R0, and the variable resistor R0 is connected to the conductive plate 20. In the embodiment of the present application, a variable resistor means that the resistance value of the resistor can change. For example, the resistance value of the variable resistor can be adjusted by manual operation. Exemplarily, the variable resistor R0 includes a mechanical adjustable resistor, a potentiometer, a digital potentiometer or a wire-wound resistor, and is not limited thereto. In applications, any suitable type of variable resistor can be selected, and no specific limitation is made here.

[0047] When the conductive plate 20 carries the chip 30 to be protected, the chip 30 to be protected is connected in series with the variable resistor R0 through the conductive plate 20, and the variable resistor R0 is used to reduce the current flowing through the chip 30 to be protected during the failure analysis of the chip 30 to be protected. In applications, power can be supplied to both ends of the series circuit where the variable resistor R0 and the chip 30 to be protected are located, and by adjusting the resistance value of the variable resistor, the current flowing through the chip 30 to be protected can reach an appropriate current value, so that the chip 30 to be protected can perform failure analysis at the appropriate current value. In this way, through the variable resistor R0, the current flowing through the chip 30 to be protected has sufficient adjustable space, and the appropriate resistance range can be adaptively selected according to the resistance value of the chip 30 to be protected itself after failure, playing a role in protecting the chip.

[0048] Exemplarily, the resistance value range of the variable resistor R0 is 1 KΩ - 10 MΩ. It should be noted that in practical applications, the resistance value range of the variable resistor R0 can be designed accordingly according to the voltage applied during the failure analysis process. This is only for exemplary illustration and does not constitute a limitation thereto.

[0049] Please continue to refer to Figure 3 , in one embodiment, the resistor module 10 further includes a first switch S1. Exemplarily, the first switch S1 includes a single-pole single-throw (SPST) switch. For example, the first switch S1 can be a toggle switch, a push-button switch, a key switch, etc. The type of the first switch S1 can be specifically set according to actual requirements and will not be overly limited herein.

[0050] In some embodiments, the variable resistor R0 is connected between the first switch S1 and the conductive plate 20. That is, the first end of the variable resistor R0 is connected to the first switch S1, and the second end of the variable resistor R0 is connected to the conductive plate 20.

[0051] In other embodiments, the first switch S1 is connected between the variable resistor R0 and the conductive plate 20. That is, the first end of the first switch S1 is connected to the variable resistor R0, and the second end of the first switch S1 is connected to the conductive plate 20.

[0052] It should be noted that the embodiments of the present application do not limit the relative positional relationship between the variable resistor and the first switch S1 and the conductive plate 20 respectively. The variable resistor can be arbitrarily selected to be disposed between the first switch S1 and the conductive plate 20 according to requirements, or the first switch S1 can be disposed between the variable resistor R0 and the conductive plate 20, which is not limited herein.

[0053] Exemplarily, the first switch S1 and the variable resistor R0 can be encapsulated in the same device, which can improve the integration of the device and reduce the occupied area of the device.

[0054] Based on the above, when the conductive plate 20 bears the chip 30 to be protected and the first switch S1 is in the conducting state, the chip 30 to be protected is connected in series with the variable resistor through the conductive plate 20, where the first switch S1 is located on the series connection path of the chip 30 to be protected and the variable resistor. In application, power can be supplied to both ends of the series connection path where the first switch S1, the variable resistor, and the chip 30 to be protected are located to perform a failure analysis on the chip 30 to be protected. Specifically, in the default state, the first switch S1 is in the off state, and the resistance value of the variable resistor R0 is the maximum value. Before the failure analysis, place the chip 30 to be protected on the conductive plate 20, supply a constant voltage to both ends of the series connection path of the chip 30 to be protected and the variable resistor R0, and switch the first switch S1 to the conducting state, gradually reducing the resistance value of the variable resistor R0 so that the current flowing through the chip 30 to be protected increases to an appropriate value, and then perform a failure analysis on the chip 30 to be protected.

[0055] The chip protection device provided by the above embodiment can adjust the resistance value of the variable resistor so that the current flowing through the chip 30 to be protected during the failure analysis of the chip 30 to be protected is an appropriate value, achieving fine control of the magnitude of the current flowing through the chip 30 to be protected, effectively avoiding secondary damage to the chip 30 to be protected caused by a large current, and ensuring the accuracy and safety of the subsequent failure analysis process. Moreover, the chip protection device can control the on-off state of the series connection path where the chip 30 to be protected and the variable resistor are located through the first switch S1, so that the circuit connection between the chip 30 to be protected and the variable resistor can be cut off or restored when needed, improving the flexibility of the operation, and also providing additional safety protection to ensure that the chip will not be accidentally exposed to the current when the failure analysis is not performed, making the failure analysis process more controllable, reducing errors caused by improper technical operations or external interference, and thus improving the efficiency of the analysis and the reliability of the results.

[0056] In one embodiment, as Figure 4 shown, the resistance module 10 includes a second switch S2 and a plurality of variable resistors connected in parallel. Among them, the resistance value ranges of the variable resistors are different. The present application does not specifically limit the number of variable resistors and the resistance value ranges of the individual variable resistors. For example, the number of variable resistors can be 2, 3, 4, or other suitable values greater than 4. Taking Figure 4 the structure shown as an example, where the resistance module 10 includes 4 parallel variable resistors R1, R2, R3, and R4. Among them, the resistance value range of the variable resistor R1 is 1 MΩ - 10 MΩ, the resistance value range of the variable resistor R2 is 100 KΩ - 1000 KΩ, the resistance value range of the variable resistor R3 is 10 KΩ - 100 KΩ, and the resistance value range of the variable resistor R4 is 1 KΩ - 10 KΩ.

[0057] Exemplarily, the second switch S2 includes a single-pole multi-throw (SPnT) switch. For example, the second switch S2 can be a toggle switch, a push-button switch, a key switch, a rotary switch, etc. Specifically, the type of the second switch S2 can be set according to actual requirements, and no excessive limitation is made here.

[0058] In some embodiments, a plurality of variable resistors are respectively connected between the second switch S2 and the conductive plate 20. That is, the first ends of the plurality of variable resistors are respectively connected to the plurality of first ends of the second switch S2 in one-to-one correspondence. The second ends of the plurality of variable resistors are respectively connected to the conductive plate 20. As Figure 4 shown, the first ends of the variable resistors R1, R2, R3, and R4 are respectively connected to the four first ends of the second switch S2 in one-to-one correspondence, and the first ends of the variable resistors R1, R2, R3, and R4 are respectively connected to the conductive plate 20.

[0059] In other embodiments, the second switch S2 is connected between the plurality of variable resistors and the conductive plate 20 respectively. That is, the plurality of first ends of the second switch S2 are respectively connected to the first ends of the plurality of variable resistors in one-to-one correspondence, and the second end of the second switch S2 is connected to the conductive plate 20.

[0060] In applications, the connection manner among the plurality of variable resistors, the second switch S2, and the conductive plate 20 can be selected according to actual requirements, and no excessive limitation is made here.

[0061] Exemplarily, the second switch S2 can be encapsulated with a plurality of variable resistors connected in parallel in the same device, which can improve the integration degree of the device and reduce the occupied area of the device.

[0062] Based on the above, when the conductive plate 20 bears the chip 30 to be protected and the second switch S2 conducts the target variable resistor and the conductive plate 20, the chip 30 to be protected is connected in series with the target variable resistor through the conductive plate 20, where the target variable resistor is located on the series connection path of the chip 30 to be protected and the variable resistor. The target variable resistor is any one of the plurality of variable resistors. In applications, power can be supplied to both ends of the series connection path where the second switch S2, the target variable resistor, and the chip 30 to be protected are located to perform failure analysis on the chip 30 to be protected.

[0063] For Figure 4Taking the shown structure as an example, in the default state, the second switch S2 is in the off state, and the resistance values of the variable resistors R1 to R4 are all at the maximum values. Before the failure analysis, the chip 30 to be protected is placed on the conductive plate 20, and a constant voltage is provided across the series connection path of the chip 30 to be protected and the variable resistors. The second switch S2 first conducts the variable resistor R1 and the chip 30 to be protected, and gradually reduces the resistance value of the variable resistor R1. If the current flowing through the chip 30 to be protected does not reach the appropriate value, the second switch S2 then conducts the variable resistor R2 and the chip 30 to be protected, and gradually reduces the resistance value of the variable resistor R2, and so on, until the current flowing through the chip 30 to be protected reaches the appropriate value, and then the failure analysis of the chip 30 to be protected is carried out.

[0064] For the chip protection device provided in the above embodiment, the resistance module 10 includes a second switch S2 and a plurality of variable resistors connected in parallel. The target variable resistor with an appropriate resistance value can be selected from the plurality of variable resistors through the second switch S2, so that when the conductive plate 20 carries the chip 30 to be protected and the second switch S2 conducts the target variable resistor and the conductive plate 20, the chip 30 to be protected is connected in series with the target variable resistor through the conductive plate 20, and the current flowing through the chip 30 to be protected during the failure analysis of the chip 30 to be protected is reduced through the target variable resistor. Since the resistance value ranges of the variable resistors are different and the resistance values of the variable resistors are adjustable, therefore, the current flowing through the chip 30 to be protected has sufficient adjustable space through the second switch S2 and the plurality of variable resistors, and the appropriate resistance range can be selected accordingly according to the resistance value of the chip 30 to be protected after its own failure, so as to achieve the purpose of protecting the chip and improve the flexibility of the operation.

[0065] In one embodiment, as Figure 5 shown, the resistance module 10 includes a third switch S3 and a plurality of fixed resistors connected in parallel. Among them, the resistance values of the fixed resistors are different. Exemplarily, the resistance values of the fixed resistors are in the range of 1 KΩ to 10 MΩ. In the embodiments of the present application, a fixed resistor refers to a resistor with a fixed and non-adjustable resistance value. The present application does not specifically limit the number of fixed resistors and the resistance values of each fixed resistor. For example, the number of fixed resistors can be 2, 3, 4, or other suitable values greater than 4. Taking Figure 5 the shown structure as an example, among them, the fixed resistors include 5 variable resistors R5, R6, R7, R8, and R9 connected in parallel. Among them, the resistance value of the fixed resistor R5 is 10 MΩ, the resistance value of the fixed resistor R6 is 1 MΩ, the resistance value of the fixed resistor R7 is 100 KΩ, the resistance value of the fixed resistor R8 is 10 KΩ, and the resistance value of the fixed resistor R9 is 1 KΩ.

[0066] Exemplarily, the third switch S3 includes a single-pole multi-throw (SPnT) switch. For example, the third switch S3 can be a toggle switch, a push-button switch, a key switch, a rotary switch, etc. Specifically, the type of the third switch S3 can be set according to actual requirements, and no excessive limitation is made here.

[0067] In some embodiments, a plurality of fixed resistors are respectively connected between the third switch S3 and the conductive plate 20. That is, the first ends of the plurality of fixed resistors are respectively connected to the plurality of first ends of the third switch S3 in one-to-one correspondence. The second ends of the plurality of fixed resistors are respectively connected to the conductive plate 20. As Figure 5 shown, the first ends of the fixed resistors R5, R6, R7, R8, and R9 are respectively connected to the four first ends of the third switch S3 in one-to-one correspondence, and the first ends of the fixed resistors R5, R6, R7, R8, and R9 are respectively connected to the conductive plate 20.

[0068] In other embodiments, the third switch S3 is connected between the plurality of fixed resistors and the conductive plate 20 respectively. That is, the plurality of first ends of the third switch S3 are respectively connected to the first ends of the plurality of fixed resistors in one-to-one correspondence, and the second end of the third switch S3 is connected to the conductive plate 20.

[0069] In application, the connection manner among the plurality of fixed resistors, the third switch S3, and the conductive plate 20 can be selected according to actual requirements, and no excessive limitation is made here.

[0070] Exemplarily, the third switch S3 can be encapsulated with a plurality of parallel-connected fixed resistors in the same device, which can improve the integration degree of the device and reduce the occupied area of the device.

[0071] Based on the above, when the conductive plate 20 bears the chip 30 to be protected and the third switch S3 conducts the target fixed resistor and the conductive plate 20, the chip 30 to be protected is connected in series with the target fixed resistor through the conductive plate 20, where the target fixed resistor is located on the series connection path of the chip 30 to be protected and the fixed resistors. The target fixed resistor is any one of the plurality of fixed resistors. In application, power can be supplied to both ends of the series connection path where the third switch S3, the target fixed resistor, and the chip 30 to be protected are located to perform failure analysis on the chip 30 to be protected.

[0072] To Figure 5Taking the shown structure as an example, in the default state, the third switch S3 is in the off state. Before failure analysis, place the chip 30 to be protected on the conductive plate 20, and provide a constant voltage across the series connection path of the chip 30 to be protected and the fixed-value resistor. The third switch S3 first conducts the fixed-value resistor R5 and the chip 30 to be protected. If the current flowing through the chip 30 to be protected does not reach the appropriate value, then the third switch S3 conducts the fixed-value resistor R6 and the chip 30 to be protected. If the current flowing through the chip 30 to be protected still does not reach the appropriate value, then the third switch S3 conducts the fixed-value resistor R7 and the chip 30 to be protected, and so on, until the current flowing through the chip 30 to be protected reaches the appropriate value, and then perform failure analysis on the chip 30 to be protected.

[0073] For the chip protection device provided in the above embodiment, the resistor module 10 includes a third switch S3 and a plurality of fixed-value resistors arranged in parallel. The target fixed-value resistor can be selected from the plurality of fixed-value resistors with different resistance values through the third switch S3, so that when the conductive plate 20 carries the chip 30 to be protected and the third switch S3 conducts the target fixed-value resistor and the conductive plate 20, the chip 30 to be protected is connected in series with the target fixed-value resistor through the conductive plate 20, and the current flowing through the chip 30 to be protected during the failure analysis of the chip 30 to be protected is reduced by the target fixed-value resistor. Since the resistance values of the fixed-value resistors are different, therefore, according to the resistance value of the chip 30 to be protected after its own failure, the appropriate resistance value of the fixed-value resistor can be selected through the third switch S3, so that the current flowing through the chip 30 to be protected is the appropriate value, avoiding secondary damage to the chip 30 to be protected caused by large current, achieving the purpose of protecting the chip, and improving the flexibility of the operation.

[0074] In one embodiment, as Figure 6 shown, the conductive plate 20 includes at least a conductive layer 201. The conductive layer 201 is connected to the resistor module 10. Exemplarily, one side of the conductive layer 201 is connected to the resistor module 10. For example, in Figure 6 it, the left side of the conductive plate 20 is connected to the resistor module 10. The conductive layer 201 is used to carry the chip 30 to be protected. When the conductive layer 201 carries the chip 30 to be protected, the chip 30 to be protected is connected in series with the resistor module 10 through the conductive layer 201. Based on this, the conductive layer 201 serves as a platform for carrying the chip 30 to be protected and plays an electrical connection role to ensure that the chip can form an effective series circuit with the resistor module 10 to reduce the current flowing through the chip 30 to be protected through the resistor module 10.

[0075] Please continue to refer to Figure 6, in one embodiment, the material of the conductive layer 201 can be a conductive metal material. Exemplarily, the material of the conductive layer 201 includes at least one of copper, aluminum, silver, and gold. These metal materials have good electrical conductivity and can effectively conduct current, ensuring the stability of the electrical connection between the chip 30 to be protected and the resistor module 10, thereby improving the accuracy and reliability of chip failure analysis.

[0076] Please continue to refer to Figure 6 , in one embodiment, the surface area of the conductive layer 201 for carrying the chip 30 to be protected is greater than or equal to the surface area of the chip 30 to be protected in contact with the conductive layer 201. Taking Figure 6 the structure shown as an example, the surface of the conductive layer 201 for carrying the chip 30 to be protected is the upper surface of the conductive layer 201, and the surface of the chip 30 to be protected in contact with the conductive layer 201 is the lower surface of the chip 30 to be protected. Based on this, sufficient contact between the conductive layer 201 and the chip 30 to be protected can be ensured, enabling the chip 30 to be protected to form a stable electrical connection with the resistor module 10 through the conductive plate 20, improving the reliability and stability of the chip protection device.

[0077] Please continue to refer to Figure 6 , in one embodiment, the conductive plate 20 further includes an insulating layer 202. The insulating layer 202 is located on the side of the conductive layer 201 away from the surface carrying the chip 30 to be protected. The surface area of the insulating layer 202 in contact with the conductive layer 201 is greater than or equal to the surface area of the conductive layer 201 away from the chip 30 to be protected. Taking Figure 6 the structure shown as an example, the contact surface between the insulating layer 202 and the conductive layer 201 is the upper surface of the insulating layer 202, and the surface of the conductive layer 201 away from the chip 30 to be protected is the lower surface of the conductive layer 201. In application, the insulating layer 202 can be used as the base of the conductive plate 20. Exemplarily, the material of the insulating layer 202 includes insulating materials, such as silicon nitride, silicon oxide, epoxy resin, etc. Based on this, the conductive plate 20 can achieve the electrical connection between the chip 30 to be protected and the resistor module 10 through the conductive layer 201, and can also isolate the conductive layer 201 from other external structures through the insulating layer 202, playing a role of electrical insulation.

[0078] Please continue to refer to Figures 1 to 6 , in one embodiment, the resistor module 10 is detachably connected to the conductive plate 20. In this way, the resistor module 10 and the conductive plate 20 can be disassembled or connected as needed, reducing the occupied space and making the replacement and maintenance of any part of the resistor module 10 and the conductive plate 20 in the chip protection device simpler and faster. This not only improves the flexibility of the chip protection device but also reduces the operating cost.

[0079] Please continue to refer to Figures 3 to 5, in one embodiment, the chip protection device is configured with a first conductive terminal P1 and a second conductive terminal P2. The first conductive terminal P1 and the second conductive terminal P2 are respectively located at two ends of the series connection path of the chip 30 to be protected and the resistor module 10. Among them, the first conductive terminal P1 and the second conductive terminal P2 are respectively used to connect to the failure analysis machine platform, so that the failure analysis machine platform supplies power to the series connection path. Among them, the conductive terminals (the first conductive terminal P1 and / or the second conductive terminal P2) include but are not limited to forms such as pins and leads, and are not limited herein. Taking Figure 4 the shown structure as an example, the first conductive terminal P1 is located at the second end (fixed end) of the second switch S2, and the second conductive terminal P2 is located on the right side of the conductive plate 20. That is, the first conductive terminal P1 and the second conductive terminal P2 are respectively located at two ends of the series connection path where the second switch S2, the target variable resistor, and the chip 30 to be protected are located. Based on this, power can be supplied to the series connection path where the chip 30 to be protected and the resistor module 10 are located through the first conductive terminal P1 and the second conductive terminal P2, which helps to realize the failure analysis of the chip 30 to be protected.

[0080] Based on the same concept, the embodiment of the present application also provides a chip failure analysis system for implementing the above-mentioned chip protection device. The implementation solution provided by this system to solve the problem is similar to the implementation solution described in the above method. Therefore, the specific limitations in one or more chip failure analysis system embodiments provided below can refer to the limitations on the chip protection device in the above text, and will not be repeated here.

[0081] Please continue to refer to Figure 1 , in one embodiment, a chip failure analysis system is provided. The chip failure analysis system includes a chip protection device and a failure analysis machine platform. Among them, the chip protection device is connected to the failure analysis machine platform. When the conductive plate 20 carries the chip 30 to be protected, the failure analysis machine platform is used to supply power to the series connection path of the chip 30 to be protected and the resistor module 10, so as to perform failure analysis on the chip 30 to be protected on the series connection path through the failure analysis machine platform. Among them, the failure analysis methods include but are not limited to OBIRCH, EMMI, etc.

[0082] Exemplarily, the range of the supply voltage provided by the failure analysis machine platform to the series connection path of the chip 30 to be protected and the resistor module 10 is 0 - 20V. It should be noted that in practical applications, the voltage applied to the series connection path can be determined according to factors such as the chip 30 to be protected and the failure analysis method. This is only an exemplary illustration here and does not constitute a limitation thereto.

[0083] Please continue to refer to Figures 3 to 5, in one embodiment, the chip protection device includes a first conductive terminal P1 and a second conductive terminal P2. Among them, the chip protection device is connected to the failure analysis machine through the first conductive terminal P1 and the second conductive terminal P2.

[0084] In one embodiment, a chip failure analysis system is provided. The chip failure analysis system includes a chip protection device and a failure analysis machine. For a chip sample to be subjected to failure analysis, before performing hot spot localization using the OBIRCH method, electrical tests are first performed. Among them, for those samples that generate large current leakage, such as short-circuited chips, before hot spot localization, they are first placed in a device that protects the state of the failed chip structure, such as Figure 1 shown.

[0085] Among them, as Figure 4 shown, the chip protection device includes a second switch S2 and four parallel variable resistors. The four variable resistors are variable resistor R1 = 1MΩ to 10MΩ, variable resistor R2 = 100KΩ to 1000KΩ, variable resistor R3 = 10KΩ to 100KΩ, and variable resistor R4 = 1KΩ to 10KΩ.

[0086] In the default state, the second switch S2 is in the off state, and the resistance values of the variable resistors R1 to R4 are all at their maximum values, that is, variable resistor R1 = 10MΩ, variable resistor R2 = 1000KΩ, variable resistor R1 = 100KΩ, variable resistor R1 = 10KΩ. Before failure analysis, the chip 30 to be protected is placed on the upper surface of the conductive plate 20, and the failure analysis machine provides a supply voltage of 20V through the first conductive terminal P1 and the second conductive terminal P2. The second switch S2 first conducts the variable resistor R1 and the chip 30 to be protected, and gradually reduces the resistance value of the variable resistor R1. When the current flowing through the chip 30 to be protected does not reach the appropriate value, the second switch S2 is toggled to conduct the variable resistor R2 and the chip 30 to be protected, and the resistance value of the variable resistor R2 is gradually reduced. When the resistance value of the variable resistor R2 is reduced to 200KΩ, the current flowing into the chip 30 to be protected is reduced to the appropriate value, that is, I = V / (Rc + Re) = 20V / 200KΩ = 100 μA, where I represents the current flowing through the chip; V represents the supply voltage; Rc represents the resistance value of the chip; Re represents the resistance value of the target variable resistor. This current value will not cause secondary damage to the chip 30 to be protected. Based on this, the failure analysis machine can further send a signal to perform hot spot localization on the chip 30 to be protected, realizing the failure analysis of the chip.

[0087] In the above chip failure analysis system, through the chip protection device, it is possible to well improve the situation where a sudden large current directly causes secondary damage to the sample during hot spot localization of a short-circuited chip, and improve the accuracy of the failure analysis result.

[0088] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as within the scope described in this specification.

[0089] The above-described embodiments merely represent several implementation manners of the present utility model. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the utility model patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present utility model, several modifications and improvements can still be made, and these all belong to the protection scope of the present utility model. Therefore, the protection scope of the present utility model patent shall be subject to the appended claims.

Claims

1. A chip protection device, characterized in that: The chip protection device comprises a resistance module and a conductive plate, wherein the resistance module is connected to the conductive plate; The conductive plate is used to carry the chip to be protected, wherein, when the conductive plate carries the chip to be protected, the chip to be protected is connected in series with the resistor module through the conductive plate; The resistor module is used to reduce the current flowing through the chip to be protected during the failure analysis of the chip to be protected.

2. The chip protection device according to claim 1, characterized in that: The resistor module includes a variable resistor, and the variable resistor is connected to the conductive plate.

3. The chip protection device according to claim 2, characterized in that: The resistor module further includes a first switch, and the variable resistor is connected between the first switch and the conductive plate; or, the first switch is connected between the variable resistor and the conductive plate; When the conductive plate carries the chip to be protected and the first switch is in an on state, the chip to be protected is connected in series with the variable resistor through the conductive plate.

4. The chip protection device according to claim 1, characterized in that: The resistance module includes a second switch and a plurality of variable resistors arranged in parallel, and the resistance range of each variable resistor is different; The plurality of variable resistors are respectively connected between the second switch and the conductive plate; or the second switch is respectively connected between the plurality of variable resistors and the conductive plate; When the conductive plate carries the chip to be protected and the second switch conducts the target variable resistor and the conductive plate, the chip to be protected is connected in series with the target variable resistor through the conductive plate, and the target variable resistor is any one of the multiple variable resistors.

5. The chip protection device according to claim 1, characterized in that: The resistance module includes a third switch and a plurality of fixed-value resistors arranged in parallel, and the resistance values ​​of the fixed-value resistors are different; The plurality of fixed value resistors are respectively connected between the third switch and the conductive plate; or the third switch is respectively connected between the plurality of fixed value resistors and the conductive plate; When the conductive plate carries the chip to be protected and the third switch conducts a target fixed-value resistor and the conductive plate, the chip to be protected is connected in series with the target fixed-value resistor through the conductive plate, and the target fixed-value resistor is any one of the multiple fixed-value resistors.

6. The chip protection device according to any one of claims 1 to 5, characterized in that: The conductive plate at least includes a conductive layer, the conductive layer is connected to the resistor module, and the conductive layer is used to carry the chip to be protected.

7. The chip protection device according to claim 6, characterized in that: The surface area of ​​the conductive layer used to support the chip to be protected is greater than or equal to the surface area of ​​the chip to be protected in contact with the conductive layer.

8. The chip protection device according to claim 6, characterized in that: The conductive plate further includes an insulating layer, which is located on a side of the conductive layer away from the chip to be protected, and a surface area of ​​the insulating layer in contact with the conductive layer is greater than or equal to a surface area of ​​the conductive layer away from the chip to be protected.

9. The chip protection device according to claim 1, characterized in that: The chip protection device is configured with a first conductive terminal and a second conductive terminal, and the first conductive terminal and the second conductive terminal are respectively located at two ends of a series path between the chip to be protected and the resistor module.

10. A chip failure analysis system, characterized in that: include: The chip protection device and failure analysis machine according to any one of claims 1 to 9, wherein the chip protection device is connected to the failure analysis machine; In the case where the conductive plate carries the chip to be protected, the failure analysis machine is used to supply power to a series path between the chip to be protected and the resistor module.

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