Dual-timing and dual-compensation distance measuring circuit
By adopting a dual timing and double compensation scheme in the ranging circuit, combined with ADC and TDC modules, the problems of poor measurement accuracy and weak measurement capabilities in the prior art are solved, and the distance measurement effect with high precision and strong anti-interference is achieved.
Patent Information
- Application Number
- CN202421248009.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-03
- Publication Date
- 2025-06-13
- Estimated Expiration
- 2034-06-03
AI Technical Summary
When the existing ranging circuit measures high reflectivity objects or close-range objects, the full range of the ADC results in poor accuracy and blind spots in measurement, and when measuring low reflectivity objects or long-range objects, the measurement ability is weak.
The distance measurement circuit of dual timing and double compensation is adopted, combined with the front-end filtering circuit, analog-digital conversion module, time-digital conversion module, comparator module and control module, and the dual timing module of ADC and TDC can achieve high-precision processing and compensation of the distance measurement signal.
It improves the measurement accuracy and consistency of the rangefinder, enhances the measurement ability and anti-interference ability, and is suitable for measuring objects and distances of different reflectivity.
Smart Images
Figure CN222979786U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of ranging, and particularly relates to a ranging circuit with dual timing and dual compensation. Background Art
[0002] Laser ranging determines the distance between a ranging device and an object to be measured by measuring the time interval between the transmitted laser and the received laser. However, there are certain deviations in both the AD acquisition chip and the comparator chip. According to the principle of laser ranging, when the time interval differs by 1 ns, the measurement result of the measured distance will cause a measurement deviation of about 15 cm, so the consistency of the measurement result is not very good.
[0003] A ranging circuit is provided in the related art, which includes a comparator, an ADC module (analog-to-digital converter), a processor, and a display. The comparator receives a signal and outputs it to the ADC module. The distance data obtained by measuring the target is measured by the ADC module, and the distance data is processed by the processor and sent to the display for display.
[0004] However, when the measurement target of the above related technology is a high-reflectivity object (such as a road sign, reflective film) or a short-distance object, there are problems of poor accuracy and measurement blind area caused by the full scale of the ADC (range: the input amplitude range of the analog quantity). When the measurement target is a low-reflectivity object or a long-distance object, the measurement ability is weak. Summary of the Utility Model
[0005] An embodiment of the utility model provides a ranging circuit with dual timing and dual compensation, aiming to solve the problems of poor measurement accuracy and weak measurement energy in the existing ranging circuit.
[0006] An embodiment of the utility model provides a ranging circuit with dual timing and dual compensation, including: a front-end filtering circuit, an analog-to-digital conversion module, a time-to-digital conversion module, a comparator module, a control module, and a display module; the input end of the front-end filtering circuit receives a ranging signal, the first output end of the front-end filtering circuit is electrically connected to the input end of the analog-to-digital conversion module, and the second output end of the front-end filtering circuit is electrically connected to the first input end of the comparator module; the output end of the analog-to-digital conversion module is electrically connected to the input end of the control module, the output end of the comparator module is electrically connected to the input end of the time-to-digital conversion module, the output end of the time-to-digital conversion module is electrically connected to the input end of the control module, and the input end of the control module is further electrically connected to the second input end of the comparator module; the output end of the control module is electrically connected to the display module.
[0007] Further, the front-end filter circuit includes: a first capacitor, a second capacitor, a first resistor, and a third capacitor; the first end of the first capacitor serves as the input end of the front-end filter circuit, the second end of the first capacitor is electrically connected to the first end of the second capacitor and the first end of the first resistor respectively, the second end of the second capacitor is grounded, the second end of the first resistor is electrically connected to the first end of the third capacitor, the second end of the first resistor serves as the output end of the front-end filter circuit, and the second end of the third capacitor is grounded.
[0008] Further, the comparator module includes: a second resistor, a third resistor, a fourth resistor, a fifth resistor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, and a comparator chip;
[0009] The first end of the second resistor is electrically connected to the power supply, the second end of the second resistor is electrically connected to the first end of the third resistor and the first end of the fourth capacitor respectively, the second end of the fourth capacitor is electrically connected to the first end of the fourth resistor and grounded, the second end of the fourth resistor is electrically connected to the second end of the third resistor, the first end of the fifth capacitor, and pin 3 of the comparator chip, and the second end of the fifth capacitor serves as the first input end of the comparator module; pin 1 of the comparator chip serves as the output end of the comparator module;
[0010] Pin 2 of the comparator chip is grounded, pin 5 of the comparator chip is electrically connected to the first end of the sixth capacitor and the power supply respectively, pin 4 of the comparator chip is electrically connected to the first end of the fifth resistor and the first end of the eighth capacitor respectively, and the second end of the eighth capacitor is grounded; the second end of the fifth resistor is electrically connected to the first end of the seventh capacitor, and the second end of the seventh capacitor is grounded; the first end of the seventh capacitor serves as the second input end of the comparator module.
[0011] Further, the model of the comparator chip is the STM32G4 comparator.
[0012] Further, the analog-to-digital conversion module includes: an ADC module chip, a ninth capacitor, and a tenth capacitor; the input end of the ADC module chip serves as the input end of the analog-to-digital conversion module, the output end of the ADC module chip serves as the output end of the analog-to-digital conversion module, the first ends of the ninth capacitor and the tenth capacitor are electrically connected to the reference voltage end of the ADC analog chip, and the second ends of the ninth capacitor and the tenth capacitor are electrically connected and grounded.
[0013] Further, the model of the ADC module chip is the ADC0832CCN chip.
[0014] Further, the time digital conversion module includes: a TDC module chip, an eleventh capacitor, a twelfth capacitor, a thirteenth capacitor, a fourteenth capacitor, a sixth resistor, and a seventh resistor;
[0015] Pin 17 and pin 18 of the TDC module chip serve as the input terminals of the time digital conversion module, and pins 6 to 9 of the TDC module chip serve as the output terminals of the time digital conversion module;
[0016] The first ends of the eleventh capacitor and the twelfth capacitor are electrically connected to the power supply, and the second ends of the eleventh capacitor and the twelfth capacitor are electrically connected and grounded; the first end of the sixth resistor is respectively electrically connected to the first end of the twelfth capacitor and pin 2 of the TDC module chip, the first end of the thirteenth capacitor is respectively electrically connected to the second end of the sixth resistor and the first end of the fourteenth capacitor, and the second ends of the thirteenth capacitor and the fourteenth capacitor are electrically connected and grounded; the first end of the seventh resistor is electrically connected to pin 4 of the TDC module chip, and the second end of the seventh resistor is electrically connected to the power supply.
[0017] Preferably, the model of the TDC module chip is the TDC-GP30 chip.
[0018] The beneficial effects achieved by the present utility model: The present utility model provides a ranging circuit with dual timing and dual compensation. The ranging signal is received through the input terminal of the front-end filtering circuit. The first output terminal of the front-end filtering circuit is electrically connected to the input terminal of the analog-to-digital conversion module, and the second output terminal of the front-end filtering circuit is connected to the first input terminal of the comparator module; the output terminal of the analog-to-digital conversion module is electrically connected to the input terminal of the control module, the output terminal of the comparator module is electrically connected to the input terminal of the time digital conversion module, the output terminal of the time digital conversion module is electrically connected to the input terminal of the control module, and the input terminal of the control module is further electrically connected to the second input terminal of the comparator module; the output terminal of the control module is electrically connected to the display module. In this way, the timing module for measurement adopts the scheme of ADC (analog-to-digital converter) + TDC (time digital converter), with dual timing and dual compensation. The two cooperate with each other, making reasonable use of the advantages of both, and at the same time making up for the shortcomings of the single scheme. This enables the rangefinder to have high measurement accuracy, good measurement consistency, strong measurement ability, and strong anti-interference ability. Description of the Drawings
[0019] Figure 1 is a schematic diagram of a ranging circuit with dual timing and dual compensation provided by an embodiment of the present utility model;
[0020] Figure 2 is a circuit diagram of the front-end filtering circuit provided by an embodiment of the present utility model;
[0021] Figure 3 is the circuit diagram of the comparator module provided by the embodiment of the present utility model;
[0022] Figure 4 is the circuit diagram of the time-to-digital conversion module provided by the embodiment of the present utility model;
[0023] Figure 5 is the circuit diagram of the analog-to-digital conversion module provided by the embodiment of the present utility model;
[0024] Figure 6 is the waveform schematic diagram of the received signal provided by the embodiment of the present utility model.
[0025] Among them, 1. Front-end filter circuit, 2. Comparator module, 3. Analog-to-digital conversion module, 4. Time-to-digital conversion module, 5. Control module, 6. Display module. Specific implementation manners
[0026] Next, the technical solutions in the embodiments of the present utility model will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all the embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present utility model.
[0027] In the existing technical solutions, when the measurement target of the related technology is a high-reflectivity object (for example: road sign, reflective film) or a short-distance object, there are problems of poor accuracy and measurement blind area caused by the full scale of the ADC (range: the input amplitude range of the analog quantity). When the measurement target is a low-reflectivity object or a long-distance object, the measurement ability is weak.
[0028] In the present utility model, the ranging signal is received through the input end of the front-end filter circuit. The first output end of the front-end filter circuit is electrically connected to the input end of the analog-to-digital conversion module, and the second output end of the front-end filter circuit is connected to the first input end of the comparator module; the output end of the analog-to-digital conversion module is electrically connected to the input end of the control module, the output end of the comparator module is electrically connected to the input end of the time-to-digital conversion module, the output end of the time-to-digital conversion module is electrically connected to the input end of the control module, and the input end of the control module is also electrically connected to the second input end of the comparator module; the output end of the control module is electrically connected to the display module. In this way, the timing module for measurement adopts the scheme of ADC (analog-to-digital converter) + TDC (time-to-digital converter), double timing, and double compensation. The two cooperate with each other, reasonably utilize the advantages of both, and at the same time make up for the disadvantages of the single scheme, so that the rangefinder has high measurement accuracy, good measurement consistency, strong measurement ability, and strong anti-interference ability.
[0029] See Figures 1-6As shown Figure 1 is a schematic diagram of a ranging circuit with dual timing and dual compensation provided by an embodiment of the present invention; Figure 2 is a circuit diagram of a front-end filtering circuit provided by an embodiment of the present invention;
[0030] Figure 3 is a circuit diagram of a comparator module provided by an embodiment of the present invention; Figure 4 is a circuit diagram of a time-to-digital conversion module provided by an embodiment of the present invention; Figure 5 is a circuit diagram of an analog-to-digital conversion module provided by an embodiment of the present invention; Figure 6 is a waveform schematic diagram of a received signal provided by an embodiment of the present invention.
[0031] The present invention provides a ranging circuit with dual timing and dual compensation, including: a front-end filtering circuit 1, an analog-to-digital conversion module 3, a time-to-digital conversion module 4, a comparator module 2, a control module 5, and a display module 6; the input end of the front-end filtering circuit 1 receives a ranging signal, the first output end of the front-end filtering circuit 1 is electrically connected to the input end of the analog-to-digital conversion module 3, and the second output end of the front-end filtering circuit 1 is electrically connected to the first input end of the comparator module 2; the output end of the analog-to-digital conversion module 3 is electrically connected to the input end of the control module 5, the output end of the comparator module 2 is electrically connected to the input end of the time-to-digital conversion module 4, the output end of the time-to-digital conversion module 4 is electrically connected to the input end of the control module 5, and the input end of the control module 5 is also fed back to the second input end of the comparator module 2; the output end of the control module 5 is electrically connected to the display module 6.
[0032] Among them, the received signal: in the ranging scenario, the emitted laser hits the ranging target and then returns to the photoelectric sensor, and the photoelectric sensor converts the optical signal into an electrical signal, and the electrical signal is amplified by the front-end amplifier circuit and then called the received signal.
[0033] Among them, the control module 5 is an MCU processor. The display module 6 is an LED display screen or an LCD display screen.
[0034] More specifically, the front-end filter circuit 1 includes: a first capacitor C14, a second capacitor C66, a first resistor R16, and a third capacitor C68; the first end of the first capacitor C14 serves as the input terminal (X1-2) of the front-end filter circuit 1, the second end of the first capacitor C14 is electrically connected to the first end of the second capacitor C66 and the first end of the first resistor R16 respectively, the second end of the second capacitor C66 is grounded, the second end of the first resistor R16 is electrically connected to the first end of the third capacitor C68, the second end of the first resistor R16 serves as the output terminal (SIG) of the front-end filter circuit 1, and the second end of the third capacitor C68 is grounded.
[0035] More specifically, the comparator module 2 includes: a second resistor R38, a third resistor R39, a fourth resistor R36, a fifth resistor R46, a fourth capacitor C61, a fifth capacitor C62, a sixth capacitor C64, a seventh capacitor C70, an eighth capacitor C71, and a comparator chip U14;
[0036] The first end of the second resistor R38 is electrically connected to the power supply, the second end of the second resistor R38 is electrically connected to the first end of the third resistor R39 and the first end of the fourth capacitor C61 respectively, the second end of the fourth capacitor C61 is electrically connected to the first end of the fourth resistor R36 and grounded, the second end of the fourth resistor R36 is electrically connected to the second end of the third resistor R39, the first end of the fifth capacitor C62, and the pin 3 of the comparator chip U14, and the second end of the fifth capacitor C62 serves as the first input terminal of the comparator module 2; the pin 1 of the comparator chip U14 serves as the output terminal of the comparator module 2;
[0037] The pin 2 of the comparator chip U14 is grounded, the pin 5 of the comparator chip U14 is electrically connected to the first end of the sixth capacitor C64 and the power supply (MUC-3.3V), the pin 4 of the comparator chip U14 is electrically connected to the first end of the fifth resistor R46 and the first end of the eighth capacitor C71 respectively, and the second end of the eighth capacitor C71 is grounded; the second end of the fifth resistor R46 is electrically connected to the first end of the seventh capacitor C70, and the second end of the seventh capacitor C70 is grounded; the first end of the seventh capacitor C70 also serves as the second input terminal of the comparator module 2.
[0038] More specifically, the model of the comparator chip U14 is the STM32G4 comparator.
[0039] More specifically, the analog-to-digital conversion module 3 includes: an ADC module chip U8, a ninth capacitor C20, and a tenth capacitor C21; the input terminal of the ADC module chip U8 serves as the input terminal of the analog-to-digital conversion module 3, the output terminal of the ADC module chip U8 serves as the output terminal of the analog-to-digital conversion module 3, the first ends of the ninth capacitor C20 and the tenth capacitor C21 are electrically connected to the reference voltage terminal of the ADC analog chip U8, and the second ends of the ninth capacitor C20 and the tenth capacitor C21 are electrically connected and grounded.
[0040] More specifically, the model of the ADC module chip U8 is the ADC0832CCN chip U8.
[0041] More specifically, the time-to-digital conversion module 4 includes: a TDC module chip U15, an eleventh capacitor C68, a twelfth capacitor C69, a thirteenth capacitor C72, a fourteenth capacitor C74, a sixth resistor R48, and a seventh resistor R51;
[0042] Pins 17 and 18 of the TDC module chip U15 serve as the input terminals of the time-to-digital conversion module 4, and pins 6 to 9 of the TDC module chip U15 serve as the output terminals of the time-to-digital conversion module 4;
[0043] The first ends of the eleventh capacitor C68 and the twelfth capacitor C69 are electrically connected to the power supply, and the second ends of the eleventh capacitor C68 and the twelfth capacitor C69 are electrically connected and grounded; the first end of the sixth resistor R48 is electrically connected to the first end of the twelfth capacitor C69 and pin 2 of the TDC module chip U15 respectively, the first end of the thirteenth capacitor C72 is electrically connected to the second end of the sixth resistor R48 and the first end of the fourteenth capacitor C74 respectively, and the second ends of the thirteenth capacitor C72 and the fourteenth capacitor C74 are electrically connected and grounded; the first end of the seventh resistor R51 is electrically connected to pin 4 of the TDC module chip U15, and the second end of the seventh resistor R51 is electrically connected to the power supply.
[0044] More specifically, the model of the TDC module chip U15 is the TDC-GP30 chip U15.
[0045] The working principle of the present utility model is as follows:
[0046] When the received signal is 3.3V, after passing through the front-end filter circuit, the signal is split into two. One end of the signal is input to the ADC. Since the input range of the ADC is only 1V, the signal collected by the ADC at this time is a full-scale signal. The MCU determines that the measurement target is a high-reflectivity object. Although the MCU cannot accurately calculate the distance, it can calculate the time window T of the distance range. The other end of the signal is input to the COPM comparator. Since the MCU has determined that the measurement target is a high-reflectivity object, the MCU will dynamically adjust the voltage of the feedback pin to make the signal output by the COPM comparator have less interference. After the TDC receives the signal output by the COMP comparator, the MCU will place the calculation window of the TDC near T0 calculated by the ADC, reducing the occupancy of the interference on the calculation window. The distance calculated by the MCU is compensated by a curve to obtain the distance S1, and the MCU displays the distance S1 on the display module.
[0047] When the received signal is lower than 1V, after passing through the front-end filter, the signal is split into two. One end of the signal is input to the ADC. At this time, the signal is lower than the input range of the ADC, and the MCU determines that the measurement target is a low-reflectivity object. The MCU processes the data collected by the ADC and calculates the distance S2 and the time window T1. The other end of the signal is input to the COPM comparator. Since the MCU has determined that the measurement target is a low-reflectivity object, the MCU will dynamically adjust the voltage of the feedback pin to make the quality of the signal output by the COPM comparator better. After the TDC receives the signal output by the COMP comparator, the MCU places the calculation window of the TDC near T1 calculated by the ADC and calculates the distance S3. The MCU comprehensively processes and curve-compensates S2 and S3 to obtain the distance S4, and the MCU displays the distance S4 on the display module.
[0048] It should be noted that the terms "including" and "having" and any variations thereof in the description, claims and drawings of the present invention are intended to cover non-exclusive inclusion. The terms "first", "second", etc. in the description, claims or drawings of the present invention are used to distinguish different objects, rather than to describe a specific order. The mention of "embodiment" in this article means that the specific features, structures or characteristics described in connection with the embodiment can be included in at least one embodiment of the present invention. The appearance of this phrase at various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.
[0049] The above are only the preferred embodiments of the present utility model and are not intended to limit the present utility model. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present utility model shall be included within the protection scope of the present utility model.
Claims
1. A dual timing and dual compensation ranging circuit, characterized in that: include: Front-end filtering circuit, analog-to-digital conversion module, time-to-digital conversion module, comparator module, control module and display module; The input end of the front-end filtering circuit receives the ranging signal, the first output end of the front-end filtering circuit is electrically connected to the input end of the analog-to-digital conversion module, and the second output end of the front-end filtering circuit is electrically connected to the first input end of the comparator module; the output end of the analog-to-digital conversion module is electrically connected to the input end of the control module, the output end of the comparator module is electrically connected to the input end of the time-to-digital conversion module, the output end of the time-to-digital conversion module is electrically connected to the input end of the control module, and the input end of the control module is also electrically connected to the second input end of the comparator module; the output end of the control module is electrically connected to the display module.
2. The dual timing and dual compensation ranging circuit as claimed in claim 1, characterized in that: The front-end filtering circuit includes: a first capacitor, a second capacitor, a first resistor and a third capacitor; the first end of the first capacitor serves as the input end of the front-end filtering circuit, the second end of the first capacitor is electrically connected to the first end of the second capacitor and the first end of the first resistor respectively, the second end of the second capacitor is grounded, the second end of the first resistor is electrically connected to the first end of the third capacitor, the second end of the first resistor serves as the output end of the front-end filtering circuit, and the second end of the third capacitor is grounded.
3. The dual timing and dual compensation ranging circuit as claimed in claim 1, characterized in that: The comparator module includes: a second resistor, a third resistor, a fourth resistor, a fifth resistor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor and a comparison chip; The first end of the second resistor is electrically connected to the power supply, the second end of the second resistor is electrically connected to the first end of the third resistor and the first end of the fourth capacitor respectively, the second end of the fourth capacitor is electrically connected to the first end of the fourth resistor and is grounded, the second end of the fourth resistor is electrically connected to the second end of the third resistor, the first end of the fifth capacitor and the pin 3 of the comparison chip respectively, the second end of the fifth capacitor serves as the first input end of the comparator module; the pin 1 of the comparison chip serves as the output end of the comparator module; Pin 2 of the comparison chip is grounded, pin 5 of the comparison chip is electrically connected to the first end of the sixth capacitor and the power supply, respectively, pin 4 of the comparison chip is electrically connected to the first end of the fifth resistor and the first end of the eighth capacitor, respectively, and the second end of the eighth capacitor is grounded; the second end of the fifth resistor is electrically connected to the first end of the seventh capacitor, and the second end of the seventh capacitor is grounded; the first end of the seventh capacitor serves as the second input end of the comparator module.
4. The dual timing and dual compensation ranging circuit as claimed in claim 3, characterized in that: The model of the comparison chip is STM32G4 comparator.
5. The dual timing and dual compensation ranging circuit as claimed in claim 1, characterized in that: The analog-to-digital conversion module includes: an ADC module chip, a ninth capacitor and a tenth capacitor; the input end of the ADC module chip serves as the input end of the analog-to-digital conversion module, the output end of the ADC module chip serves as the output end of the analog-to-digital conversion module, the first end of the ninth capacitor and the first end of the tenth capacitor are electrically connected to the reference voltage end of the ADC module chip, and the second end of the ninth capacitor and the second end of the tenth capacitor are electrically connected and grounded.
6. The dual timing and dual compensation ranging circuit as claimed in claim 5, characterized in that: The model of the ADC module chip is ADC0832CCN chip.
7. The dual timing and dual compensation ranging circuit as claimed in claim 1, characterized in that: The time-to-digital conversion module includes: a TDC module chip, an eleventh capacitor, a twelfth capacitor, a thirteenth capacitor, a fourteenth capacitor, a sixth resistor and a seventh resistor; Pins 17 and 18 of the TDC module chip serve as input terminals of the time-to-digital conversion module, and pins 6 to 9 of the TDC module chip serve as output terminals of the time-to-digital conversion module; The first end of the eleventh capacitor and the first end of the twelfth capacitor are electrically connected to the power supply, and the second end of the eleventh capacitor is electrically connected to the second end of the twelfth capacitor and grounded; the first end of the sixth resistor is electrically connected to the first end of the twelfth capacitor and pin 2 of the TDC module chip, respectively, the first end of the thirteenth capacitor is electrically connected to the second end of the sixth resistor and the first end of the fourteenth capacitor, respectively, the second end of the thirteenth capacitor is electrically connected to the second end of the fourteenth capacitor and grounded; the first end of the seventh resistor is electrically connected to pin 4 of the TDC module chip, and the second end of the seventh resistor is electrically connected to the power supply.
8. The dual timing and dual compensation ranging circuit as claimed in claim 7, characterized in that: The model of the TDC module chip is TDC-GP30 chip.